Add memory barrier instructions to the RVDS CM3 ports.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@1861 1d2547de-c912-0410-9cb9-b8ca96c0e9e2

diff --git a/FreeRTOS/Source/portable/RVDS/ARM_CM3/port.c b/FreeRTOS/Source/portable/RVDS/ARM_CM3/port.c
index fb58a6a3e928c21399728753032bce5a2b714b5d..bed6025091a531bda0866c78671e5ff2ac2bc6fc 100644 (file)
--- a/FreeRTOS/Source/portable/RVDS/ARM_CM3/port.c
+++ b/FreeRTOS/Source/portable/RVDS/ARM_CM3/port.c
@@ -56,19 +56,19 @@
     ***************************************************************************\r
 \r
 \r
-    http://www.FreeRTOS.org - Documentation, books, training, latest versions, \r
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
     license and Real Time Engineers Ltd. contact details.\r
 \r
     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
     including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
     fully thread aware and reentrant UDP/IP stack.\r
 \r
-    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High \r
-    Integrity Systems, who sell the code with commercial support, \r
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+    Integrity Systems, who sell the code with commercial support,\r
     indemnification and middleware, under the OpenRTOS brand.\r
-    \r
-    http://www.SafeRTOS.com - High Integrity Systems also provide a safety \r
-    engineered and independently SIL3 certified version for use in safety and \r
+\r
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+    engineered and independently SIL3 certified version for use in safety and\r
     mission critical applications that require provable dependability.\r
 */\r
 \r
@@ -105,14 +105,12 @@ is defined. */
 #define portNVIC_SYSTICK_CTRL_REG                      ( * ( ( volatile unsigned long * ) 0xe000e010 ) )\r
 #define portNVIC_SYSTICK_LOAD_REG                      ( * ( ( volatile unsigned long * ) 0xe000e014 ) )\r
 #define portNVIC_SYSTICK_CURRENT_VALUE_REG     ( * ( ( volatile unsigned long * ) 0xe000e018 ) )\r
-#define portNVIC_INT_CTRL_REG                          ( * ( ( volatile unsigned long * ) 0xe000ed04 ) )\r
 #define portNVIC_SYSPRI2_REG                           ( * ( ( volatile unsigned long * ) 0xe000ed20 ) )\r
 /* ...then bits in the registers. */\r
 #define portNVIC_SYSTICK_CLK_BIT                       ( 1UL << 2UL )\r
 #define portNVIC_SYSTICK_INT_BIT                       ( 1UL << 1UL )\r
 #define portNVIC_SYSTICK_ENABLE_BIT                    ( 1UL << 0UL )\r
 #define portNVIC_SYSTICK_COUNT_FLAG_BIT                ( 1UL << 16UL )\r
-#define portNVIC_PENDSVSET_BIT                         ( 1UL << 28UL )\r
 #define portNVIC_PENDSVCLEAR_BIT                       ( 1UL << 27UL )\r
 #define portNVIC_PEND_SYSTICK_CLEAR_BIT                ( 1UL << 25UL )\r
 \r
@@ -122,6 +120,9 @@ is defined. */
 /* Constants required to set up the initial stack. */\r
 #define portINITIAL_XPSR                       ( 0x01000000 )\r
 \r
+/* Constants used with memory barrier intrinsics. */\r
+#define portSY_FULL_READ_WRITE         ( 15 )\r
+\r
 /* Each task maintains its own interrupt status in the critical nesting\r
 variable. */\r
 static unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa;\r
@@ -258,10 +259,15 @@ void vPortEndScheduler( void )
 }\r
 /*-----------------------------------------------------------*/\r
 \r
-void vPortYieldFromISR( void )\r
+void vPortYield( void )\r
 {\r
        /* Set a PendSV to request a context switch. */\r
        portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
+\r
+       /* Barriers are normally not required but do ensure the code is completely\r
+       within the specified behaviour for the architecture. */\r
+       __dsb( portSY_FULL_READ_WRITE );\r
+       __isb( portSY_FULL_READ_WRITE );\r
 }\r
 /*-----------------------------------------------------------*/\r
 \r
@@ -269,6 +275,8 @@ void vPortEnterCritical( void )
 {\r
        portDISABLE_INTERRUPTS();\r
        uxCriticalNesting++;\r
+       __dsb( portSY_FULL_READ_WRITE );\r
+       __isb( portSY_FULL_READ_WRITE );\r
 }\r
 /*-----------------------------------------------------------*/\r
 \r
@@ -376,7 +384,7 @@ void xPortSysTickHandler( void )
                /* Enter a critical section but don't use the taskENTER_CRITICAL()\r
                method as that will mask interrupts that should exit sleep mode. */\r
                __disable_irq();\r
-               \r
+\r
                /* If a context switch is pending or a task is waiting for the scheduler\r
                to be unsuspended then abandon the low power entry. */\r
                if( eTaskConfirmSleepModeStatus() == eAbortSleep )\r
@@ -384,7 +392,7 @@ void xPortSysTickHandler( void )
                        /* Restart SysTick. */\r
                        portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
 \r
-                       /* Re-enable interrupts - see comments above __disable_irq() call \r
+                       /* Re-enable interrupts - see comments above __disable_irq() call\r
                        above. */\r
                        __enable_irq();\r
                }\r
@@ -410,6 +418,8 @@ void xPortSysTickHandler( void )
                        if( xModifiableIdleTime > 0 )\r
                        {\r
                                __wfi();\r
+                               __dsb( portSY_FULL_READ_WRITE );\r
+                               __isb( portSY_FULL_READ_WRITE );\r
                        }\r
                        configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\r
 \r
@@ -419,7 +429,7 @@ void xPortSysTickHandler( void )
                        kernel with respect to calendar time. */\r
                        portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\r
 \r
-                       /* Re-enable interrupts - see comments above __disable_irq() call \r
+                       /* Re-enable interrupts - see comments above __disable_irq() call\r
                        above. */\r
                        __enable_irq();\r
 \r

diff --git a/FreeRTOS/Source/portable/RVDS/ARM_CM3/portmacro.h b/FreeRTOS/Source/portable/RVDS/ARM_CM3/portmacro.h
index 98757a43042e11f3d8447419413e18d3c6ca09a9..83e5dde00e756c6e021554c9862e566560833b9d 100644 (file)
--- a/FreeRTOS/Source/portable/RVDS/ARM_CM3/portmacro.h
+++ b/FreeRTOS/Source/portable/RVDS/ARM_CM3/portmacro.h
@@ -56,19 +56,19 @@
     ***************************************************************************\r
 \r
 \r
-    http://www.FreeRTOS.org - Documentation, books, training, latest versions, \r
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
     license and Real Time Engineers Ltd. contact details.\r
 \r
     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
     including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
     fully thread aware and reentrant UDP/IP stack.\r
 \r
-    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High \r
-    Integrity Systems, who sell the code with commercial support, \r
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+    Integrity Systems, who sell the code with commercial support,\r
     indemnification and middleware, under the OpenRTOS brand.\r
-    \r
-    http://www.SafeRTOS.com - High Integrity Systems also provide a safety \r
-    engineered and independently SIL3 certified version for use in safety and \r
+\r
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+    engineered and independently SIL3 certified version for use in safety and\r
     mission critical applications that require provable dependability.\r
 */\r
 \r
@@ -116,9 +116,10 @@ extern "C" {
 \r
 /* Scheduler utilities. */\r
 extern void vPortYield( void );\r
-extern void vPortYieldFromISR( void );\r
-#define portYIELD()                                    vPortYieldFromISR()\r
-#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) vPortYieldFromISR()\r
+#define portNVIC_INT_CTRL_REG          ( * ( ( volatile unsigned long * ) 0xe000ed04 ) )\r
+#define portNVIC_PENDSVSET_BIT         ( 1UL << 28UL )\r
+#define portYIELD()                                    vPortYield()\r
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT\r
 /*-----------------------------------------------------------*/\r
 \r
 /* Critical section management. */\r

diff --git a/FreeRTOS/Source/portable/RVDS/ARM_CM4F/port.c b/FreeRTOS/Source/portable/RVDS/ARM_CM4F/port.c
index 591c725ceb921fa609dfce9943cb5b4d26a1e86b..d6ab1b08ac5219239b86e650314ad7c839410c7f 100644 (file)
--- a/FreeRTOS/Source/portable/RVDS/ARM_CM4F/port.c
+++ b/FreeRTOS/Source/portable/RVDS/ARM_CM4F/port.c
@@ -56,19 +56,19 @@
     ***************************************************************************\r
 \r
 \r
-    http://www.FreeRTOS.org - Documentation, books, training, latest versions, \r
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
     license and Real Time Engineers Ltd. contact details.\r
 \r
     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
     including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
     fully thread aware and reentrant UDP/IP stack.\r
 \r
-    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High \r
-    Integrity Systems, who sell the code with commercial support, \r
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+    Integrity Systems, who sell the code with commercial support,\r
     indemnification and middleware, under the OpenRTOS brand.\r
-    \r
-    http://www.SafeRTOS.com - High Integrity Systems also provide a safety \r
-    engineered and independently SIL3 certified version for use in safety and \r
+\r
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+    engineered and independently SIL3 certified version for use in safety and\r
     mission critical applications that require provable dependability.\r
 */\r
 \r
@@ -105,14 +105,12 @@ is defined. */
 #define portNVIC_SYSTICK_CTRL_REG                      ( * ( ( volatile unsigned long * ) 0xe000e010 ) )\r
 #define portNVIC_SYSTICK_LOAD_REG                      ( * ( ( volatile unsigned long * ) 0xe000e014 ) )\r
 #define portNVIC_SYSTICK_CURRENT_VALUE_REG     ( * ( ( volatile unsigned long * ) 0xe000e018 ) )\r
-#define portNVIC_INT_CTRL_REG                          ( * ( ( volatile unsigned long * ) 0xe000ed04 ) )\r
 #define portNVIC_SYSPRI2_REG                           ( * ( ( volatile unsigned long * ) 0xe000ed20 ) )\r
 /* ...then bits in the registers. */\r
 #define portNVIC_SYSTICK_CLK_BIT                       ( 1UL << 2UL )\r
 #define portNVIC_SYSTICK_INT_BIT                       ( 1UL << 1UL )\r
 #define portNVIC_SYSTICK_ENABLE_BIT                    ( 1UL << 0UL )\r
 #define portNVIC_SYSTICK_COUNT_FLAG_BIT                ( 1UL << 16UL )\r
-#define portNVIC_PENDSVSET_BIT                         ( 1UL << 28UL )\r
 #define portNVIC_PENDSVCLEAR_BIT                       ( 1UL << 27UL )\r
 #define portNVIC_PEND_SYSTICK_CLEAR_BIT                ( 1UL << 25UL )\r
 \r
@@ -127,6 +125,9 @@ is defined. */
 #define portINITIAL_XPSR                       ( 0x01000000 )\r
 #define portINITIAL_EXEC_RETURN                ( 0xfffffffd )\r
 \r
+/* Constants used with memory barrier intrinsics. */\r
+#define portSY_FULL_READ_WRITE         ( 15 )\r
+\r
 /* Each task maintains its own interrupt status in the critical nesting\r
 variable. */\r
 static unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa;\r
@@ -302,10 +303,15 @@ void vPortEndScheduler( void )
 }\r
 /*-----------------------------------------------------------*/\r
 \r
-void vPortYieldFromISR( void )\r
+void vPortYield( void )\r
 {\r
        /* Set a PendSV to request a context switch. */\r
        portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
+\r
+       /* Barriers are normally not required but do ensure the code is completely\r
+       within the specified behaviour for the architecture. */\r
+       __dsb( portSY_FULL_READ_WRITE );\r
+       __isb( portSY_FULL_READ_WRITE );\r
 }\r
 /*-----------------------------------------------------------*/\r
 \r
@@ -313,6 +319,8 @@ void vPortEnterCritical( void )
 {\r
        portDISABLE_INTERRUPTS();\r
        uxCriticalNesting++;\r
+       __dsb( portSY_FULL_READ_WRITE );\r
+       __isb( portSY_FULL_READ_WRITE );\r
 }\r
 /*-----------------------------------------------------------*/\r
 \r
@@ -439,7 +447,7 @@ void xPortSysTickHandler( void )
                /* Enter a critical section but don't use the taskENTER_CRITICAL()\r
                method as that will mask interrupts that should exit sleep mode. */\r
                __disable_irq();\r
-               \r
+\r
                /* If a context switch is pending or a task is waiting for the scheduler\r
                to be unsuspended then abandon the low power entry. */\r
                if( eTaskConfirmSleepModeStatus() == eAbortSleep )\r
@@ -447,7 +455,7 @@ void xPortSysTickHandler( void )
                        /* Restart SysTick. */\r
                        portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
 \r
-                       /* Re-enable interrupts - see comments above __disable_irq() call \r
+                       /* Re-enable interrupts - see comments above __disable_irq() call\r
                        above. */\r
                        __enable_irq();\r
                }\r
@@ -473,6 +481,8 @@ void xPortSysTickHandler( void )
                        if( xModifiableIdleTime > 0 )\r
                        {\r
                                __wfi();\r
+                               __dsb( portSY_FULL_READ_WRITE );\r
+                               __isb( portSY_FULL_READ_WRITE );\r
                        }\r
                        configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\r
 \r
@@ -482,7 +492,7 @@ void xPortSysTickHandler( void )
                        kernel with respect to calendar time. */\r
                        portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\r
 \r
-                       /* Re-enable interrupts - see comments above __disable_irq() call \r
+                       /* Re-enable interrupts - see comments above __disable_irq() call\r
                        above. */\r
                        __enable_irq();\r
 \r

diff --git a/FreeRTOS/Source/portable/RVDS/ARM_CM4F/portmacro.h b/FreeRTOS/Source/portable/RVDS/ARM_CM4F/portmacro.h
index f377c891f6c4b19ba978c8a5b02e45913237f039..1438d90e973270bff81ee00d361f2eb6ef2c9766 100644 (file)
--- a/FreeRTOS/Source/portable/RVDS/ARM_CM4F/portmacro.h
+++ b/FreeRTOS/Source/portable/RVDS/ARM_CM4F/portmacro.h
@@ -116,9 +116,10 @@ extern "C" {
 \r
 /* Scheduler utilities. */\r
 extern void vPortYield( void );\r
-extern void vPortYieldFromISR( void );\r
-#define portYIELD()                                    vPortYieldFromISR()\r
-#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) vPortYieldFromISR()\r
+#define portNVIC_INT_CTRL_REG          ( * ( ( volatile unsigned long * ) 0xe000ed04 ) )\r
+#define portNVIC_PENDSVSET_BIT         ( 1UL << 28UL )\r
+#define portYIELD()                                    vPortYield()\r
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT\r
 /*-----------------------------------------------------------*/\r
 \r
 /* Critical section management. */\r