Correct addessing errors in platform files.
Split off common core module data from Integrator header files to
include/armcoremodule.h.
Patch by Peter Pearse, 04 Oct 2005
Changes for U-Boot 1.1.4:
======================================================================
+* Cleanup
+
+* Update ARM Integrator boards:
+ Correct addessing errors in platform files.
+ Split off common core module data from Integrator header files to
+ include/armcoremodule.h.
+ Patch by Peter Pearse, 04 Oct 2005
+
* Make sure only supported compiler options are used
Import "cc-option" shell function from kernel and
use it to get the correct ARM GCC options for individual CPUs
Patch by Peter Pearse, 30 Jun 2005
* Fix 440GR to print correct cpu revision
- Patch by Stefan Roese, 4 Oct 2005
+ Patch by Stefan Roese, 04 Oct 2005
* Change board message on AMCC Yosemite & Yellowstone to common style
- Patch by Stefan Roese, 3 Oct 2005
+ Patch by Stefan Roese, 03 Oct 2005
* Fix compiler warning
{
return CFG_HZ_CLOCK/div_clock;
}
+
+/* The Integrator/AP timer1 is clocked at 24MHz
+ * can be divided by 16 or 256
+ * and is a 16-bit counter
+ */
mov r0, #CM_BASE
ldr r1,[r0,#OS_CTRL]
orr r1,r1,#CMMASK_RESET
- str r1,[r0]
+ str r1,[r0,#OS_CTRL]
reset_failed:
b reset_failed
beq init_reg_OK
/* lock for change */
- mov r3, #CMVAL_LOCK
- and r3,r3,#CMMASK_LOCK
+ mov r3, #CMVAL_LOCK1
+ add r3,r3,#CMVAL_LOCK2
str r3, [r0, #OS_LOCK]
/* set desired value */
orr r1,r1,r2
mov r0, #CM_BASE
ldr r1,[r0,#OS_CTRL]
orr r1,r1,#CMMASK_RESET
- str r1,[r0]
+ str r1,[r0,#OS_CTRL]
reset_failed:
b reset_failed
#if !defined (CONFIG_CM920T) && !defined (CONFIG_CM920T_ETM) && \
!defined (CONFIG_CM940T)
+ /* CMxx6 code */
#ifdef CONFIG_CM_MULTIPLE_SSRAM
/* set simple mapping */
beq init_reg_OK
/* lock for change */
- mov r3, #CMVAL_LOCK
- and r3,r3,#CMMASK_LOCK
+ mov r3, #CMVAL_LOCK1
+ and r3, r3, #CMVAL_LOCK2
str r3, [r0, #OS_LOCK]
/* set desired value */
orr r1,r1,r2
# only supported compiler options are used
#
cc-option = $(shell if $(CC) $(CFLAGS) $(1) -S -o /dev/null -xc /dev/null \
- > /dev/null 2>&1; then echo "$(1)"; else echo "$(2)"; fi ;)
+ > /dev/null 2>&1; then echo "$(1)"; else echo "$(2)"; fi ;)
#
# Include the make variables (CC, etc...)
# =========================================================================
PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
-
# =========================================================================
PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
-
# =========================================================================
PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
-
# =========================================================================
PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
-
# =========================================================================
PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
-
# =========================================================================
PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
-
# ========================================================================
PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
-
# ========================================================================
PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
-
# ========================================================================
PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
-
# ========================================================================
PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
-
SDRAM
RAM controllers
clock generators etc.
+CMs may be fitted with varying amounts of SDRAM using a DIMM socket.
Boot Methods :
------------
--- /dev/null
+/*
+ * (C) Copyright 2005
+ * ARM Ltd.
+ * Peter Pearse, <Peter.Pearse@arm.com>
+ * Configuration for ARM Core Modules.
+ * No standalonw port yet available
+ * - this file is included by both integratorap.h & integratorcp.h
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ARMCOREMODULE_H
+#define __ARMCOREMODULE_H
+
+#define CM_BASE 0x10000000
+
+/* CM registers common to all CMs */
+/* Note that observed values after reboot into the ARM Boot Monitor
+ have been used as defaults, rather than the POR values */
+#define OS_CTRL 0x0000000C
+#define CMMASK_REMAP 0x00000005 /* set remap & led */
+#define CMMASK_RESET 0x00000008
+#define OS_LOCK 0x00000014
+#define CMVAL_LOCK1 0x0000A000 /* locking value */
+#define CMVAL_LOCK2 0x0000005F /* locking value */
+#define CMVAL_UNLOCK 0x00000000 /* any value != CM_LOCKVAL */
+#define OS_SDRAM 0x00000020
+#define OS_INIT 0x00000024
+#define CMMASK_MAP_SIMPLE 0xFFFDFFFF /* simple mapping */
+#define CMMASK_TCRAM_DISABLE 0xFFFEFFFF /* TCRAM disabled */
+#define CMMASK_LOWVEC 0x00000000 /* vectors @ 0x00000000 */
+#define CMMASK_LE 0xFFFFFFF7 /* little endian */
+#define CMMASK_CMxx6_COMMON 0x00000013 /* Common value for CMxx6 */
+ /* - observed reset value of */
+ /* CM926EJ-S */
+ /* CM1136-EJ-S */
+
+#if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E)
+#define CMMASK_INIT_102 0x00000300 /* see CM102xx ref manual */
+ /* - PLL test clock bypassed */
+ /* - bus clock ratio 2 */
+ /* - little endian */
+ /* - vectors at zero */
+#endif /* CM1022xx */
+
+/* Determine CM characteristics */
+
+#undef CONFIG_CM_MULTIPLE_SSRAM
+#undef CONFIG_CM_SPD_DETECT
+#undef CONFIG_CM_REMAP
+#undef CONFIG_CM_INIT
+#undef CONFIG_CM_TCRAM
+
+#if defined (CONFIG_CM946E_S) || defined (CONFIG_CM966E_S)
+#define CONFIG_CM_MULTIPLE_SSRAM /* CM has multiple SSRAM mapping */
+#endif
+
+/* Excalibur core module has reduced functionality */
+#ifndef CONFIG_CM922T_XA10
+#define CONFIG_CM_SPD_DETECT /* CM supports SPD query */
+#define OS_SPD 0x00000100 /* Address of SPD data */
+#define CONFIG_CM_REMAP /* CM supports remapping */
+#define CONFIG_CM_INIT /* CM has initialization reg */
+#endif /* NOT EXCALIBUR */
+
+#if defined(CONFIG_CM926EJ_S) || defined (CONFIG_CM946E_S) || \
+ defined(CONFIG_CM966E_S) || defined (CONFIG_CM1026EJ_S) || \
+ defined(CONFIG_CM1136JF_S)
+#define CONFIG_CM_TCRAM /* CM has TCRAM */
+#endif
+
+#ifdef CONFIG_CM_SPD_DETECT
+#define OS_SPD 0x00000100 /* The SDRAM SPD data is copied here */
+#endif
+
+#endif /* __ARMCOREMODULE_H */
* to define the necessary CONFIG_ s for the CM involved
* see e.g. integratorcp_CM926EJ-S_config
*/
+#include "armcoremodule.h"
-#define CM_BASE 0x10000000
-
-/* CM registers common to all integrator/CP CMs */
-#define OS_CTRL 0x0000000C
-#define CMMASK_REMAP 0x00000005 /* Set remap & led */
-#define CMMASK_RESET 0x00000008
-#define OS_LOCK 0x00000014
-#define CMVAL_LOCK 0x0000A000 /* Locking value */
-#define CMMASK_LOCK 0x0000005F /* Locking value */
-#define CMVAL_UNLOCK 0x00000000 /* Any value != CM_LOCKVAL */
-#define OS_SDRAM 0x00000020
-#define OS_INIT 0x00000024
-#define CMMASK_MAP_SIMPLE 0xFFFDFFFF /* simple mapping */
-#define CMMASK_TCRAM_DISABLE 0xFFFEFFFF /* TCRAM disabled */
-#define CMMASK_LOWVEC 0x00000004 /* vectors @ 0x00000000 */
-
-#ifdef CONFIG_CM_SPD_DETECT
-#define OS_SPD 0x00000100 /* The SDRAM SPD data is copied here */
-#endif
-
-#if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E)
-#define CMMASK_INIT_102 0x00000300 /* see CM102xx ref manual
- * - PLL test clock bypassed
- * - bus clock ratio 2
- * - little endian
- * - vectors at zero
- */
-#endif /* CM1022xx */
-
-#define CMMASK_LE 0x00000008 /* little endian */
-#define CMMASK_CMxx6_COMMON 0x00000100 /* Common value for CMxx6
- * - divisor/ratio b00000001
- * bx
- * - HCLKDIV b000
- * bxx
- * - PLL BYPASS b00
- */
#endif /* __CONFIG_H */
#define CONFIG_PL01x_PORTS { (void *)CFG_SERIAL0, (void *)CFG_SERIAL1 }
#define CONFIG_CONS_INDEX 0
#define CONFIG_BAUDRATE 38400
-#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CFG_SERIAL0 0x16000000
#define CFG_SERIAL1 0x17000000
#if 0
#define CONFIG_BOOTDELAY 2
-#define CONFIG_BOOTARGS "root=/dev/nfs mem=128M ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0"
+#define CONFIG_BOOTARGS "root=/dev/nfs nfsroot=<IP address>:/<exported rootfs> mem=128M ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0"
#define CONFIG_BOOTCOMMAND "bootp ; bootm"
#endif
+/* The kernel command line & boot command below are for a platform flashed with afu.axf
+
+Image 666 Block 0 End Block 0 address 0x24000000 exec 0x24000000- name u-boot
+Image 667 Block 1 End Block 13 address 0x24040000 exec 0x24040000- name u-linux
+Image 668 Block 14 End Block 33 address 0x24380000 exec 0x24380000- name rootfs
+SIB at Block62 End Block62 address 0x24f80000
-/* Flash loaded
- - U-Boot
- - u-linux
- - system.cramfs
*/
#define CONFIG_BOOTDELAY 2
-#define CONFIG_BOOTARGS "root=/dev/mtdblock2 mem=128M ip=dhcp netdev=27,0, \
-0xfc800000,0xfc800010,eth0 video=clcdfb:0"
-#define CONFIG_BOOTCOMMAND "cp 0x24040000 0x7fc0 0x80000; bootm"
+#define CONFIG_BOOTARGS "root=/dev/mtdblock2 mem=128M ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0 console=ttyAMA0"
+#define CONFIG_BOOTCOMMAND "cp 0x24080000 0x7fc0 0x100000; bootm"
/*
* Miscellaneous configurable options
*/
-#define CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT "Integrator-CP # " /* Monitor Command Prompt */
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "Integrator-CP # " /* Monitor Command Prompt */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size*/
/* Print Buffer Size */
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size*/
#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
#define CFG_LOAD_ADDR 0x7fc0 /* default load address */
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
-#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
/*-----------------------------------------------------------------------
* FLASH and environment organization
+
+ * Top varies according to amount fitted
+ * Reserve top 4 blocks of flash
+ * - ARM Boot Monitor
+ * - Unused
+ * - SIB block
+ * - U-Boot environment
+ *
+ * Base is always 0x24000000
+
*/
-#define CFG_FLASH_BASE 0x24000000
+#define CFG_FLASH_BASE 0x24000000
#define CFG_MAX_FLASH_SECT 64
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define PHYS_FLASH_SIZE 0x01000000 /* 16MB */
+#define PHYS_FLASH_SIZE 0x01000000 /* 16MB */
#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
-#define CFG_MONITOR_BASE 0x24F40000
-#define CFG_ENV_IS_IN_FLASH
+#define CFG_MONITOR_LEN 0x00100000
+#define CFG_ENV_IS_IN_FLASH (1)
+
+/*
+ * Move up the U-Boot & monitor area if more flash is fitted.
+ * If this U-Boot is to be run on Integrators with varying flash sizes,
+ * drivers/cfi_flash.c::flash_init() can read the Integrator CP_FLASHPROG
+ * register and dynamically assign CFG_ENV_ADDR & CFG_MONITOR_BASE
+ * - CFG_MONITOR_BASE is set to indicate that the environment is not
+ * embedded in the boot monitor(s) area
+ */
+#if ( PHYS_FLASH_SIZE == 0x04000000 )
+
+#define CFG_ENV_ADDR 0x27F00000
+#define CFG_MONITOR_BASE 0x27F40000
+
+#elif (PHYS_FLASH_SIZE == 0x02000000 )
+
+#define CFG_ENV_ADDR 0x25F00000
+#define CFG_MONITOR_BASE 0x25F40000
+
+#else
+
#define CFG_ENV_ADDR 0x24F00000
+#define CFG_MONITOR_BASE 0x27F40000
+
+#endif
+
#define CFG_ENV_SECT_SIZE 0x40000 /* 256KB */
#define CFG_ENV_SIZE 8192 /* 8KB */
+/*-----------------------------------------------------------------------
+ * CP control registers
+ */
+#define CPCR_BASE 0xCB000000 /* CP Registers*/
+#define OS_FLASHPROG 0x00000004 /* Flash register*/
+#define CPMASK_EXTRABANK 0x8
+#define CPMASK_FLASHSIZE 0x4
+#define CPMASK_FLWREN 0x2
+#define CPMASK_FLVPPEN 0x1
+
+/*
+ * The ARM boot monitor initializes the board.
+ * However, the default U-Boot code also performs the initialization.
+ * If desired, this can be prevented by defining SKIP_LOWLEVEL_INIT
+ * - see documentation supplied with board for details of how to choose the
+ * image to run at reset/power up
+ * e.g. whether the ARM Boot Monitor runs before U-Boot
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+ */
+
+/*
+ * The ARM boot monitor does not relocate U-Boot.
+ * However, the default U-Boot code performs the relocation check,
+ * and may relocate the code if the memory map is changed.
+ * If necessary this can be prevented by defining SKIP_RELOCATE_UBOOT
+
+#define SKIP_CONFIG_RELOCATE_UBOOT
+
+ */
/*-----------------------------------------------------------------------
* There are various dependencies on the core module (CM) fitted
* Users should refer to their CM user guide
* - when porting adjust u-boot/Makefile accordingly
- * to define the necessary CONFIG_ s for the CM involved
- * see e.g. integratorcp_CM926EJ-S_config
+ * to define the necessary CONFIG_ s for the CM involved
+ * see e.g. cp_926ejs_config
*/
-#define CM_BASE 0x10000000
-
-/* CM registers common to all integrator/CP CMs */
-#define OS_CTRL 0x0000000C
-#define CMMASK_REMAP 0x00000005 /* set remap & led */
-#define CMMASK_RESET 0x00000008
-#define OS_LOCK 0x00000014
-#define CMVAL_LOCK 0x0000A000 /* locking value */
-#define CMMASK_LOCK 0x0000005F /* locking value */
-#define CMVAL_UNLOCK 0x00000000 /* any value != CM_LOCKVAL */
-#define OS_SDRAM 0x00000020
-#define OS_INIT 0x00000024
-#define CMMASK_MAP_SIMPLE 0xFFFDFFFF /* simple mapping */
-#define CMMASK_TCRAM_DISABLE 0xFFFEFFFF /* TCRAM disabled */
-#define CMMASK_LOWVEC 0x00000004 /* vectors @ 0x00000000 */
-#if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E)
-#define CMMASK_INIT_102 0x00000300 /* see CM102xx ref manual
- * - PLL test clock bypassed
- * - bus clock ratio 2
- * - little endian
- * - vectors at zero
- */
-#endif /* CM1022xx */
-
-#define CMMASK_LE 0x00000008 /* little endian */
-#define CMMASK_CMxx6_COMMON 0x00000100 /* Common value for CMxx6
- * - divisor/ratio b00000001
- * bx
- * - HCLKDIV b000
- * bxx
- * - PLL BYPASS b00
- */
-
-/* Determine CM characteristics */
-
-#undef CONFIG_CM_MULTIPLE_SSRAM
-#undef CONFIG_CM_SPD_DETECT
-#undef CONFIG_CM_REMAP
-#undef CONFIG_CM_INIT
-#undef CONFIG_CM_TCRAM
-
-#if defined (CONFIG_CM946E_S) || defined (CONFIG_CM966E_S)
-#define CONFIG_CM_MULTIPLE_SSRAM /* CM has multiple SSRAM mapping */
-#endif
-
-#ifndef CONFIG_CM922t_XA10
-#define CONFIG_CM_SPD_DETECT /* CM supports SPD query */
-#define OS_SPD 0x00000100 /* Address of SPD data */
-#define CONFIG_CM_REMAP /* CM supports remapping */
-#define CONFIG_CM_INIT /* CM has initialization reg */
-#endif
+#include "armcoremodule.h"
-#if defined(CONFIG_CM926EJ_S) || defined (CONFIG_CM946E_S) || \
- defined(CONFIG_CM966E_S) || defined (CONFIG_CM1026EJ_S) || \
- defined(CONFIG_CM1136JF_S)
-#define CONFIG_CM_TCRAM /* CM has TCRAM */
-#endif
+/*
+ * If CONFIG_SKIP_LOWLEVEL_INIT is not defined &
+ * the core module has a CM_INIT register
+ * then the U-Boot initialisation code will
+ * e.g. ARM Boot Monitor or pre-loader is repeated once
+ * (to re-initialise any existing CM_INIT settings to safe values).
+ *
+ * This is usually not the desired behaviour since the platform
+ * will either reboot into the ARM monitor (or pre-loader)
+ * or continuously cycle thru it without U-Boot running,
+ * depending upon the setting of Integrator/CP switch S2-4.
+ *
+ * However it may be needed if Integrator/CP switch S2-1
+ * is set OFF to boot direct into U-Boot.
+ * In that case comment out the line below.
+#undef CONFIG_CM_INIT
+ */
#endif /* __CONFIG_H */
projects / u-boot / commitdiff