mmc: s5p_sdhci: add the s5p_sdhci_core_init function

To reuse the code, added the s5p_sdhci_core_init function.
Before applied this patch, didn't use the 8-bit mode at exynos baord.
Because it didn't set "MMC_MODE_8BIT".

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/drivers/mmc/s5p_sdhci.c b/drivers/mmc/s5p_sdhci.c
index ccae4ccae15638410eb73c9766ee07467164f0a4..2ff0ec2a4221dad2c4e1c00bddba3f28374a1e35 100644 (file)
--- a/drivers/mmc/s5p_sdhci.c
+++ b/drivers/mmc/s5p_sdhci.c
@@ -65,17 +65,9 @@ static void s5p_sdhci_set_control_reg(struct sdhci_host *host)
        sdhci_writel(host, ctrl, SDHCI_CONTROL2);
 }
 
-int s5p_sdhci_init(u32 regbase, int index, int bus_width)
+static int s5p_sdhci_core_init(struct sdhci_host *host)
 {
-       struct sdhci_host *host = NULL;
-       host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host));
-       if (!host) {
-               printf("sdhci__host malloc fail!\n");
-               return 1;
-       }
-
        host->name = S5P_NAME;
-       host->ioaddr = (void *)regbase;
 
        host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE |
                SDHCI_QUIRK_BROKEN_R1B | SDHCI_QUIRK_32BIT_DMA_ADDR |
@@ -85,15 +77,28 @@ int s5p_sdhci_init(u32 regbase, int index, int bus_width)
 
        host->set_control_reg = &s5p_sdhci_set_control_reg;
        host->set_clock = set_mmc_clk;
-       host->index = index;
 
        host->host_caps = MMC_MODE_HC;
-       if (bus_width == 8)
+       if (host->bus_width == 8)
                host->host_caps |= MMC_MODE_8BIT;
 
        return add_sdhci(host, 52000000, 400000);
 }
 
+int s5p_sdhci_init(u32 regbase, int index, int bus_width)
+{
+       struct sdhci_host *host = malloc(sizeof(struct sdhci_host));
+       if (!host) {
+               printf("sdhci__host malloc fail!\n");
+               return 1;
+       }
+       host->ioaddr = (void *)regbase;
+       host->index = index;
+       host->bus_width = bus_width;
+
+       return s5p_sdhci_core_init(host);
+}
+
 #ifdef CONFIG_OF_CONTROL
 struct sdhci_host sdhci_host[SDHCI_MAX_HOSTS];
 
@@ -126,20 +131,7 @@ static int do_sdhci_init(struct sdhci_host *host)
                }
        }
 
-       host->name = S5P_NAME;
-
-       host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE |
-               SDHCI_QUIRK_BROKEN_R1B | SDHCI_QUIRK_32BIT_DMA_ADDR |
-               SDHCI_QUIRK_WAIT_SEND_CMD;
-       host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
-       host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
-
-       host->set_control_reg = &s5p_sdhci_set_control_reg;
-       host->set_clock = set_mmc_clk;
-
-       host->host_caps = MMC_MODE_HC;
-
-       return add_sdhci(host, 52000000, 400000);
+       return s5p_sdhci_core_init(host);
 }
 
 static int sdhci_get_config(const void *blob, int node, struct sdhci_host *host)