arm64: Disable TTBR1 maps in EL1

When running in EL1, AArch64 knows two page table maps. One with addresses
that start with all zeros (TTBR0) and one with addresses that start with all
ones (TTBR1).

In U-Boot we don't care about the high up maps, so just disable them to ensure
we don't walk an invalid page table by accident.

Reported-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>

diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index 9229532efacdb66cf0b189241cdc172103cae8b0..d92f2d1768f42b8145a8d22feb0e0b1bf8eee238 100644 (file)
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -71,7 +71,7 @@ static u64 get_tcr(int el, u64 *pips, u64 *pva_bits)
        }
 
        if (el == 1) {
-               tcr = TCR_EL1_RSVD | (ips << 32);
+               tcr = TCR_EL1_RSVD | (ips << 32) | TCR_EPD1_DISABLE;
        } else if (el == 2) {
                tcr = TCR_EL2_RSVD | (ips << 16);
        } else {

diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h
index 39ff74566e20869892bad6847d6129f19a2e3ecc..0080ae6ff5291853cf3984142e4d71e37a310828 100644 (file)
--- a/arch/arm/include/asm/armv8/mmu.h
+++ b/arch/arm/include/asm/armv8/mmu.h
@@ -154,6 +154,7 @@
 #define TCR_TG0_4K             (0 << 14)
 #define TCR_TG0_64K            (1 << 14)
 #define TCR_TG0_16K            (2 << 14)
+#define TCR_EPD1_DISABLE       (1 << 23)
 
 #ifndef CONFIG_SYS_FULL_VA
 #define TCR_EL1_IPS_BITS       (UL(3) << 32)   /* 42 bits physical address */