fsl_dma: Add bitfield definitions for common registers

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/drivers/dma/fsl_dma.c b/drivers/dma/fsl_dma.c
index a9989ee5cb74f036c4c5f65a9120ef6d496477c6..baf29420f0b6bc3c6212e445bac049b97d34f854 100644 (file)
--- a/drivers/dma/fsl_dma.c
+++ b/drivers/dma/fsl_dma.c
@@ -51,11 +51,11 @@ static uint dma_check(void) {
        volatile uint status = dma->sr;
 
        /* While the channel is busy, spin */
-       while (status & 4)
+       while (status & FSL_DMA_SR_CB)
                status = dma->sr;
 
        /* clear MR[CS] channel start bit */
-       dma->mr &= 1;
+       dma->mr &= FSL_DMA_MR_CS;
        dma_sync();
 
        if (status != 0)
@@ -67,8 +67,8 @@ static uint dma_check(void) {
 void dma_init(void) {
        volatile fsl_dma_t *dma = &dma_base->dma[0];
 
-       dma->satr = 0x00040000;
-       dma->datr = 0x00040000;
+       dma->satr = FSL_DMA_SATR_SREAD_NO_SNOOP;
+       dma->datr = FSL_DMA_DATR_DWRITE_NO_SNOOP;
        dma->sr = 0xffffffff; /* clear any errors */
        dma_sync();
 }
@@ -81,11 +81,11 @@ int dma_xfer(void *dest, uint count, void *src) {
        dma->bcr = count;
 
        /* Disable bandwidth control, use direct transfer mode */
-       dma->mr = 0xf000004;
+       dma->mr = FSL_DMA_MR_BWC_DIS | FSL_DMA_MR_CTM_DIRECT;
        dma_sync();
 
        /* Start the transfer */
-       dma->mr = 0xf000005;
+       dma->mr = FSL_DMA_MR_BWC_DIS | FSL_DMA_MR_CTM_DIRECT | FSL_DMA_MR_CS;
        dma_sync();
 
        return dma_check();

diff --git a/include/asm-ppc/fsl_dma.h b/include/asm-ppc/fsl_dma.h
index aab8720977e466976dab78f65ec20e1fd31cc149..c9ec6b59e699724ea636a238450ddbc03c2ab9d3 100644 (file)
--- a/include/asm-ppc/fsl_dma.h
+++ b/include/asm-ppc/fsl_dma.h
@@ -29,12 +29,58 @@
 
 typedef struct fsl_dma {
        uint    mr;             /* DMA mode register */
+#define FSL_DMA_MR_CS          0x00000001      /* Channel start */
+#define FSL_DMA_MR_CC          0x00000002      /* Channel continue */
+#define FSL_DMA_MR_CTM         0x00000004      /* Channel xfer mode */
+#define FSL_DMA_MR_CTM_DIRECT  0x00000004      /* Direct channel xfer mode */
+#define FSL_DMA_MR_CA          0x00000008      /* Channel abort */
+#define FSL_DMA_MR_CDSM                0x00000010
+#define FSL_DMA_MR_XFE         0x00000020      /* Extended features en */
+#define FSL_DMA_MR_EIE         0x00000040      /* Error interrupt en */
+#define FSL_DMA_MR_EOLSIE      0x00000080      /* End-of-lists interrupt en */
+#define FSL_DMA_MR_EOLNIE      0x00000100      /* End-of-links interrupt en */
+#define FSL_DMA_MR_EOSIE       0x00000200      /* End-of-seg interrupt en */
+#define FSL_DMA_MR_SRW         0x00000400      /* Single register write */
+#define FSL_DMA_MR_SAHE                0x00001000      /* Source addr hold enable */
+#define FSL_DMA_MR_DAHE                0x00002000      /* Dest addr hold enable */
+#define FSL_DMA_MR_SAHTS_MASK  0x0000c000      /* Source addr hold xfer size */
+#define FSL_DMA_MR_DAHTS_MASK  0x00030000      /* Dest addr hold xfer size */
+#define FSL_DMA_MR_EMS_EN      0x00040000      /* Ext master start en */
+#define FSL_DMA_MR_EMP_EN      0x00200000      /* Ext master pause en */
+#define FSL_DMA_MR_BWC_MASK    0x0f000000      /* Bandwidth/pause ctl */
+#define FSL_DMA_MR_BWC_DIS     0x0f000000      /* Bandwidth/pause ctl disable */
        uint    sr;             /* DMA status register */
+#define FSL_DMA_SR_EOLSI       0x00000001      /* End-of-list interrupt */
+#define FSL_DMA_SR_EOSI                0x00000002      /* End-of-segment interrupt */
+#define FSL_DMA_SR_CB          0x00000004      /* Channel busy */
+#define FSL_DMA_SR_EOLNI       0x00000008      /* End-of-links interrupt */
+#define FSL_DMA_SR_PE          0x00000010      /* Programming error */
+#define FSL_DMA_SR_CH          0x00000020      /* Channel halted */
+#define FSL_DMA_SR_TE          0x00000080      /* Transfer error */
        char    res0[4];
        uint    clndar;         /* DMA current link descriptor address register */
        uint    satr;           /* DMA source attributes register */
+#define FSL_DMA_SATR_ESAD_MASK         0x000001ff      /* Extended source addr */
+#define FSL_DMA_SATR_SREAD_NO_SNOOP    0x00040000      /* Read, don't snoop */
+#define FSL_DMA_SATR_SREAD_SNOOP       0x00050000      /* Read, snoop */
+#define FSL_DMA_SATR_SREAD_UNLOCK      0x00070000      /* Read, unlock l2 */
+#define FSL_DMA_SATR_STRAN_MASK                0x00f00000      /* Source interface  */
+#define FSL_DMA_SATR_SSME              0x01000000      /* Source stride en */
+#define FSL_DMA_SATR_SPCIORDER         0x02000000      /* PCI transaction order */
+#define FSL_DMA_SATR_STFLOWLVL_MASK    0x0c000000      /* RIO flow level */
+#define FSL_DMA_SATR_SBPATRMU          0x20000000      /* Bypass ATMU */
        uint    sar;            /* DMA source address register */
        uint    datr;           /* DMA destination attributes register */
+#define FSL_DMA_DATR_EDAD_MASK         0x000001ff      /* Extended dest addr */
+#define FSL_DMA_DATR_DWRITE_NO_SNOOP   0x00040000      /* Write, don't snoop */
+#define FSL_DMA_DATR_DWRITE_SNOOP      0x00050000      /* Write, snoop */
+#define FSL_DMA_DATR_DWRITE_ALLOC      0x00060000      /* Write, alloc l2 */
+#define FSL_DMA_DATR_DWRITE_LOCK       0x00070000      /* Write, lock l2 */
+#define FSL_DMA_DATR_DTRAN_MASK                0x00f00000      /* Dest interface  */
+#define FSL_DMA_DATR_DSME              0x01000000      /* Dest stride en */
+#define FSL_DMA_DATR_DPCIORDER         0x02000000      /* PCI transaction order */
+#define FSL_DMA_DATR_DTFLOWLVL_MASK    0x0c000000      /* RIO flow level */
+#define FSL_DMA_DATR_DBPATRMU          0x20000000      /* Bypass ATMU */
        uint    dar;            /* DMA destination address register */
        uint    bcr;            /* DMA byte count register */
        char    res1[4];