p1014rdb: set ddr bus width properly depending on SVR

Currently, for NAND boot for the P1010/4RDB we hard code the DDR
configuration. We can still dynamically set the DDR bus width in
the nand spl so the P1010/4RDB boards can boot from the same
u-boot image

Signed-off-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h
index 93639ba85164bd9d4646380ad29d9d4e9645f9c4..157ae246354a312f5c9e45a86645664216a16c2e 100644 (file)
--- a/arch/powerpc/include/asm/fsl_ddr_sdram.h
+++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h
@@ -88,6 +88,7 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
 #define SDRAM_CFG_SDRAM_TYPE_MASK      0x07000000
 #define SDRAM_CFG_SDRAM_TYPE_SHIFT     24
 #define SDRAM_CFG_DYN_PWR              0x00200000
+#define SDRAM_CFG_DBW_MASK             0x00180000
 #define SDRAM_CFG_32_BE                        0x00080000
 #define SDRAM_CFG_16_BE                        0x00100000
 #define SDRAM_CFG_8_BE                 0x00040000

diff --git a/nand_spl/board/freescale/p1010rdb/nand_boot.c b/nand_spl/board/freescale/p1010rdb/nand_boot.c
index 16eeb61d85b6b870c1ee2285d6c6101160fdb252..1f89ab5816f22da305c42fc0f8df6982208c6b31 100644 (file)
--- a/nand_spl/board/freescale/p1010rdb/nand_boot.c
+++ b/nand_spl/board/freescale/p1010rdb/nand_boot.c
@@ -35,6 +35,7 @@ unsigned long ddr_freq_mhz;
 void sdram_init(void)
 {
        ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
+       u32 svr = mfspr(SPRN_SVR);
 
        out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | SDRAM_CFG_32_BE);
        out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
@@ -70,6 +71,16 @@ void sdram_init(void)
        out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5);
        out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CONTROL);
 
+       /* P1014 and it's derivatives support max 16bit DDR width */
+       if (svr == SVR_P1014) {
+               __raw_writel(ddr->sdram_cfg & ~SDRAM_CFG_DBW_MASK, &ddr->sdram_cfg);
+               __raw_writel(ddr->sdram_cfg | SDRAM_CFG_16_BE, &ddr->sdram_cfg);
+               /* For CS0_BNDS we divide the start and end address by 2, so we can just
+                * shift the entire register to achieve the desired result and the mask
+                * the value so we don't write reserved fields */
+               __raw_writel((CONFIG_SYS_DDR_CS0_BNDS >> 1) & 0x0fff0fff, &ddr->cs0_bnds);
+       }
+
        /* mimic 500us delay, with busy isync() loop */
        udelay(100);