]> git.sur5r.net Git - u-boot/commitdiff
driver/ldpaa: Add support of WRIOP static data structure
authorPrabhakar Kushwaha <prabhakar@freescale.com>
Sat, 21 Mar 2015 02:28:22 +0000 (19:28 -0700)
committerYork Sun <yorksun@freescale.com>
Thu, 23 Apr 2015 15:55:58 +0000 (08:55 -0700)
Wire rate IO Processor (WRIOP) provide support of receive and transmit
ethernet frames from the ethernet MAC.  Here Each WRIOP block supports
upto 64 DPMACs.

Create a house keeping data structure to support upto 16 DPMACs and
store external phy related information.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c
arch/arm/include/asm/arch-fsl-lsch3/config.h
arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h
drivers/net/ldpaa_eth/Makefile
drivers/net/ldpaa_eth/ldpaa_eth.h
drivers/net/ldpaa_eth/ldpaa_wriop.c [new file with mode: 0644]
include/fsl-mc/ldpaa_wriop.h [new file with mode: 0644]

index 78b92102c92d39f3d3994802b2fc3c8ca26a5c64..02ca126ab80b85c90e7175f31f8d52ef8de0a032 100644 (file)
@@ -9,6 +9,7 @@
 #include <asm/errno.h>
 #include <asm/arch/fsl_serdes.h>
 #include <asm/arch-fsl-lsch3/immap_lsch3.h>
+#include <fsl-mc/ldpaa_wriop.h>
 
 #ifdef CONFIG_SYS_FSL_SRDS_1
 static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
@@ -86,8 +87,12 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
                enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
                if (unlikely(lane_prtcl >= SERDES_PRCTL_COUNT))
                        debug("Unknown SerDes lane protocol %d\n", lane_prtcl);
-               else
+               else {
                        serdes_prtcl_map[lane_prtcl] = 1;
+#ifdef CONFIG_FSL_MC_ENET
+                       wriop_init_dpmac(sd, lane + 1, (int)lane_prtcl);
+#endif
+               }
        }
 }
 
index 684c70f20ee5d3d96bd3188512cba1138d277f35..403b2ef0f8c45ce146b5e03eb260e5569e826fc4 100644 (file)
@@ -38,6 +38,9 @@
 #define CONFIG_SYS_FSL_PMU_CLTBENR             (CONFIG_SYS_FSL_PMU_ADDR + \
                                                 0x18A0)
 
+#define CONFIG_SYS_FSL_WRIOP1_ADDR             (CONFIG_SYS_IMMR + 0x7B80000)
+#define CONFIG_SYS_FSL_WRIOP1_MDIO1    (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000)
+#define CONFIG_SYS_FSL_WRIOP1_MDIO2    (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000)
 #define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR       (CONFIG_SYS_IMMR + 0xEA0000)
 
 /* SP (Cortex-A5) related */
index 91cf68b6892e58f485f2696a5e1697d558dd3607..d6bee60385f04d8dee260dbb7a699a6ec38ffb8b 100644 (file)
@@ -47,6 +47,30 @@ struct ccsr_gur {
        u32     devdisr5;       /* Device disable control 5 */
        u32     devdisr6;       /* Device disable control 6 */
        u32     devdisr7;       /* Device disable control 7 */
+#define FSL_CHASSIS3_DEVDISR2_DPMAC1   0x00000001
+#define FSL_CHASSIS3_DEVDISR2_DPMAC2   0x00000002
+#define FSL_CHASSIS3_DEVDISR2_DPMAC3   0x00000004
+#define FSL_CHASSIS3_DEVDISR2_DPMAC4   0x00000008
+#define FSL_CHASSIS3_DEVDISR2_DPMAC5   0x00000010
+#define FSL_CHASSIS3_DEVDISR2_DPMAC6   0x00000020
+#define FSL_CHASSIS3_DEVDISR2_DPMAC7   0x00000040
+#define FSL_CHASSIS3_DEVDISR2_DPMAC8   0x00000080
+#define FSL_CHASSIS3_DEVDISR2_DPMAC9   0x00000100
+#define FSL_CHASSIS3_DEVDISR2_DPMAC10  0x00000200
+#define FSL_CHASSIS3_DEVDISR2_DPMAC11  0x00000400
+#define FSL_CHASSIS3_DEVDISR2_DPMAC12  0x00000800
+#define FSL_CHASSIS3_DEVDISR2_DPMAC13  0x00001000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC14  0x00002000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC15  0x00004000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC16  0x00008000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC17  0x00010000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC18  0x00020000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC19  0x00040000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC20  0x00080000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC21  0x00100000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC22  0x00200000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC23  0x00400000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC24  0x00800000
        u8      res_08c[0x90-0x8c];
        u32     coredisru;      /* uppper portion for support of 64 cores */
        u32     coredisrl;      /* lower portion for support of 64 cores */
index 3b1a60bbcad762cbfe85b859182f0e4a08e99442..d32d67ee611f70d2a6ffcf7216abc3b0cdbf0c05 100644 (file)
@@ -4,5 +4,5 @@
 # SPDX-License-Identifier:     GPL-2.0+
 #
 
-# Layerscape LDPAA driver
+obj-y += ldpaa_wriop.o
 obj-y += ldpaa_eth.o
index c7760ef69ff3f951b0c8d76d1fc6d2c095ff644e..3107ab6cff930ec0f667c5cd5b5d1e358b8c24be 100644 (file)
@@ -132,11 +132,7 @@ struct ldpaa_eth_priv {
        uint16_t tx_flow_id;
 
        enum ldpaa_eth_type type;       /* 1G or 10G ethernet */
-       phy_interface_t enet_if;
-       struct mii_dev *bus;
        struct phy_device *phydev;
-       int phyaddr;
-
 };
 
 extern struct fsl_mc_io *dflt_mc_io;
diff --git a/drivers/net/ldpaa_eth/ldpaa_wriop.c b/drivers/net/ldpaa_eth/ldpaa_wriop.c
new file mode 100644 (file)
index 0000000..926057a
--- /dev/null
@@ -0,0 +1,146 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/types.h>
+#include <malloc.h>
+#include <net.h>
+#include <linux/compat.h>
+#include <asm/arch/fsl_serdes.h>
+#include <fsl-mc/ldpaa_wriop.h>
+
+struct wriop_dpmac_info dpmac_info[NUM_WRIOP_PORTS];
+
+__weak phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtc)
+{
+       return PHY_INTERFACE_MODE_NONE;
+}
+
+void wriop_init_dpmac(int sd, int dpmac_id, int lane_prtcl)
+{
+       phy_interface_t enet_if;
+       int index = dpmac_id + sd * 8;
+
+       dpmac_info[index].enabled = 0;
+       dpmac_info[index].id = 0;
+       dpmac_info[index].enet_if = PHY_INTERFACE_MODE_NONE;
+
+       enet_if = wriop_dpmac_enet_if(index, lane_prtcl);
+       if (enet_if != PHY_INTERFACE_MODE_NONE) {
+               dpmac_info[index].enabled = 1;
+               dpmac_info[index].id = index;
+               dpmac_info[index].enet_if = enet_if;
+       }
+}
+
+/*TODO what it do */
+static int wriop_dpmac_to_index(int dpmac_id)
+{
+       int i;
+
+       for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
+               if (dpmac_info[i].id == dpmac_id)
+                       return i;
+       }
+
+       return -1;
+}
+
+void wriop_disable_dpmac(int dpmac_id)
+{
+       int i = wriop_dpmac_to_index(dpmac_id);
+
+       if (i == -1)
+               return;
+
+       dpmac_info[i].enabled = 0;
+       wriop_dpmac_disable(dpmac_id);
+}
+
+void wriop_enable_dpmac(int dpmac_id)
+{
+       int i = wriop_dpmac_to_index(dpmac_id);
+
+       if (i == -1)
+               return;
+
+       dpmac_info[i].enabled = 1;
+       wriop_dpmac_enable(dpmac_id);
+}
+
+void wriop_set_mdio(int dpmac_id, struct mii_dev *bus)
+{
+       int i = wriop_dpmac_to_index(dpmac_id);
+
+       if (i == -1)
+               return;
+
+       dpmac_info[i].bus = bus;
+}
+
+struct mii_dev *wriop_get_mdio(int dpmac_id)
+{
+       int i = wriop_dpmac_to_index(dpmac_id);
+
+       if (i == -1)
+               return NULL;
+
+       return dpmac_info[i].bus;
+}
+
+void wriop_set_phy_address(int dpmac_id, int address)
+{
+       int i = wriop_dpmac_to_index(dpmac_id);
+
+       if (i == -1)
+               return;
+
+       dpmac_info[i].phy_addr = address;
+}
+
+int wriop_get_phy_address(int dpmac_id)
+{
+       int i = wriop_dpmac_to_index(dpmac_id);
+
+       if (i == -1)
+               return -1;
+
+       return dpmac_info[i].phy_addr;
+}
+
+void wriop_set_phy_dev(int dpmac_id, struct phy_device *phydev)
+{
+       int i = wriop_dpmac_to_index(dpmac_id);
+
+       if (i == -1)
+               return;
+
+       dpmac_info[i].phydev = phydev;
+}
+
+struct phy_device *wriop_get_phy_dev(int dpmac_id)
+{
+       int i = wriop_dpmac_to_index(dpmac_id);
+
+       if (i == -1)
+               return NULL;
+
+       return dpmac_info[i].phydev;
+}
+
+phy_interface_t wriop_get_enet_if(int dpmac_id)
+{
+       int i = wriop_dpmac_to_index(dpmac_id);
+
+       if (i == -1)
+               return PHY_INTERFACE_MODE_NONE;
+
+       if (dpmac_info[i].enabled)
+               return dpmac_info[i].enet_if;
+
+       return PHY_INTERFACE_MODE_NONE;
+}
diff --git a/include/fsl-mc/ldpaa_wriop.h b/include/fsl-mc/ldpaa_wriop.h
new file mode 100644 (file)
index 0000000..ca8e440
--- /dev/null
@@ -0,0 +1,70 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __LDPAA_WRIOP_H
+#define __LDPAA_WRIOP_H
+
+ #include <phy.h>
+
+enum wriop_port {
+       WRIOP1_DPMAC1 = 1,
+       WRIOP1_DPMAC2,
+       WRIOP1_DPMAC3,
+       WRIOP1_DPMAC4,
+       WRIOP1_DPMAC5,
+       WRIOP1_DPMAC6,
+       WRIOP1_DPMAC7,
+       WRIOP1_DPMAC8,
+       WRIOP1_DPMAC9,
+       WRIOP1_DPMAC10,
+       WRIOP1_DPMAC11,
+       WRIOP1_DPMAC12,
+       WRIOP1_DPMAC13,
+       WRIOP1_DPMAC14,
+       WRIOP1_DPMAC15,
+       WRIOP1_DPMAC16,
+       WRIOP1_DPMAC17,
+       WRIOP1_DPMAC18,
+       WRIOP1_DPMAC19,
+       WRIOP1_DPMAC20,
+       WRIOP1_DPMAC21,
+       WRIOP1_DPMAC22,
+       WRIOP1_DPMAC23,
+       WRIOP1_DPMAC24,
+       NUM_WRIOP_PORTS,
+};
+
+struct wriop_dpmac_info {
+       u8 enabled;
+       u8 id;
+       u8 phy_addr;
+       u8 board_mux;
+       void *phy_regs;
+       phy_interface_t enet_if;
+       struct phy_device *phydev;
+       struct mii_dev *bus;
+};
+
+extern struct wriop_dpmac_info dpmac_info[NUM_WRIOP_PORTS];
+
+#define DEFAULT_WRIOP_MDIO1_NAME "FSL_MDIO0"
+#define DEFAULT_WRIOP_MDIO2_NAME "FSL_MDIO1"
+
+void wriop_init_dpmac(int, int, int);
+void wriop_disable_dpmac(int);
+void wriop_enable_dpmac(int);
+void wriop_set_mdio(int, struct mii_dev *);
+struct mii_dev *wriop_get_mdio(int);
+void wriop_set_phy_address(int, int);
+int wriop_get_phy_address(int);
+void wriop_set_phy_dev(int, struct phy_device *);
+struct phy_device *wriop_get_phy_dev(int);
+phy_interface_t wriop_get_enet_if(int);
+
+void wriop_dpmac_disable(int);
+void wriop_dpmac_enable(int);
+phy_interface_t wriop_dpmac_enet_if(int, int);
+#endif /* __LDPAA_WRIOP_H */