gd->mem_clk = 0;
i = in32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET +
CG_PWRUP_STATUS);
- i = (i >> 20) & 0x07; /* value of SW4[4:7] */
+ i = (i >> 20) & 0x07; /* Get GD PLL multiplier */
switch (i) {
case 0: /* external clock */
printf ("Using external clock\n");
__asm__ __volatile__ ("sync");
- /* Base addresses for Cs0, CS1, CS2, CS3 */
+ /* Base addresses for CS0, CS1, CS2, CS3 */
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_ADDR,
0x00000000);
CPU_750CX, CPU_750FX, CPU_750GX,
CPU_7400,
CPU_7410,
- CPU_7448,
- CPU_7450, CPU_7455, CPU_7457,
CPU_7447A, CPU_7448,
+ CPU_7450, CPU_7455, CPU_7457,
CPU_UNKNOWN} cpu_t;
extern cpu_t get_cpu_type(void);
* on our cache or tlb entries.
*/
+DECLARE_GLOBAL_DATA_PTR;
+
struct exception_table_entry
{
unsigned long insn, fixup;
const struct exception_table_entry *last,
unsigned long value)
{
- DECLARE_GLOBAL_DATA_PTR;
-
while (first <= last) {
const struct exception_table_entry *mid;
long diff;
mid = (last - first) / 2 + first;
- if (mid > CFG_MONITOR_BASE){
+ if (mid > CFG_MONITOR_BASE) {
/* exception occurs in FLASH, before u-boot relocation.
- * No relocation offset is needed.
+ * No relocation offset is needed.
*/
diff = mid->insn - value;
if (diff == 0)
return mid->fixup;
} else {
- /* exception occurs in RAM, after u-boot relocation.
+ /* exception occurs in RAM, after u-boot relocation.
* A relocation offset should be added.
*/
diff = (mid->insn + gd->reloc_off) - value;