return addr & PCI_BASE_ADDRESS_MEM_MASK;
}
+void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr)
+{
+ int bar;
+
+ bar = PCI_BASE_ADDRESS_0 + barnum * 4;
+ dm_pci_write_config32(dev, bar, addr);
+}
+
static int _dm_pci_bus_to_phys(struct udevice *ctlr,
pci_addr_t bus_addr, unsigned long flags,
unsigned long skip_mask, phys_addr_t *pa)
/**
* pci_write_bar32() - Write the address of a BAR including control bits
*
- * This writes a raw address (with control bits) to a bar
+ * This writes a raw address (with control bits) to a bar. This can be used
+ * with devices which require hard-coded addresses, not part of the normal
+ * PCI enumeration process.
*
* @hose: PCI hose to use
* @dev: PCI device to update
* @addr: BAR address with control bits
*/
void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum,
- u32 addr_and_ctrl);
+ u32 addr);
/**
* pci_read_bar32() - read the address of a bar
int pci_get_regions(struct udevice *dev, struct pci_region **iop,
struct pci_region **memp, struct pci_region **prefp);
+/**
+ * dm_pci_write_bar32() - Write the address of a BAR
+ *
+ * This writes a raw address to a bar
+ *
+ * @dev: PCI device to update
+ * @barnum: BAR number (0-5)
+ * @addr: BAR address
+ */
+void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr);
+
/**
* dm_pci_read_bar32() - read a base address register from a device
*