ARM: MX51: PLL errata workaround

This is a port of the official PLL errata workaround from Freescale to
mainline u-boot.
The PLL's in the i.MX51 processor can go out of lock due to a metastable
condition in an analog flip-flop when used at high frequencies.
This workaround implements an undocumented feature in the PLL (dither
mode), which causes the effect of this failure to be much lower (in terms
of frequency deviation), avoiding system failure, or at least decreasing
the likelihood of system failure.

Signed-off-by: David Jander <david@protonic.nl>

diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
index 94de9f1d614458a2175c05a4ccb9a2a0e5d53b6b..6c66b42619901417b099c6052ec05e9f7a09e3b3 100644 (file)
--- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
@@ -121,6 +121,35 @@
        beq 1b
 .endm
 
+.macro setup_pll_errata pll, freq
+       ldr r2, =\pll
+       mov r1, #0x0
+       str r1, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */
+       ldr r1, =0x00001236
+       str r1, [r2, #PLL_DP_CTL]    /* Restart PLL with PLM=1 */
+1:     ldr r1, [r2, #PLL_DP_CTL]    /* Wait for lock */
+       ands r1, r1, #0x1
+       beq 1b
+
+       ldr r5, \freq
+       str r5, [r2, #PLL_DP_MFN]    /* Modify MFN value */
+       str r5, [r2, #PLL_DP_HFS_MFN]
+
+       mov r1, #0x1
+       str r1, [r2, #PLL_DP_CONFIG] /* Reload MFN value */
+
+2:     ldr r1, [r2, #PLL_DP_CONFIG]
+       tst r1, #1
+       bne 2b
+
+       ldr r1, =100                 /* Wait at least 4 us */
+3:     subs r1, r1, #1
+       bge 3b
+
+       mov r1, #0x2
+       str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
+.endm
+
 .macro init_clock
        ldr r0, =CCM_BASE_ADDR
 
@@ -157,7 +186,12 @@
        mov r1, #0x4
        str r1, [r0, #CLKCTL_CCSR]
 
+#if defined(CONFIG_MX51_PLL_ERRATA)
+       setup_pll PLL1_BASE_ADDR, 864
+       setup_pll_errata PLL1_BASE_ADDR, W_DP_MFN_800_DIT
+#else
        setup_pll PLL1_BASE_ADDR, 800
+#endif
 
 #if defined(CONFIG_MX51)
        setup_pll PLL3_BASE_ADDR, 665
@@ -287,6 +321,10 @@ lowlevel_init:
        mov pc,lr
 
 /* Board level setting value */
+W_DP_OP_864:              .word DP_OP_864
+W_DP_MFD_864:             .word DP_MFD_864
+W_DP_MFN_864:             .word DP_MFN_864
+W_DP_MFN_800_DIT:         .word DP_MFN_800_DIT
 W_DP_OP_800:              .word DP_OP_800
 W_DP_MFD_800:             .word DP_MFD_800
 W_DP_MFN_800:             .word DP_MFN_800

diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h
index e83ca29006dd6477185a88d01a5dc01a497aa502..fb2c66fa0edfdf32e88cd6e0497297bcbe8aac87 100644 (file)
--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
@@ -235,6 +235,11 @@
 
 /* Assuming 24MHz input clock with doubler ON */
 /*                            MFI         PDF */
+#define DP_OP_864      ((8 << 4) + ((1 - 1)  << 0))
+#define DP_MFD_864     (180 - 1) /* PL Dither mode */
+#define DP_MFN_864     180
+#define DP_MFN_800_DIT 60 /* PL Dither mode */
+
 #define DP_OP_850      ((8 << 4) + ((1 - 1)  << 0))
 #define DP_MFD_850     (48 - 1)
 #define DP_MFN_850     41

diff --git a/doc/README.imx5 b/doc/README.imx5
new file mode 100644 (file)
index 0000000..f7eab7d
--- /dev/null
+++ b/doc/README.imx5
@@ -0,0 +1,17 @@
+U-Boot for Freescale i.MX5x
+
+This file contains information for the port of U-Boot to the Freescale
+i.MX5x SoCs.
+
+1. CONFIGURATION OPTIONS/SETTINGS
+---------------------------------
+
+1.1 CONFIG_MX51_PLL_ERRATA: Workaround for i.MX51 PLL errata.
+    This option should be enabled by all boards using the i.MX51 silicon
+    version up until (including) 3.0 running at 800MHz.
+    The PLL's in the i.MX51 processor can go out of lock due to a metastable
+    condition in an analog flip-flop when used at high frequencies.
+    This workaround implements an undocumented feature in the PLL (dither
+    mode), which causes the effect of this failure to be much lower (in terms
+    of frequency deviation), avoiding system failure, or at least decreasing
+    the likelihood of system failure.