pxa: fix memory coherency problem after relocation

On the xscale, the icache must be invalidated and the write buffers drained
after writing code over the data bus, even if the caches are disabled.  Tested
on the pxa270.

Signed-off-by: Mike Dunn <mikedunn@newsguy.com>

diff --git a/arch/arm/lib/relocate.S b/arch/arm/lib/relocate.S
index 949b9e8025b994cb8e6a9d85e63a920387e11ba7..cd2bab6cde7fb4e9c19cedc611122b91267d2aab 100644 (file)
--- a/arch/arm/lib/relocate.S
+++ b/arch/arm/lib/relocate.S
@@ -70,6 +70,15 @@ fixnext:
 
 relocate_done:
 
+#ifdef __XSCALE__
+       /*
+        * On xscale, icache must be invalidated and write buffers drained,
+        * even with cache disabled - 4.2.7 of xscale core developer's manual
+        */
+       mcr     p15, 0, r0, c7, c7, 0   /* invalidate icache */
+       mcr     p15, 0, r0, c7, c10, 4  /* drain write buffer */
+#endif
+
        /* ARMv4- don't know bx lr but the assembler fails to see that */
 
 #ifdef __ARM_ARCH_4__