arm: mvebu: db-88f6820: Add SPL support with DDR init code

This patch adds SPL support for the Marvell DB-88F6820-GP board.
With this change, the bin_hdr from the original Marvell U-boot
is not needed any more on this board. The sources from bin_hdr
(SERDES/PHY and DDR setup) are now integrated in mainline
U-Boot. And this patch enables them for this board.

Signed-off-by: Stefan Roese <sr@denx.de>

diff --git a/board/Marvell/db-88f6820-gp/README b/board/Marvell/db-88f6820-gp/README
new file mode 100644 (file)
index 0000000..9bea5b3
--- /dev/null
+++ b/board/Marvell/db-88f6820-gp/README
@@ -0,0 +1,18 @@
+Update from original Marvell U-Boot to mainline U-Boot:
+-------------------------------------------------------
+
+The resulting image including the SPL binary with the
+full DDR setup is "u-boot-spl.kwb".
+
+To update the SPI NOR flash, please use the following
+command:
+
+=> sf probe;tftpboot 2000000 db-88f6820-gp/u-boot-spl.kwb;\
+sf update 2000000 0 60000
+
+Note that the original Marvell U-Boot seems to have
+problems with the "sf update" command. This does not
+work reliable. So here this command should be used:
+
+=> sf probe;tftpboot 2000000 db-88f6820-gp/u-boot-spl.kwb;\
+sf erase 0 60000;sf write 2000000 0 60000

diff --git a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c
index 51ac495a4482f775c78e15aa591357b8bad35814..e661fa129671d3ef1cdd9d4dd65abfb604d3f566 100644 (file)
--- a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c
+++ b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c
@@ -11,6 +11,8 @@
 #include <asm/arch/cpu.h>
 #include <asm/arch/soc.h>
 
+#include "../drivers/ddr/marvell/a38x/ddr3_a38x_topology.h"
+
 DECLARE_GLOBAL_DATA_PTR;
 
 #define BIT(nr)                                (1UL << (nr))
@@ -54,6 +56,35 @@ static struct marvell_io_exp io_exp[] = {
        { 0x21, 3, 0xC0 }  /* Output Data, register#1 */
 };
 
+/*
+ * Define the DDR layout / topology here in the board file. This will
+ * be used by the DDR3 init code in the SPL U-Boot version to configure
+ * the DDR3 controller.
+ */
+static struct hws_topology_map board_topology_map = {
+       0x1, /* active interfaces */
+       /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
+       { { { {0x1, 0, 0, 0},
+             {0x1, 0, 0, 0},
+             {0x1, 0, 0, 0},
+             {0x1, 0, 0, 0},
+             {0x1, 0, 0, 0} },
+           SPEED_BIN_DDR_1866L,        /* speed_bin */
+           BUS_WIDTH_8,                /* memory_width */
+           MEM_4G,                     /* mem_size */
+           DDR_FREQ_800,               /* frequency */
+           0, 0,                       /* cas_l cas_wl */
+           HWS_TEMP_LOW} },            /* temperature */
+       5,                              /* Num Of Bus Per Interface*/
+       BUS_MASK_32BIT                  /* Busses mask */
+};
+
+struct hws_topology_map *ddr3_get_topology_map(void)
+{
+       /* Return the board topology as defined in the board code */
+       return &board_topology_map;
+}
+
 int board_early_init_f(void)
 {
        /* Configure MPP */

diff --git a/board/Marvell/db-88f6820-gp/kwbimage.cfg b/board/Marvell/db-88f6820-gp/kwbimage.cfg
index e81245420fae2e1b341d0ca36a814be14df6a8f2..cc057925566c584d66b0dc73207f5a62523ad2f6 100644 (file)
--- a/board/Marvell/db-88f6820-gp/kwbimage.cfg
+++ b/board/Marvell/db-88f6820-gp/kwbimage.cfg
@@ -9,4 +9,4 @@ VERSION         1
 BOOT_FROM      spi
 
 # Binary Header (bin_hdr) with DDR3 training code
-BINARY board/Marvell/db-88f6820-gp/binary.0 0000005b 00000068
+BINARY spl/u-boot-spl.bin 0000005b 00000068

diff --git a/configs/db-88f6820-gp_defconfig b/configs/db-88f6820-gp_defconfig
index 569ddfdda08a8582d0b9a22ee5cebf53b3f4535c..0ff67062a6b81d00575c4dd5d53b9cacf43350d9 100644 (file)
--- a/configs/db-88f6820-gp_defconfig
+++ b/configs/db-88f6820-gp_defconfig
@@ -1,3 +1,4 @@
+CONFIG_SPL=y
 CONFIG_ARM=y
 CONFIG_TARGET_DB_88F6820_GP=y
 # CONFIG_CMD_IMLS is not set

diff --git a/include/configs/db-88f6820-gp.h b/include/configs/db-88f6820-gp.h
index a429107a9af5ef5d632d3341c43e7ea46547393f..73b323605e3f40c6ce7b2e1f0ccca167ae8bccbc 100644 (file)
--- a/include/configs/db-88f6820-gp.h
+++ b/include/configs/db-88f6820-gp.h
@@ -11,6 +11,7 @@
  * High Level Configuration Options (easy to change)
  */
 #define CONFIG_ARMADA_XP               /* SOC Family Name */
+#define CONFIG_ARMADA_38X
 #define CONFIG_DB_88F6820_GP           /* Board target name for DDR training */
 
 #define CONFIG_SYS_L2_PL310
@@ -108,6 +109,40 @@
        "fdt_high=0x10000000\0"         \
        "initrd_high=0x10000000\0"
 
+/* SPL */
+/* Defines for SPL */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_SIZE                        (140 << 10)
+#define CONFIG_SPL_TEXT_BASE           0x40000030
+#define CONFIG_SPL_MAX_SIZE            (CONFIG_SPL_SIZE - 0x0030)
+
+#define CONFIG_SPL_BSS_START_ADDR      (0x40000000 + CONFIG_SPL_SIZE)
+#define CONFIG_SPL_BSS_MAX_SIZE                (16 << 10)
+
+#define CONFIG_SYS_SPL_MALLOC_START    (CONFIG_SPL_BSS_START_ADDR + \
+                                        CONFIG_SPL_BSS_MAX_SIZE)
+#define CONFIG_SYS_SPL_MALLOC_SIZE     (16 << 10)
+
+#define CONFIG_SPL_STACK               (0x40000000 + ((192 - 16) << 10))
+#define CONFIG_SPL_BOOTROM_SAVE                (CONFIG_SPL_STACK + 4)
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+
+/* SPL related SPI defines */
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_BUS             0
+#define CONFIG_SPL_SPI_CS              0
+#define CONFIG_SYS_SPI_U_BOOT_OFFS     0x20000
+
+/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
+#define CONFIG_SYS_MVEBU_DDR_A38X
+#define CONFIG_DDR3
+
 /*
  * mv-common.h should be defined after CMD configs since it used them
  * to enable certain macros