x86: ivybridge: Move northbridge and PCH init into drivers

Instead of calling the northbridge and PCH init from bd82x6x_init_extra()
when the PCI bus is probed, call it from the respective drivers. Also drop
the Northbridge init as it has no effect. The registers it touches appear to
be read-only.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c
index 149c1d23f12c5f5e54ef37438e63b1625f173454..c5a5d4d9c28be0e2402ecf0318d44e3ba32ee3a9 100644 (file)
--- a/arch/x86/cpu/ivybridge/bd82x6x.c
+++ b/arch/x86/cpu/ivybridge/bd82x6x.c
@@ -18,45 +18,6 @@
 
 #define BIOS_CTRL      0xdc
 
-void bd82x6x_pci_init(pci_dev_t dev)
-{
-       u16 reg16;
-       u8 reg8;
-
-       debug("bd82x6x PCI init.\n");
-       /* Enable Bus Master */
-       reg16 = x86_pci_read_config16(dev, PCI_COMMAND);
-       reg16 |= PCI_COMMAND_MASTER;
-       x86_pci_write_config16(dev, PCI_COMMAND, reg16);
-
-       /* This device has no interrupt */
-       x86_pci_write_config8(dev, INTR, 0xff);
-
-       /* disable parity error response and SERR */
-       reg16 = x86_pci_read_config16(dev, BCTRL);
-       reg16 &= ~(1 << 0);
-       reg16 &= ~(1 << 1);
-       x86_pci_write_config16(dev, BCTRL, reg16);
-
-       /* Master Latency Count must be set to 0x04! */
-       reg8 = x86_pci_read_config8(dev, SMLT);
-       reg8 &= 0x07;
-       reg8 |= (0x04 << 3);
-       x86_pci_write_config8(dev, SMLT, reg8);
-
-       /* Will this improve throughput of bus masters? */
-       x86_pci_write_config8(dev, PCI_MIN_GNT, 0x06);
-
-       /* Clear errors in status registers */
-       reg16 = x86_pci_read_config16(dev, PSTS);
-       /* reg16 |= 0xf900; */
-       x86_pci_write_config16(dev, PSTS, reg16);
-
-       reg16 = x86_pci_read_config16(dev, SECSTS);
-       /* reg16 |= 0xf900; */
-       x86_pci_write_config16(dev, SECSTS, reg16);
-}
-
 static int bd82x6x_probe(struct udevice *dev)
 {
        const void *blob = gd->fdt_blob;
@@ -108,10 +69,7 @@ int bd82x6x_init_extra(void)
                return -EINVAL;
        }
 
-       bd82x6x_pci_init(PCH_DEV);
        bd82x6x_sata_enable(PCH_SATA_DEV, blob, sata_node);
-       northbridge_enable(PCH_DEV);
-       northbridge_init(PCH_DEV);
 
        return 0;
 }

diff --git a/arch/x86/cpu/ivybridge/northbridge.c b/arch/x86/cpu/ivybridge/northbridge.c
index 6b00d31dd431bc0a8ecd93bcddfc875972b88809..2eed0afe18f936dcb695191483cc42c8bd77d249 100644 (file)
--- a/arch/x86/cpu/ivybridge/northbridge.c
+++ b/arch/x86/cpu/ivybridge/northbridge.c
@@ -197,15 +197,12 @@ static void sandybridge_setup_northbridge_bars(struct udevice *dev)
        dm_pci_write_config8(dev, PAM6, 0x33);
 }
 
-static int bd82x6x_northbridge_probe(struct udevice *dev)
+static int bd82x6x_northbridge_early_init(struct udevice *dev)
 {
        const int chipset_type = SANDYBRIDGE_MOBILE;
        u32 capid0_a;
        u8 reg8;
 
-       if (gd->flags & GD_FLG_RELOC)
-               return 0;
-
        /* Device ID Override Enable should be done very early */
        dm_pci_read_config32(dev, 0xe4, &capid0_a);
        if (capid0_a & (1 << 10)) {
@@ -226,6 +223,17 @@ static int bd82x6x_northbridge_probe(struct udevice *dev)
        return 0;
 }
 
+static int bd82x6x_northbridge_probe(struct udevice *dev)
+{
+       if (!(gd->flags & GD_FLG_RELOC))
+               return bd82x6x_northbridge_early_init(dev);
+
+       northbridge_enable(PCH_DEV);
+       northbridge_init(PCH_DEV);
+
+       return 0;
+}
+
 static const struct udevice_id bd82x6x_northbridge_ids[] = {
        { .compatible = "intel,bd82x6x-northbridge" },
        { }

diff --git a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
index fc7fc6d14bb04df1d86ee583b94472eff05c7f16..0f4fe473394513155e17ee31c036d0f1d0186a3f 100644 (file)
--- a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
+++ b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
@@ -9,7 +9,6 @@
 
 void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node);
 void bd82x6x_sata_enable(pci_dev_t dev, const void *blob, int node);
-void bd82x6x_pci_init(pci_dev_t dev);
 void bd82x6x_usb_ehci_init(pci_dev_t dev);
 void bd82x6x_usb_xhci_init(pci_dev_t dev);
 int gma_func0_init(struct udevice *dev, const void *blob, int node);

diff --git a/board/google/chromebook_link/link.c b/board/google/chromebook_link/link.c
index 1b97a8fea85537307764cbb6731f9d4afffb966d..d12d74202c51a6ed1f6dc2d0eade9be6e4c865b7 100644 (file)
--- a/board/google/chromebook_link/link.c
+++ b/board/google/chromebook_link/link.c
@@ -14,14 +14,6 @@
 
 int arch_early_init_r(void)
 {
-       struct udevice *dev;
-       int ret;
-
-       /* Make sure the platform controller hub is up and running */
-       ret = uclass_get_device(UCLASS_PCH, 0, &dev);
-       if (ret)
-               return ret;
-
        return 0;
 }