ppc/85xx: Split out cpu_init_early into its own file for NAND_SPL

By pulling out cpu_init_early we can build just it and not all of
cpu_init for NAND_SPL.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile
index a177f427efec3666b06766daec01493f75d5c09a..3ef00e850696fac4a3d7107daed7a6d25fb5c303 100644 (file)
--- a/cpu/mpc85xx/Makefile
+++ b/cpu/mpc85xx/Makefile
@@ -65,6 +65,7 @@ COBJS-$(CONFIG_CPM2)  += serial_scc.o
 COBJS  = $(COBJS-y)
 COBJS  += cpu.o
 COBJS  += cpu_init.o
+COBJS  += cpu_init_early.o
 COBJS  += interrupts.o
 COBJS  += speed.o
 COBJS  += tlb.o

diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c
index 07856c2a24cee575d162ee3ff6bc86ec6ac29cbb..48a82eda6d8006432db98527b47c05058f8e1795 100644 (file)
--- a/cpu/mpc85xx/cpu_init.c
+++ b/cpu/mpc85xx/cpu_init.c
@@ -129,57 +129,6 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm)
 }
 #endif
 
-/* We run cpu_init_early_f in AS = 1 */
-void cpu_init_early_f(void)
-{
-       u32 mas0, mas1, mas2, mas3, mas7;
-       int i;
-
-       /* Pointer is writable since we allocated a register for it */
-       gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
-
-       /*
-        * Clear initial global data
-        *   we don't use memset so we can share this code with NAND_SPL
-        */
-       for (i = 0; i < sizeof(gd_t); i++)
-               ((char *)gd)[i] = 0;
-
-       mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(0);
-       mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_4K);
-       mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G);
-       mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR);
-       mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_PHYS);
-
-       write_tlb(mas0, mas1, mas2, mas3, mas7);
-
-       /* set up CCSR if we want it moved */
-#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS)
-       {
-               u32 temp;
-               volatile u32 *ccsr_virt =
-                       (volatile u32 *)(CONFIG_SYS_CCSRBAR + 0x1000);
-
-               mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(1);
-               /* mas1 is the same as above */
-               mas2 = FSL_BOOKE_MAS2((u32)ccsr_virt, MAS2_I|MAS2_G);
-               mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0,
-                                               MAS3_SW|MAS3_SR);
-               mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_DEFAULT);
-
-               write_tlb(mas0, mas1, mas2, mas3, mas7);
-
-               temp = in_be32(ccsr_virt);
-               out_be32(ccsr_virt, CONFIG_SYS_CCSRBAR_PHYS >> 12);
-               temp = in_be32((volatile u32 *)CONFIG_SYS_CCSRBAR);
-       }
-#endif
-
-       init_laws();
-       invalidate_tlb(0);
-       init_tlbs();
-}
-
 /*
  * Breathe some life into the CPU...
  *

diff --git a/cpu/mpc85xx/cpu_init_early.c b/cpu/mpc85xx/cpu_init_early.c
new file mode 100644 (file)
index 0000000..7886f86
--- /dev/null
+++ b/cpu/mpc85xx/cpu_init_early.c
@@ -0,0 +1,76 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/fsl_law.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* We run cpu_init_early_f in AS = 1 */
+void cpu_init_early_f(void)
+{
+       u32 mas0, mas1, mas2, mas3, mas7;
+       int i;
+
+       /* Pointer is writable since we allocated a register for it */
+       gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
+
+       /*
+        * Clear initial global data
+        *   we don't use memset so we can share this code with NAND_SPL
+        */
+       for (i = 0; i < sizeof(gd_t); i++)
+               ((char *)gd)[i] = 0;
+
+       mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(0);
+       mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_4K);
+       mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G);
+       mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR);
+       mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_PHYS);
+
+       write_tlb(mas0, mas1, mas2, mas3, mas7);
+
+       /* set up CCSR if we want it moved */
+#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS)
+       {
+               u32 temp;
+               volatile u32 *ccsr_virt =
+                       (volatile u32 *)(CONFIG_SYS_CCSRBAR + 0x1000);
+
+               mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(1);
+               /* mas1 is the same as above */
+               mas2 = FSL_BOOKE_MAS2((u32)ccsr_virt, MAS2_I|MAS2_G);
+               mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0,
+                                               MAS3_SW|MAS3_SR);
+               mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_DEFAULT);
+
+               write_tlb(mas0, mas1, mas2, mas3, mas7);
+
+               temp = in_be32(ccsr_virt);
+               out_be32(ccsr_virt, CONFIG_SYS_CCSRBAR_PHYS >> 12);
+               temp = in_be32((volatile u32 *)CONFIG_SYS_CCSRBAR);
+       }
+#endif
+
+       init_laws();
+       invalidate_tlb(0);
+       init_tlbs();
+}