]> git.sur5r.net Git - u-boot/commitdiff
x86: ivybridge: Move GPIO init to the LPC init() method
authorSimon Glass <sjg@chromium.org>
Sun, 17 Jan 2016 23:11:22 +0000 (16:11 -0700)
committerBin Meng <bmeng.cn@gmail.com>
Sun, 24 Jan 2016 04:08:16 +0000 (12:08 +0800)
This init can happen in the driver also. Move it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
arch/x86/cpu/ivybridge/cpu.c
arch/x86/cpu/ivybridge/lpc.c

index c3626c4f16a75dc9e2af8d2bd32feda48479b50f..6d3f477754eddeff6e654c09c520b0d2bf1a468a 100644 (file)
@@ -278,10 +278,6 @@ int print_cpuinfo(void)
 
        gd->arch.pei_boot_mode = boot_mode;
 
-       /* TODO: Move this to the board or driver */
-       x86_pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1);
-       x86_pci_write_config32(PCH_LPC_DEV, GPIO_CNTL, 0x10);
-
        /* Print processor name */
        name = cpu_get_name(processor_name);
        printf("CPU:   %s\n", name);
index c88733dd3b00bea647967083f07a1373ea1c3c12..0d85de2a766e4b21ff5e9005324d1c11e763a8ba 100644 (file)
@@ -623,6 +623,9 @@ static int bd82x6x_lpc_early_init(struct udevice *dev)
        setbits_le32(RCB_REG(GCS), 1 >> 5);     /* No reset */
        outw(1 << 11, DEFAULT_PMBASE | 0x60 | 0x08);    /* halt timer */
 
+       dm_pci_write_config32(dev->parent, GPIO_BASE, DEFAULT_GPIOBASE | 1);
+       dm_pci_write_config32(dev->parent, GPIO_CNTL, 0x10);
+
        return 0;
 }