]> git.sur5r.net Git - u-boot/commitdiff
mmc: atmel_sdhci: Convert to the driver model support
authorWenyou Yang <wenyou.yang@atmel.com>
Wed, 10 Aug 2016 02:51:05 +0000 (10:51 +0800)
committerAndreas Bießmann <andreas@biessmann.org>
Mon, 15 Aug 2016 20:58:05 +0000 (22:58 +0200)
Convert the driver to the driver model while retaining the existing
legacy code. This allows the driver to support boards that have
converted to driver model as well as those that have not.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
drivers/mmc/Kconfig
drivers/mmc/atmel_sdhci.c
include/sdhci.h

index dc8f2b6852e8b6ba685ea40fd23667e210d8ff62..3616deedf3723ae2f92a4b54a62d9886b1917d2a 100644 (file)
@@ -34,6 +34,16 @@ config MSM_SDHCI
           SD 3.0 specifications. Both SD and eMMC devices are supported.
          Card-detect gpios are not supported.
 
+config ATMEL_SDHCI
+       bool "Atmel SDHCI controller support"
+       depends on DM_MMC && BLK && DM_MMC_OPS && ARCH_AT91
+       help
+         This enables support for the Atmel SDHCI controller, which supports
+         the embedded MultiMedia Card (e.MMC) Specification V4.51, the SD
+         Memory Card Specification V3.0, and the SDIO V3.0 specification.
+         It is compliant with the SD Host Controller Standard V3.0
+         specification.
+
 config ROCKCHIP_DWMMC
        bool "Rockchip SD/MMC controller support"
        depends on DM_MMC && OF_CONTROL
index 24b68b640bbd1fd0cdc9b7bdcdfbf6a8c334665c..dd6bd33515cce0a83583ee17d6c3ae2596f2fd6a 100644 (file)
@@ -6,12 +6,15 @@
  */
 
 #include <common.h>
+#include <clk.h>
+#include <dm.h>
 #include <malloc.h>
 #include <sdhci.h>
 #include <asm/arch/clk.h>
 
 #define ATMEL_SDHC_MIN_FREQ    400000
 
+#ifndef CONFIG_DM_MMC
 int atmel_sdhci_init(void *regbase, u32 id)
 {
        struct sdhci_host *host;
@@ -38,3 +41,123 @@ int atmel_sdhci_init(void *regbase, u32 id)
 
        return 0;
 }
+
+#else
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct atmel_sdhci_plat {
+       struct mmc_config cfg;
+       struct mmc mmc;
+};
+
+static int atmel_sdhci_get_clk(struct udevice *dev, int index, struct clk *clk)
+{
+       struct udevice *dev_clk;
+       int periph, ret;
+
+       ret = clk_get_by_index(dev, index, clk);
+       if (ret)
+               return ret;
+
+       periph = fdtdec_get_uint(gd->fdt_blob, clk->dev->of_offset, "reg", -1);
+       if (periph < 0)
+               return -EINVAL;
+
+       dev_clk = dev_get_parent(clk->dev);
+       ret = clk_request(dev_clk, clk);
+       if (ret)
+               return ret;
+
+       clk->id = periph;
+
+       return 0;
+}
+
+static int atmel_sdhci_probe(struct udevice *dev)
+{
+       struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+       struct atmel_sdhci_plat *plat = dev_get_platdata(dev);
+       struct sdhci_host *host = dev_get_priv(dev);
+       u32 max_clk;
+       u32 caps, caps_1;
+       u32 clk_base, clk_mul;
+       ulong gck_rate;
+       struct clk clk;
+       int ret;
+
+       ret = atmel_sdhci_get_clk(dev, 0, &clk);
+       if (ret)
+               return ret;
+
+       ret = clk_enable(&clk);
+       if (ret)
+               return ret;
+
+       host->name = dev->name;
+       host->ioaddr = (void *)dev_get_addr(dev);
+
+       host->quirks = 0;
+       host->bus_width = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+                                        "bus-width", 4);
+
+       caps = sdhci_readl(host, SDHCI_CAPABILITIES);
+       clk_base = (caps & SDHCI_CLOCK_V3_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
+       caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
+       clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >> SDHCI_CLOCK_MUL_SHIFT;
+       gck_rate = clk_base * 1000000 * (clk_mul + 1);
+
+       ret = atmel_sdhci_get_clk(dev, 1, &clk);
+       if (ret)
+               return ret;
+
+       ret = clk_set_rate(&clk, gck_rate);
+       if (ret)
+               return ret;
+
+       max_clk = clk_get_rate(&clk);
+       if (!max_clk)
+               return -EINVAL;
+
+       ret = sdhci_setup_cfg(&plat->cfg, host, max_clk, ATMEL_SDHC_MIN_FREQ);
+       if (ret)
+               return ret;
+
+       host->mmc = &plat->mmc;
+       host->mmc->dev = dev;
+       host->mmc->priv = host;
+       upriv->mmc = host->mmc;
+
+       clk_free(&clk);
+
+       return sdhci_probe(dev);
+}
+
+static int atmel_sdhci_bind(struct udevice *dev)
+{
+       struct atmel_sdhci_plat *plat = dev_get_platdata(dev);
+       int ret;
+
+       ret = sdhci_bind(dev, &plat->mmc, &plat->cfg);
+       if (ret)
+               return ret;
+
+       return 0;
+}
+
+static const struct udevice_id atmel_sdhci_ids[] = {
+       { .compatible = "atmel,sama5d2-sdhci" },
+       { }
+};
+
+U_BOOT_DRIVER(atmel_sdhci_drv) = {
+       .name           = "atmel_sdhci",
+       .id             = UCLASS_MMC,
+       .of_match       = atmel_sdhci_ids,
+       .ops            = &sdhci_ops,
+       .bind           = atmel_sdhci_bind,
+       .probe          = atmel_sdhci_probe,
+       .priv_auto_alloc_size = sizeof(struct sdhci_host),
+       .platdata_auto_alloc_size = sizeof(struct atmel_sdhci_plat),
+};
+#endif
index fcef4dc065a84cd54b65027cb95e445907f231ae..6844c73bdc58b89af217f9ed80e3e369bee76ab7 100644 (file)
 #define  SDHCI_CAN_64BIT       0x10000000
 
 #define SDHCI_CAPABILITIES_1   0x44
+#define  SDHCI_CLOCK_MUL_MASK  0x00FF0000
+#define  SDHCI_CLOCK_MUL_SHIFT 16
 
 #define SDHCI_MAX_CURRENT      0x48