strider: use optimised bus timing for FPGA access

Use optimised bus timing for FPGA access.

Signed-off-by: Reinhard Pfau <reinhard.pfau@gdsys.cc>
Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>

diff --git a/include/configs/strider.h b/include/configs/strider.h
index 7d9541bd83a06fd443b20e3516c6c96be1cb079f..d5f1981c0d28a58a7f0935a4d058d1c8ba02d83d 100644 (file)
--- a/include/configs/strider.h
+++ b/include/configs/strider.h
@@ -279,14 +279,13 @@
                                | BR_PS_16      /* 16 bit port */ \
                                | BR_MS_GPCM    /* MSEL = GPCM */ \
                                | BR_V)         /* valid */
-#define CONFIG_SYS_OR1_PRELIM  (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \
+
+#define CONFIG_SYS_OR1_PRELIM   (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \
                                | OR_UPM_XAM \
                                | OR_GPCM_CSNT \
-                               | OR_GPCM_ACS_DIV2 \
-                               | OR_GPCM_XACS \
-                               | OR_GPCM_SCY_15 \
-                               | OR_GPCM_TRLX_SET \
-                               | OR_GPCM_EHTR_SET)
+                               | OR_GPCM_SCY_5 \
+                               | OR_GPCM_TRLX_CLEAR \
+                               | OR_GPCM_EHTR_CLEAR)
 
 #define CONFIG_SYS_FPGA_BASE(k)                CONFIG_SYS_FPGA0_BASE
 #define CONFIG_SYS_FPGA_DONE(k)                0x0010