Add MPC8343 based board mvBlueLYNX-M7.
It's a single board stereo camera system.
Please read doc/README.mvblm7 for details.
Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
MPC8360ERDK_66 \
MPC837XEMDS \
MPC837XERDB \
+ MVBLM7 \
sbc8349 \
TQM834x \
"
MPC837XERDB_config: unconfig
@$(MKCONFIG) -a MPC837XERDB ppc mpc83xx mpc837xerdb freescale
+MVBLM7_config: unconfig
+ @$(MKCONFIG) $(@:_config=) ppc mpc83xx mvblm7
+
sbc8349_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc83xx sbc8349
--- /dev/null
+#
+# Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := $(BOARD).o pci.o fpga.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#
+# Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+
+TEXT_BASE = 0xFFF00000
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ * Keith Outwater, keith_outwater@mvis.com.
+ *
+ * (C) Copyright 2008
+ * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <ACEX1K.h>
+#include <command.h>
+#include "fpga.h"
+#include "mvblm7.h"
+
+#ifdef FPGA_DEBUG
+#define fpga_debug(fmt, args...) printf("%s: "fmt, __func__, ##args)
+#else
+#define fpga_debug(fmt, args...)
+#endif
+
+Altera_CYC2_Passive_Serial_fns altera_fns = {
+ fpga_null_fn,
+ fpga_config_fn,
+ fpga_status_fn,
+ fpga_done_fn,
+ fpga_wr_fn,
+ fpga_null_fn,
+ fpga_null_fn,
+ 0
+};
+
+Altera_desc cyclone2 = {
+ Altera_CYC2,
+ passive_serial,
+ Altera_EP2C20_SIZE,
+ (void *) &altera_fns,
+ NULL,
+ 0
+};
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int mvblm7_init_fpga(void)
+{
+ fpga_debug("Initialize FPGA interface (reloc 0x%.8lx)\n",
+ gd->reloc_off);
+ fpga_init(gd->reloc_off);
+ fpga_add(fpga_altera, &cyclone2);
+ fpga_config_fn(0, 1, 0);
+ udelay(60);
+
+ return 1;
+}
+
+int fpga_null_fn(int cookie)
+{
+ return 0;
+}
+
+int fpga_config_fn(int assert, int flush, int cookie)
+{
+ volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
+ volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
+ u32 dvo = gpio->dat;
+
+ fpga_debug("SET config : %s\n", assert ? "low" : "high");
+ if (assert)
+ dvo |= FPGA_CONFIG;
+ else
+ dvo &= ~FPGA_CONFIG;
+
+ if (flush)
+ gpio->dat = dvo;
+
+ return assert;
+}
+
+int fpga_done_fn(int cookie)
+{
+ volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
+ volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
+ int result = 0;
+
+ udelay(10);
+ fpga_debug("CONF_DONE check ... ");
+ if (gpio->dat & FPGA_CONF_DONE) {
+ fpga_debug("high\n");
+ result = 1;
+ } else
+ fpga_debug("low\n");
+
+ return result;
+}
+
+int fpga_status_fn(int cookie)
+{
+ volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
+ volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
+ int result = 0;
+
+ fpga_debug("STATUS check ... ");
+ if (gpio->dat & FPGA_STATUS) {
+ fpga_debug("high\n");
+ result = 1;
+ } else
+ fpga_debug("low\n");
+
+ return result;
+}
+
+int fpga_clk_fn(int assert_clk, int flush, int cookie)
+{
+ volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
+ volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
+ u32 dvo = gpio->dat;
+
+ fpga_debug("CLOCK %s\n", assert_clk ? "high" : "low");
+ if (assert_clk)
+ dvo |= FPGA_CCLK;
+ else
+ dvo &= ~FPGA_CCLK;
+
+ if (flush)
+ gpio->dat = dvo;
+
+ return assert_clk;
+}
+
+static inline int _write_fpga(u8 val, int dump)
+{
+ volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
+ volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
+ int i;
+ u32 dvo = gpio->dat;
+
+ if (dump)
+ fpga_debug(" %02x -> ", val);
+ for (i = 0; i < 8; i++) {
+ dvo &= ~FPGA_CCLK;
+ gpio->dat = dvo;
+ dvo &= ~FPGA_DIN;
+ if (dump)
+ fpga_debug("%d ", val&1);
+ if (val & 1)
+ dvo |= FPGA_DIN;
+ gpio->dat = dvo;
+ dvo |= FPGA_CCLK;
+ gpio->dat = dvo;
+ val >>= 1;
+ }
+ if (dump)
+ fpga_debug("\n");
+
+ return 0;
+}
+
+int fpga_wr_fn(void *buf, size_t len, int flush, int cookie)
+{
+ unsigned char *data = (unsigned char *) buf;
+ int i;
+
+ fpga_debug("fpga_wr: buf %p / size %d\n", buf, len);
+ for (i = 0; i < len; i++)
+ _write_fpga(data[i], 0);
+ fpga_debug("\n");
+
+ return FPGA_SUCCESS;
+}
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ * Keith Outwater, keith_outwater@mvis.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+extern int mvblm7_init_fpga(void);
+
+extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
+extern int fpga_status_fn(int cookie);
+extern int fpga_config_fn(int assert, int flush, int cookie);
+extern int fpga_done_fn(int cookie);
+extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
+extern int fpga_wr_fn(void *buf, size_t len, int flush, int cookie);
+extern int fpga_null_fn(int cookie);
--- /dev/null
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
+ *
+ * (C) Copyright 2008
+ * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc83xx.h>
+#include <asm/mpc8349_pci.h>
+#include <pci.h>
+#include <spi.h>
+#include <asm/mmu.h>
+#if defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#endif
+
+#include "mvblm7.h"
+
+int fixed_sdram(void)
+{
+ volatile immap_t *im = (immap_t *)CFG_IMMR;
+ u32 msize = 0;
+ u32 ddr_size;
+ u32 ddr_size_log2;
+
+ msize = CFG_DDR_SIZE;
+ for (ddr_size = msize << 20, ddr_size_log2 = 0;
+ (ddr_size > 1);
+ ddr_size = ddr_size >> 1, ddr_size_log2++) {
+ if (ddr_size & 1)
+ return -1;
+ }
+ im->sysconf.ddrlaw[0].bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
+ im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) &
+ LAWAR_SIZE);
+
+ im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS;
+ im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG;
+ im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
+ im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
+ im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
+ im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
+ im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
+ im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
+ im->ddr.sdram_mode = CFG_DDR_MODE;
+ im->ddr.sdram_interval = CFG_DDR_INTERVAL;
+ im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL;
+
+ udelay(300);
+
+ im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
+
+ return CFG_DDR_SIZE;
+}
+
+long int initdram(int board_type)
+{
+ volatile immap_t *im = (immap_t *) CFG_IMMR;
+ u32 msize = 0;
+
+ if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
+ return -1;
+
+ im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
+ msize = fixed_sdram();
+
+ /* return total bus RAM size(bytes) */
+ return msize * 1024 * 1024;
+}
+
+int checkboard(void)
+{
+ puts("Board: Matrix Vision mvBlueLYNX-M7 " MV_VERSION "\n");
+
+ return 0;
+}
+
+u8 *dhcp_vendorex_prep(u8 *e)
+{
+ char *ptr;
+
+ /* DHCP vendor-class-identifier = 60 */
+ ptr = getenv("dhcp_vendor-class-identifier");
+ if (ptr) {
+ *e++ = 60;
+ *e++ = strlen(ptr);
+ while (*ptr)
+ *e++ = *ptr++;
+ }
+ /* DHCP_CLIENT_IDENTIFIER = 61 */
+ ptr = getenv("dhcp_client_id");
+ if (ptr) {
+ *e++ = 61;
+ *e++ = strlen(ptr);
+ while (*ptr)
+ *e++ = *ptr++;
+ }
+
+ return e;
+}
+
+u8 *dhcp_vendorex_proc(u8 *popt)
+{
+ return NULL;
+}
+
+#ifdef CONFIG_HARD_SPI
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return bus == 0 && cs == 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0];
+
+ iopd->dat &= ~MVBLM7_MMC_CS;
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0];
+
+ iopd->dat |= ~MVBLM7_MMC_CS;
+}
+#endif
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+#ifdef CONFIG_PCI
+ ft_pci_setup(blob, bd);
+#endif
+}
+
+#endif
--- /dev/null
+#ifndef __MVBC_H__
+#define __MVBC_H__
+
+#define MV_GPIO
+
+#define FPGA_CONFIG 0x80000000
+#define FPGA_CCLK 0x40000000
+#define FPGA_DIN 0x20000000
+#define FPGA_STATUS 0x10000000
+#define FPGA_CONF_DONE 0x08000000
+#define MMC_CS 0x04000000
+
+#define WD_WDI 0x00400000
+#define WD_TS 0x00200000
+#define MAN_RST 0x00100000
+
+#define MV_GPIO_DAT (WD_TS)
+#define MV_GPIO_OUT (FPGA_CONFIG|FPGA_DIN|FPGA_CCLK|WD_TS|WD_WDI|MMC_CS)
+#define MV_GPIO_ODE (FPGA_CONFIG|MAN_RST)
+
+#endif
--- /dev/null
+echo
+echo "==== running autoscript ===="
+echo
+setenv bootdtb bootm \${kernel_boot} \${mv_initrd_addr_ram} \${mv_dtb_addr_ram}
+setenv ramkernel setenv kernel_boot \${loadaddr}
+setenv flashkernel setenv kernel_boot \${mv_kernel_addr}
+setenv cpird cp \${mv_initrd_addr} \${mv_initrd_addr_ram} \${mv_initrd_length}
+setenv bootfromflash run flashkernel cpird ramparam bootdtb
+setenv getdtb tftp \${mv_dtb_addr_ram} \${dtb_name}
+setenv cpdtb cp \${mv_dtb_addr} \${mv_dtb_addr_ram} 0x2000
+setenv rundtb fdt addr \${mv_dtb_addr_ram}\;fdt boardsetup
+setenv bootfromnet tftp \${mv_initrd_addr_ram} \${initrd_name}\;run ramkernel
+setenv set_static_ip setenv ipaddr \${static_ipaddr}
+setenv set_static_nm setenv netmask \${static_netmask}
+setenv set_static_gw setenv gatewayip \${static_gateway}
+setenv set_ip setenv ip \${ipaddr}::\${gatewayip}:\${netmask}
+setenv ramparam setenv bootargs root=/dev/ram0 ro rootfstype=squashfs
+if test ${autoscr_boot} != no;
+then
+ if test ${netboot} = yes;
+ then
+ bootp
+ if test $? = 0;
+ then
+ echo "=== bootp succeeded -> netboot ==="
+ run set_ip
+ run getdtb rundtb bootfromnet ramparam bootdtb
+ else
+ echo "=== netboot failed ==="
+ fi
+ fi
+ run set_static_ip set_static_nm set_static_gw set_ip
+ echo "=== bootfromflash ==="
+ run cpdtb rundtb bootfromflash
+else
+ echo "=== boot stopped with autoscr_boot no ==="
+fi
--- /dev/null
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
+ *
+ * (C) Copyright 2008
+ * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#if defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#endif
+#include <pci.h>
+#include <mpc83xx.h>
+#include "mvblm7.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* System RAM mapped to PCI space */
+#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
+
+#define SLOT0_IRQ 3
+#define SLOT1_IRQ 4
+void pci_mvblm7_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+{
+ unsigned char line = 0xff;
+
+ if (PCI_BUS(dev) == 0) {
+ switch (PCI_DEV(dev)) {
+ case 0x0:
+ return;
+ case 0xb:
+ line = 0;
+ break;
+ case 0xc:
+ line = 1;
+ break;
+ default:
+ printf("***pci_scan: illegal dev = 0x%08x\n",
+ PCI_DEV(dev));
+ line = 0xff;
+ break;
+ }
+ pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, line);
+ }
+}
+
+static struct pci_controller pci_hose = {
+ fixup_irq:pci_mvblm7_fixup_irq
+};
+
+int mvblm7_load_fpga(void)
+{
+ size_t data_size = 0;
+ void *fpga_data = NULL;
+ char *datastr = getenv("fpgadata");
+ char *sizestr = getenv("fpgadatasize");
+
+ if (datastr)
+ fpga_data = (void *)simple_strtoul(datastr, NULL, 16);
+ if (sizestr)
+ data_size = (size_t)simple_strtoul(sizestr, NULL, 16);
+
+ return fpga_load(0, fpga_data, data_size);
+}
+
+static struct pci_region pci_regions[] = {
+ {
+ bus_start: CFG_PCI1_MEM_BASE,
+ phys_start: CFG_PCI1_MEM_PHYS,
+ size: CFG_PCI1_MEM_SIZE,
+ flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+ },
+ {
+ bus_start: CFG_PCI1_MMIO_BASE,
+ phys_start: CFG_PCI1_MMIO_PHYS,
+ size: CFG_PCI1_MMIO_SIZE,
+ flags: PCI_REGION_MEM
+ },
+ {
+ bus_start: CFG_PCI1_IO_BASE,
+ phys_start: CFG_PCI1_IO_PHYS,
+ size: CFG_PCI1_IO_SIZE,
+ flags: PCI_REGION_IO
+ }
+};
+
+void pci_init_board(void)
+{
+ char *s;
+ int i;
+ int warmboot;
+ int load_fpga;
+ volatile immap_t *immr;
+ volatile pcictrl83xx_t *pci_ctrl;
+ volatile gpio83xx_t *gpio;
+ volatile clk83xx_t *clk;
+ volatile law83xx_t *pci_law;
+ struct pci_region *reg[] = { pci_regions };
+
+ load_fpga = 1;
+ immr = (immap_t *) CFG_IMMR;
+ clk = (clk83xx_t *) &immr->clk;
+ pci_ctrl = immr->pci_ctrl;
+ pci_law = immr->sysconf.pcilaw;
+ gpio = (volatile gpio83xx_t *)&immr->gpio[0];
+
+ s = getenv("skip_fpga");
+ if (s) {
+ printf("found 'skip_fpga' -> FPGA _not_ loaded !\n");
+ load_fpga = 0;
+ }
+
+ gpio->dat = MV_GPIO_DAT;
+ gpio->odr = MV_GPIO_ODE;
+ if (load_fpga)
+ gpio->dir = MV_GPIO_OUT;
+ else
+ gpio->dir = MV_GPIO_OUT & ~(FPGA_DIN|FPGA_CCLK);
+
+ printf("SICRH / SICRL : 0x%08x / 0x%08x\n", immr->sysconf.sicrh,
+ immr->sysconf.sicrl);
+
+ mvblm7_init_fpga();
+ if (load_fpga)
+ mvblm7_load_fpga();
+
+ /* Enable PCI_CLK_OUTPUTs 0 and 1 with 1:1 clocking */
+ clk->occr = 0xc0000000;
+
+ pci_ctrl[0].gcr = 0;
+ udelay(2000);
+ pci_ctrl[0].gcr = 1;
+
+ for (i = 0; i < 1000; ++i)
+ udelay(1000);
+
+ pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
+ pci_law[0].ar = LBLAWAR_EN | LBLAWAR_1GB;
+
+ pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
+ pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
+
+ warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM;
+
+ mpc83xx_pci_init(1, reg, warmboot);
+}
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