struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
u32 usb_pwrfault;
+ if (hwconfig("qe-hdlc")) {
+ out_be32(&scfg->rcwpmuxcr0,
+ (in_be32(&scfg->rcwpmuxcr0) & ~0xff00) | 0x6600);
+ printf("Assign to qe-hdlc clk, rcwpmuxcr0=%x\n",
+ in_be32(&scfg->rcwpmuxcr0));
+ } else {
#ifdef CONFIG_HAS_FSL_XHCI_USB
- out_be32(&scfg->rcwpmuxcr0, 0x3333);
- out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
- usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
- SCFG_USBPWRFAULT_USB3_SHIFT) |
- (SCFG_USBPWRFAULT_DEDICATED <<
- SCFG_USBPWRFAULT_USB2_SHIFT) |
- (SCFG_USBPWRFAULT_SHARED <<
- SCFG_USBPWRFAULT_USB1_SHIFT);
- out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
+ out_be32(&scfg->rcwpmuxcr0, 0x3333);
+ out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
+ usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
+ SCFG_USBPWRFAULT_USB3_SHIFT) |
+ (SCFG_USBPWRFAULT_DEDICATED <<
+ SCFG_USBPWRFAULT_USB2_SHIFT) |
+ (SCFG_USBPWRFAULT_SHARED <<
+ SCFG_USBPWRFAULT_USB1_SHIFT);
+ out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
#endif
-
+ }
return 0;
}
}
#endif
+void fdt_del_qe(void *blob)
+{
+ int nodeoff = 0;
+
+ while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
+ "fsl,qe")) >= 0) {
+ fdt_del_node(blob, nodeoff);
+ }
+}
+
int ft_board_setup(void *blob, bd_t *bd)
{
u64 base[CONFIG_NR_DRAM_BANKS];
#ifdef CONFIG_SYS_DPAA_FMAN
fdt_fixup_fman_ethernet(blob);
#endif
+
+ /*
+ * qe-hdlc and usb multi-use the pins,
+ * when set hwconfig to qe-hdlc, delete usb node.
+ */
+ if (hwconfig("qe-hdlc"))
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+ fdt_del_node_and_alias(blob, "usb1");
+#endif
+ /*
+ * qe just support qe-uart and qe-hdlc,
+ * if qe-uart and qe-hdlc are not set in hwconfig,
+ * delete qe node.
+ */
+ if (!hwconfig("qe-uart") && !hwconfig("qe-hdlc"))
+ fdt_del_qe(blob);
+
return 0;
}