u32 tmp[] = { 32, 0x8, 33, 0x8, 34, 0x8 };
 
                                path = fdt_path_offset(blob, prop);
-                               prop = fdt_getprop(blob, path, "interrupts", 0);
+                               prop = fdt_getprop(blob, path, "interrupts",
+                                                  NULL);
                                if (prop)
                                        fdt_setprop(blob, path, "interrupts",
                                                    &tmp, sizeof(tmp));
                                u32 tmp[] = { 35, 0x8, 36, 0x8, 37, 0x8 };
 
                                path = fdt_path_offset(blob, prop);
-                               prop = fdt_getprop(blob, path, "interrupts", 0);
+                               prop = fdt_getprop(blob, path, "interrupts",
+                                                  NULL);
                                if (prop)
                                        fdt_setprop(blob, path, "interrupts",
                                                    &tmp, sizeof(tmp));
 
        mult_t vco_divider;
 } corecnf_t;
 
-corecnf_t corecnf_tab[] = {
+static corecnf_t corecnf_tab[] = {
        {_byp, _byp},           /* 0x00 */
        {_byp, _byp},           /* 0x01 */
        {_byp, _byp},           /* 0x02 */
        return gd->mem_clk;
 }
 
-int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
        char buf[32];
 
 
 #ifndef CONFIG_NAND_SPL
 static struct pci_region pci_regions[] = {
        {
-               bus_start: CONFIG_SYS_PCI1_MEM_BASE,
-               phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
-               size: CONFIG_SYS_PCI1_MEM_SIZE,
-               flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+               .bus_start = CONFIG_SYS_PCI1_MEM_BASE,
+               .phys_start = CONFIG_SYS_PCI1_MEM_PHYS,
+               .size = CONFIG_SYS_PCI1_MEM_SIZE,
+               .flags = PCI_REGION_MEM | PCI_REGION_PREFETCH
        },
        {
-               bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
-               phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
-               size: CONFIG_SYS_PCI1_MMIO_SIZE,
-               flags: PCI_REGION_MEM
+               .bus_start = CONFIG_SYS_PCI1_MMIO_BASE,
+               .phys_start = CONFIG_SYS_PCI1_MMIO_PHYS,
+               .size = CONFIG_SYS_PCI1_MMIO_SIZE,
+               .flags = PCI_REGION_MEM
        },
        {
-               bus_start: CONFIG_SYS_PCI1_IO_BASE,
-               phys_start: CONFIG_SYS_PCI1_IO_PHYS,
-               size: CONFIG_SYS_PCI1_IO_SIZE,
-               flags: PCI_REGION_IO
+               .bus_start = CONFIG_SYS_PCI1_IO_BASE,
+               .phys_start = CONFIG_SYS_PCI1_IO_PHYS,
+               .size = CONFIG_SYS_PCI1_IO_SIZE,
+               .flags = PCI_REGION_IO
        }
 };