p1022ds: add audclk hwconfig setting to enable codec reference clock

The Freescale P1022DS can use either a 12.288MHz or a 11.2896MHz reference
clock for the audio codec, but by default both are disabled.  Add a 'audclk'
hwconfig option that allows the user to choose which clock he wants.

The 12.288MHz clock allows the codec to use sampling rates of 16, 24, 32, 48,
64, and 96KHz.  The 11.2896 clock allows 14700, 22050, 29400, 44100, 58800, and
88200Hz.

Also configure a pin muxing to select some SSI signals, which will disable
I2C1.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c
index 5cdee9ff70f03cafbffd397f04c8e1ae909fd562..ee93e8b8156f930352253a59b88b75164c9dace2 100644 (file)
--- a/board/freescale/p1022ds/p1022ds.c
+++ b/board/freescale/p1022ds/p1022ds.c
@@ -27,6 +27,7 @@
 #include <asm/mp.h>
 #include <netdev.h>
 #include <i2c.h>
+#include <hwconfig.h>
 
 #include "../common/ngpixis.h"
 
@@ -90,34 +91,58 @@ phys_size_t initdram(int board_type)
 
 #define CONFIG_TFP410_I2C_ADDR 0x38
 
+/* Masks for the SSI_TDM and AUDCLK bits of the ngPIXIS BRDCFG1 register. */
+#define CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK      0x0c
+#define CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK       0x03
+
+/* Route the I2C1 pins to the SSI port instead. */
+#define CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI       0x08
+
+/* Choose the 12.288Mhz codec reference clock */
+#define CONFIG_PIXIS_BRDCFG1_AUDCLK_12         0x02
+
+/* Choose the 11.2896Mhz codec reference clock */
+#define CONFIG_PIXIS_BRDCFG1_AUDCLK_11         0x01
+
 int misc_init_r(void)
 {
        u8 temp;
+       const char *audclk;
+       size_t arglen;
 
-       /*  Enable the TFP410 Encoder */
+       /* For DVI, enable the TFP410 Encoder. */
 
        temp = 0xBF;
        if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
                return -1;
-
-       /* Verify if enabled */
-       temp = 0;
        if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
                return -1;
-
        debug("DVI Encoder Read: 0x%02x\n", temp);
 
        temp = 0x10;
        if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
                return -1;
-
-       /* Verify if enabled */
-       temp = 0;
        if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
                return -1;
-
        debug("DVI Encoder Read: 0x%02x\n",temp);
 
+       /*
+        * Enable the reference clock for the WM8776 codec, and route the MUX
+        * pins for SSI. The default is the 12.288 MHz clock
+        */
+
+       temp = in_8(&pixis->brdcfg1) & ~(CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK |
+               CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK);
+       temp |= CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI;
+
+       audclk = hwconfig_arg("audclk", &arglen);
+       /* Check the first two chars only */
+       if (audclk && (strncmp(audclk, "11", 2) == 0))
+               temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_11;
+       else
+               temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_12;
+       out_8(&pixis->brdcfg1, temp);
+
        return 0;
 }
 
@@ -310,6 +335,27 @@ int board_eth_init(bd_t *bis)
 }
 
 #ifdef CONFIG_OF_BOARD_SETUP
+/**
+ * ft_codec_setup - fix up the clock-frequency property of the codec node
+ *
+ * Update the clock-frequency property based on the value of the 'audclk'
+ * hwconfig option.  If audclk is not specified, then default to 12.288MHz.
+ */
+static void ft_codec_setup(void *blob, const char *compatible)
+{
+       const char *audclk;
+       size_t arglen;
+       u32 freq;
+
+       audclk = hwconfig_arg("audclk", &arglen);
+       if (audclk && (strncmp(audclk, "11", 2) == 0))
+               freq = 11289600;
+       else
+               freq = 12288000;
+
+       do_fixup_by_compat_u32(blob, compatible, "clock-frequency", freq, 1);
+}
+
 void ft_board_setup(void *blob, bd_t *bd)
 {
        phys_addr_t base;
@@ -327,6 +373,9 @@ void ft_board_setup(void *blob, bd_t *bd)
 #ifdef CONFIG_FSL_SGMII_RISER
        fsl_sgmii_riser_fdt_fixup(blob);
 #endif
+
+       /* Update the WM8776 node's clock frequency property */
+       ft_codec_setup(blob, "wlf,wm8776");
 }
 #endif
 

diff --git a/doc/README.fsl-hwconfig b/doc/README.fsl-hwconfig
new file mode 100644 (file)
index 0000000..03fea74
--- /dev/null
+++ b/doc/README.fsl-hwconfig
@@ -0,0 +1,21 @@
+Freescale-specific 'hwconfig' options.
+
+This file documents Freescale-specific key:value pairs for the 'hwconfig'
+option.  See README.hwconfig for general information about 'hwconfig'.
+
+audclk
+       Specific to the P1022DS reference board.
+
+       This option specifies which of the two oscillator frequencies should be
+       routed to the Wolfson WM8776 codec.  The ngPIXIS can be programmed to
+       route either a 11.2896MHz or a 12.288MHz clock.  The default is
+       12.288MHz.  This option has two effects.  First, the MUX on the board
+       will be programmed accordingly.  Second, the clock-frequency property
+       in the codec node in the device tree will be updated to the correct
+       value.
+
+       'audclk:11'
+               Select the 11.2896MHz clock
+
+       'audclk:12'
+               Select the 12.288MHz clock

diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h
index 2306e7f90c961c30aa25c8ed3f051e557ef24cce..da826fc26f526f5f6b9823bd1c6fc3b2f52dc41b 100644 (file)
--- a/include/configs/P1022DS.h
+++ b/include/configs/P1022DS.h
@@ -134,6 +134,7 @@
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_BOARD_EARLY_INIT_R
 #define CONFIG_MISC_INIT_R
+#define CONFIG_HWCONFIG
 
 #define CONFIG_FSL_NGPIXIS
 #define PIXIS_BASE             0xffdf0000      /* PIXIS registers */