ppc4xx: Update lwmon5 board support

This patch includes the following changes for the lwmon5 board support:

- Enable cache in SDRAM
- Use common EHCI driver instead of the PPC4xx specific OHCI driver
  This can be done since only high-speed devices are connected.
- Remove cached TLB entry again after ECC setup
- Use correct define for cache enabling
  (CONFIG_4xx_DCACHE instead of CONFIG_SYS_ENABLE_SDRAM_CACHE)
- Enable FIT image support

Signed-off-by: Stefan Roese <sr@denx.de>

diff --git a/board/lwmon5/sdram.c b/board/lwmon5/sdram.c
index f90efebb8a53ee02f7bc5af8788e076cf0763e63..b64b35a94ea2251cf2eeac3e397523b4c4869a51 100644 (file)
--- a/board/lwmon5/sdram.c
+++ b/board/lwmon5/sdram.c
@@ -45,10 +45,10 @@
  * memory.
  *
  * If at some time this restriction doesn't apply anymore, just define
- * CONFIG_SYS_ENABLE_SDRAM_CACHE in the board config file and this code should setup
+ * CONFIG_4xx_DCACHE in the board config file and this code should setup
  * everything correctly.
  */
-#ifdef CONFIG_SYS_ENABLE_SDRAM_CACHE
+#ifdef CONFIG_4xx_DCACHE
 #define MY_TLB_WORD2_I_ENABLE  0                       /* enable caching on SDRAM */
 #else
 #define MY_TLB_WORD2_I_ENABLE  TLB_WORD2_I_ENABLE      /* disable caching on SDRAM */
@@ -220,18 +220,32 @@ phys_size_t initdram (int board_type)
        program_tlb(0, CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20,
                    MY_TLB_WORD2_I_ENABLE);
 
+#if defined(CONFIG_DDR_ECC)
+#if defined(CONFIG_4xx_DCACHE)
+       /*
+        * If ECC is enabled, initialize the parity bits.
+        */
+       program_ecc(0, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
+#else /* CONFIG_4xx_DCACHE */
        /*
         * Setup 2nd TLB with same physical address but different virtual address
         * with cache enabled. This is done for fast ECC generation.
         */
        program_tlb(0, CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
 
-#ifdef CONFIG_DDR_ECC
        /*
         * If ECC is enabled, initialize the parity bits.
         */
        program_ecc(CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
-#endif
+
+       /*
+        * Now after initialization (auto-calibration and ECC generation)
+        * remove the TLB entries with caches enabled and program again with
+        * desired cache functionality
+        */
+       remove_tlb(CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20);
+#endif /* CONFIG_4xx_DCACHE */
+#endif /* CONFIG_DDR_ECC */
 
        /*
         * Clear possible errors resulting from data-eye-search.

diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h
index 4c9744ca4fa16fdacbbe32a6a0eb6ad3c0c6a538..aedf49510490fb059a64175035a14bc708b77a65 100644 (file)
--- a/include/configs/lwmon5.h
+++ b/include/configs/lwmon5.h
@@ -43,6 +43,8 @@
 
 #define CONFIG_SYS_CLK_FREQ    33300000        /* external freq to pll */
 
+#define CONFIG_4xx_DCACHE              /* enable cache in SDRAM        */
+
 #define CONFIG_BOARD_EARLY_INIT_F      /* Call board_early_init_f      */
 #define CONFIG_BOARD_EARLY_INIT_R      /* Call board_early_init_r      */
 #define CONFIG_BOARD_POSTCLK_INIT      /* Call board_postclk_init      */
@@ -321,6 +323,8 @@
 /* Update size in "reg" property of NOR FLASH device tree nodes */
 #define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
 
+#define CONFIG_FIT                     /* enable FIT image support     */
+
 #define        CONFIG_POST_KEY_MAGIC   "3C+3E" /* press F3 + F5 keys to force POST */
 
 #define        CONFIG_PREBOOT          "setenv bootdelay 15"
@@ -393,16 +397,18 @@
 #define CONFIG_VIDEO_SW_CURSOR
 #define CONFIG_SPLASH_SCREEN
 
-/* USB */
-#ifdef CONFIG_440EPX
-#define CONFIG_USB_OHCI
+/*
+ * USB/EHCI
+ */
+#define CONFIG_USB_EHCI                        /* Enable EHCI USB support      */
+#define CONFIG_USB_EHCI_PPC4XX         /* on PPC4xx platform           */
+#define CONFIG_SYS_PPC4XX_USB_ADDR     0xe0000300
+#define CONFIG_EHCI_DCACHE             /* with dcache handling support */
+#define CONFIG_EHCI_MMIO_BIG_ENDIAN
+#define CONFIG_EHCI_DESC_BIG_ENDIAN
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* re-init HCD after CMD_RESET */
 #define CONFIG_USB_STORAGE
 
-/* Comment this out to enable USB 1.1 device */
-#define USB_2_0_DEVICE
-
-#endif /* CONFIG_440EPX */
-
 /* Partitions */
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION