#endif
#ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */
(ACR_RPTCNT << ACR_RPTCNT_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_ACR_APARK /* Arbiter address parking mode */
+ (ACR_APARK << ACR_APARK_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_ACR_PARKM /* Arbiter parking master */
+ (ACR_PARKM << ACR_PARKM_SHIFT) |
#endif
0;
__be32 acr_val =
#endif
#ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */
(CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_ACR_APARK /* Arbiter address parking mode */
+ (CONFIG_SYS_ACR_APARK << ACR_APARK_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_ACR_PARKM /* Arbiter parking master */
+ (CONFIG_SYS_ACR_PARKM << ACR_PARKM_SHIFT) |
#endif
0;
__be32 spcr_mask =
*/
#define CONFIG_SYS_IMMR 0xE0000000
+/*
+ * Bus Arbitration Configuration Register (ACR)
+ */
+#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */
+#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */
+#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */
+#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */
+
/*
* DDR Setup
*/