ppc4xx: Prepare Bamboo port for NAND booting support

This patch updates the "normal" Bamboo NOR booting port, so
that it is compatible with the coming soon NAND booting
Bamboo port.

It also enables the 2nd NAND flash on the Bamboo.

Signed-off-by: Stefan Roese <sr@denx.de>

diff --git a/board/amcc/bamboo/Makefile b/board/amcc/bamboo/Makefile
index 5da96e9e1c846aaab582cd468654ae8debc73520..d01cc49e2ce6a3914867367087fc98158d900ec5 100644 (file)
--- a/board/amcc/bamboo/Makefile
+++ b/board/amcc/bamboo/Makefile
@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2002-2006
+# (C) Copyright 2002-2007
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
@@ -33,7 +33,7 @@ OBJS  := $(addprefix $(obj),$(COBJS))
 SOBJS  := $(addprefix $(obj),$(SOBJS))
 
 $(LIB):        $(OBJS) $(SOBJS)
-       $(AR) $(ARFLAGS) $@ $(OBJS)
+       $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
 
 clean:
        rm -f $(SOBJS) $(OBJS)

diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c
index 6260b016df3d1f5a8f9aab896d9d26b5be38df0a..2e651df3b79df55ae3b2f3905f1b2d2e3a1c87bd 100644 (file)
--- a/board/amcc/bamboo/bamboo.c
+++ b/board/amcc/bamboo/bamboo.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2005
+ * (C) Copyright 2005-2007
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -291,6 +291,7 @@ int checkboard(void)
        return (0);
 }
 
+#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
 /*************************************************************************
  *
  * init_spd_array -- Bamboo has one bank onboard sdram (plus DIMM)
@@ -345,10 +346,12 @@ static void init_spd_array(void)
        cfg_simulate_spd_eeprom[25]    = 0x00;    /* SDRAM Cycle Time (cas latency 1.5) = N.A */
        cfg_simulate_spd_eeprom[12]    = 0x82;    /* refresh Rate Type: Normal (15.625us) + Self refresh */
 }
+#endif
 
 long int initdram (int board_type)
 {
-       long dram_size = 0;
+#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
+       long dram_size;
 
        /*
         * First write simulated values in eeprom array for onboard bank 0
@@ -358,6 +361,9 @@ long int initdram (int board_type)
        dram_size = spd_sdram();
 
        return dram_size;
+#else
+       return CFG_MBYTES_SDRAM << 20;
+#endif
 }
 
 #if defined(CFG_DRAM_TEST)
@@ -881,11 +887,11 @@ void ext_bus_cntlr_init(void)
                /*------------------------------------------------------------------------- */
        case BOOT_FROM_NAND_FLASH0:
                /*------------------------------------------------------------------------- */
-               ebc0_cs0_bnap_value = 0;
-               ebc0_cs0_bncr_value = 0;
+               ebc0_cs0_bnap_value = EBC0_BNAP_NAND_FLASH;
+               ebc0_cs0_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
 
-               ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
-               ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
+               ebc0_cs1_bnap_value = 0;
+               ebc0_cs1_bncr_value = 0;
                ebc0_cs2_bnap_value = 0;
                ebc0_cs2_bncr_value = 0;
                ebc0_cs3_bnap_value = 0;
@@ -1409,10 +1415,10 @@ void update_ndfc_ios(void)
        gpio_tab[GPIO0][6].in_out = GPIO_OUT;       /* EBC_CS_N(1) */
        gpio_tab[GPIO0][6].alt_nb = GPIO_ALT1;
 
-#if 0
        gpio_tab[GPIO0][7].in_out = GPIO_OUT;       /* EBC_CS_N(2) */
        gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
 
+#if 0
        gpio_tab[GPIO0][7].in_out = GPIO_OUT;       /* EBC_CS_N(3) */
        gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
 #endif
@@ -1900,12 +1906,21 @@ void configure_ppc440ep_pins(void)
        {
                update_ndfc_ios();
 
+#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
                mtsdr(sdr_cust0, SDR0_CUST0_MUX_NDFC_SEL   |
                      SDR0_CUST0_NDFC_ENABLE    |
                      SDR0_CUST0_NDFC_BW_8_BIT  |
                      SDR0_CUST0_NDFC_ARE_MASK  |
                      SDR0_CUST0_CHIPSELGAT_EN1 |
                      SDR0_CUST0_CHIPSELGAT_EN2);
+#else
+               mtsdr(sdr_cust0, SDR0_CUST0_MUX_NDFC_SEL   |
+                     SDR0_CUST0_NDFC_ENABLE    |
+                     SDR0_CUST0_NDFC_BW_8_BIT  |
+                     SDR0_CUST0_NDFC_ARE_MASK  |
+                     SDR0_CUST0_CHIPSELGAT_EN0 |
+                     SDR0_CUST0_CHIPSELGAT_EN2);
+#endif
 
                ndfc_selection_in_fpga();
        }

diff --git a/board/amcc/bamboo/config.mk b/board/amcc/bamboo/config.mk
index 9d7f4c310510c620c6f57a059fc62343e72db1d3..b46527dcc5fb1c7f4300f621e6a2520a8518c12e 100644 (file)
--- a/board/amcc/bamboo/config.mk
+++ b/board/amcc/bamboo/config.mk
@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2002-2006
+# (C) Copyright 2002-2007
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
@@ -21,7 +21,11 @@
 # MA 02111-1307 USA
 #
 
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+
+ifndef TEXT_BASE
 TEXT_BASE = 0xFFFA0000
+endif
 
 PLATFORM_CPPFLAGS += -DCONFIG_440=1
 

diff --git a/board/amcc/bamboo/flash.c b/board/amcc/bamboo/flash.c
index a30ab7ada8f2a2e7ed9316ed73ea1aad89179213..8a2e832cf48a7858e20b4545f9b95ffd890af139 100644 (file)
--- a/board/amcc/bamboo/flash.c
+++ b/board/amcc/bamboo/flash.c
@@ -53,7 +53,7 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips        */
 static unsigned long flash_addr_table[][CFG_MAX_FLASH_BANKS] = {
        {0x87800001, 0xFFF00000, 0xFFF80000}, /* 0:boot from small flash */
        {0x00000000, 0x00000000, 0x00000000}, /* 1:boot from pci 66      */
-       {0x00000000, 0x00000000, 0x00000000}, /* 2:boot from nand flash  */
+       {0x87800001, 0x00000000, 0x00000000}, /* 0:boot from nand flash  */
        {0x87F00000, 0x87F80000, 0xFFC00001}, /* 3:boot from big flash 33*/
        {0x87F00000, 0x87F80000, 0xFFC00001}, /* 4:boot from big flash 66*/
        {0x00000000, 0x00000000, 0x00000000}, /* 5:boot from             */
@@ -134,10 +134,10 @@ unsigned long flash_init(void)
                flash_info[i].size = 0;
 
                /* check whether the address is 0 */
-               if (flash_addr_table[index][i] == 0) {
+               if (flash_addr_table[index][i] == 0)
                        continue;
-               }
 
+               DEBUGF("Detection bank %d...\n", i);
                /* call flash_get_size() to initialize sector address */
                size_b[i] = flash_get_size((vu_long *) flash_addr_table[index][i],
                                   &flash_info[i]);

diff --git a/board/amcc/bamboo/init.S b/board/amcc/bamboo/init.S
index 7820107aa5a1ff38d8db02ac2cf713d18311c77c..1459eec363845d67e8627128a2ae038cc73cebc9 100644 (file)
--- a/board/amcc/bamboo/init.S
+++ b/board/amcc/bamboo/init.S
@@ -1,74 +1,31 @@
 /*
-*
-* See file CREDITS for list of people who contributed to this
-* project.
-*
-* This program is free software; you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as
-* published by the Free Software Foundation; either version 2 of
-* the License, or (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License
-* along with this program; if not, write to the Free Software
-* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-* MA 02111-1307 USA
-*/
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ *  Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
 
 #include <ppc_asm.tmpl>
 #include <config.h>
-
-/* General */
-#define TLB_VALID   0x00000200
-
-/* Supported page sizes */
-
-#define SZ_1K      0x00000000
-#define SZ_4K      0x00000010
-#define SZ_16K     0x00000020
-#define SZ_64K     0x00000030
-#define SZ_256K            0x00000040
-#define SZ_1M      0x00000050
-#define SZ_8M       0x00000060
-#define SZ_16M     0x00000070
-#define SZ_256M            0x00000090
-
-/* Storage attributes */
-#define SA_W       0x00000800      /* Write-through */
-#define SA_I       0x00000400      /* Caching inhibited */
-#define SA_M       0x00000200      /* Memory coherence */
-#define SA_G       0x00000100      /* Guarded */
-#define SA_E       0x00000080      /* Endian */
-
-/* Access control */
-#define AC_X       0x00000024      /* Execute */
-#define AC_W       0x00000012      /* Write */
-#define AC_R       0x00000009      /* Read */
-
-/* Some handy macros */
-
-#define EPN(e)         ((e) & 0xfffffc00)
-#define TLB0(epn,sz)   ( (EPN((epn)) | (sz) | TLB_VALID ) )
-#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
-#define TLB2(a)                ( (a)&0x00000fbf )
-
-#define tlbtab_start\
-       mflr    r1  ;\
-       bl 0f       ;
-
-#define tlbtab_end\
-       .long 0, 0, 0   ;   \
-0:     mflr    r0      ;   \
-       mtlr    r1      ;   \
-       blr             ;
-
-#define tlbentry(epn,sz,rpn,erpn,attr)\
-       .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
-
+#include <asm-ppc/mmu.h>
 
 /**************************************************************************
  * TLB TABLE
@@ -80,34 +37,68 @@
  *  Pointer to the table is returned in r1
  *
  *************************************************************************/
-
-    .section .bootpg,"ax"
-    .globl tlbtab
+       .section .bootpg,"ax"
+       .globl tlbtab
 
 tlbtab:
-    tlbtab_start
-
-    /*
-     * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
-     * speed up boot process. It is patched after relocation to enable SA_I
-     */
-    tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/)
-
-    /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
-    tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
-
-    tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
-    tlbentry( CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I )
-    tlbentry( CFG_NVRAM_BASE_ADDR, SZ_256M, CFG_NVRAM_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I )
-    tlbentry( CFG_NAND_ADDR, SZ_256M, CFG_NAND_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I )
-
-    /* PCI */
-    tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I )
-    tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I )
-    tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I )
-    tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I )
-
-    /* USB 2.0 Device */
-    tlbentry( CFG_USB_DEVICE, SZ_1K, CFG_USB_DEVICE, 0, AC_R|AC_W|SA_G|SA_I )
-
-    tlbtab_end
+       tlbtab_start
+
+       /*
+        * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+        * speed up boot process. It is patched after relocation to enable SA_I
+        */
+#ifndef CONFIG_NAND_SPL
+       tlbentry(CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
+#else
+       tlbentry(CFG_NAND_BOOT_SPL_SRC, SZ_4K, CFG_NAND_BOOT_SPL_SRC, 0, AC_R|AC_W|AC_X|SA_G)
+#endif
+
+       /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+       tlbentry(CFG_INIT_RAM_ADDR, SZ_4K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
+
+       tlbentry(CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
+
+       /* PCI base & peripherals */
+       tlbentry(CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I)
+
+       tlbentry(CFG_NVRAM_BASE_ADDR, SZ_256M, CFG_NVRAM_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I)
+       tlbentry(CFG_NAND_ADDR, SZ_4K, CFG_NAND_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I)
+
+       /* PCI */
+       tlbentry(CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I)
+       tlbentry(CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I)
+       tlbentry(CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I)
+       tlbentry(CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I)
+
+       /* USB 2.0 Device */
+       tlbentry(CFG_USB_DEVICE, SZ_1K, CFG_USB_DEVICE, 0, AC_R|AC_W|SA_G|SA_I)
+
+       tlbtab_end
+
+#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+       /*
+        * For NAND booting the first TLB has to be reconfigured to full size
+        * and with caching disabled after running from RAM!
+        */
+#define TLB00  TLB0(CFG_BOOT_BASE_ADDR, SZ_256M)
+#define TLB01  TLB1(CFG_BOOT_BASE_ADDR, 0)
+#define TLB02  TLB2(AC_R|AC_W|AC_X|SA_G|SA_I)
+
+       .globl  reconfig_tlb0
+reconfig_tlb0:
+       sync
+       isync
+       addi    r4,r0,0x0000            /* TLB entry #0 */
+       lis     r5,TLB00@h
+       ori     r5,r5,TLB00@l
+       tlbwe   r5,r4,0x0000            /* Save it out */
+       lis     r5,TLB01@h
+       ori     r5,r5,TLB01@l
+       tlbwe   r5,r4,0x0001            /* Save it out */
+       lis     r5,TLB02@h
+       ori     r5,r5,TLB02@l
+       tlbwe   r5,r4,0x0002            /* Save it out */
+       sync
+       isync
+       blr
+#endif