imx-common: cache: configure L2 Cache for i.MX6SLL

If L2 cache configured as OCRAM, reset it.
Switch to use runtime check.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>

diff --git a/arch/arm/imx-common/cache.c b/arch/arm/imx-common/cache.c
index b77548821dbbbea8909e395b6c56967bc6c08b5f..1c4a9a28c892d1b603f554a85e9cc88c899736a6 100644 (file)
--- a/arch/arm/imx-common/cache.c
+++ b/arch/arm/imx-common/cache.c
@@ -8,6 +8,7 @@
 #include <asm/armv7.h>
 #include <asm/pl310.h>
 #include <asm/io.h>
+#include <asm/imx-common/sys_proto.h>
 
 #ifndef CONFIG_SYS_DCACHE_OFF
 void enable_caches(void)
@@ -39,6 +40,7 @@ void enable_caches(void)
 void v7_outer_cache_enable(void)
 {
        struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
+       struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
        unsigned int val;
 
 
@@ -55,15 +57,14 @@ void v7_outer_cache_enable(void)
         */
        setbits_le32(&pl310->pl310_aux_ctrl, L310_SHARED_ATT_OVERRIDE_ENABLE);
 
-#if defined CONFIG_MX6SL
-       struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
-       val = readl(&iomux->gpr[11]);
-       if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
-               /* L2 cache configured as OCRAM, reset it */
-               val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
-               writel(val, &iomux->gpr[11]);
+       if (is_mx6sl() || is_mx6sll()) {
+               val = readl(&iomux->gpr[11]);
+               if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
+                       /* L2 cache configured as OCRAM, reset it */
+                       val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
+                       writel(val, &iomux->gpr[11]);
+               }
        }
-#endif
 
        writel(0x132, &pl310->pl310_tag_latency_ctrl);
        writel(0x132, &pl310->pl310_data_latency_ctrl);