]> git.sur5r.net Git - u-boot/commitdiff
am335x evm: Enable support for spi0
authorTom Rini <trini@ti.com>
Wed, 8 Aug 2012 21:35:55 +0000 (14:35 -0700)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>
Sat, 1 Sep 2012 12:58:19 +0000 (14:58 +0200)
Signed-off-by: Tom Rini <trini@ti.com>
board/ti/am335x/mux.c
drivers/spi/omap3_spi.c
include/configs/am335x_evm.h

index 992f9ba78e263d155584fe7e406098a99b06d19d..80becd5c7a187eb788d65493bdc428a6bc701858 100644 (file)
@@ -310,6 +310,16 @@ static struct module_pin_mux i2c1_pin_mux[] = {
        {-1},
 };
 
+static struct module_pin_mux spi0_pin_mux[] = {
+       {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)},   /* SPI0_SCLK */
+       {OFFSET(spi0_d0), (MODE(0) | RXACTIVE |
+                       PULLUDEN | PULLUP_EN)},                 /* SPI0_D0 */
+       {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)},     /* SPI0_D1 */
+       {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE |
+                       PULLUDEN | PULLUP_EN)},                 /* SPI0_CS0 */
+       {-1},
+};
+
 static struct module_pin_mux gpio0_7_pin_mux[] = {
        {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN)},      /* GPIO0_7 */
        {-1},
@@ -430,6 +440,7 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header)
                        configure_module_pin_mux(i2c1_pin_mux);
                else if (profile == PROFILE_2) {
                        configure_module_pin_mux(mmc1_pin_mux);
+                       configure_module_pin_mux(spi0_pin_mux);
                }
        } else if (!strncmp(header->name, "A335X_SK", HDR_NAME_LEN)) {
                /* Starter Kit EVM */
index 47f9e56f421e27fdc933951db8ebf29ac3699fcb..e40a632caa040eba54ee0f2f6549c1da537152af 100644 (file)
@@ -173,8 +173,18 @@ int spi_claim_bus(struct spi_slave *slave)
        /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
         * REVISIT: this controller could support SPI_3WIRE mode.
         */
+#ifdef CONFIG_AM33XX
+       /*
+        * The reference design on AM33xx has D0 and D1 wired up opposite
+        * of how it has been done on previous platforms.  We assume that
+        * custom hardware will also follow this convention.
+        */
+       conf &= OMAP3_MCSPI_CHCONF_DPE0;
+       conf |= ~(OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1);
+#else
        conf &= ~(OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1);
        conf |= OMAP3_MCSPI_CHCONF_DPE0;
+#endif
 
        /* wordlength */
        conf &= ~OMAP3_MCSPI_CHCONF_WL_MASK;
index c827ebfce7c8f07bc9a06a0162a98a03f0f23e5f..2bfe8c6dcdfa0de7c3bb716ec25f12c1fdeea74e 100644 (file)
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_EXT2
 
+#define CONFIG_SPI
+#define CONFIG_OMAP3_SPI
+#define CONFIG_MTD_DEVICE
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED                (24000000)
+
  /* Physical Memory Map */
 #define CONFIG_NR_DRAM_BANKS           1               /*  1 bank of DRAM */
 #define PHYS_DRAM_1                    0x80000000      /* DRAM Bank #1 */
 #define CONFIG_I2C_MULTI_BUS
 #define CONFIG_DRIVER_OMAP24XX_I2C
 #define CONFIG_CMD_EEPROM
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
 #define CONFIG_SYS_I2C_EEPROM_ADDR     0x50    /* Main EEPROM */
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
 #define CONFIG_SYS_I2C_MULTI_EEPROMS