Changes since U-Boot 1.1.1:
======================================================================
+* Patch by Dave Peverley, 30 Apr 2004:
+ Add support for OMAP730 Perseus2 Development board
+
+* Patch by Alan J. Luse, 29 Apr 2004:
+ Fix flash chip-select (OR0) option register setting on FADS boards.
+
+* Patch by Alan J. Luse, 29 Apr 2004:
+ Report MII network speed and duplex setting properly when
+ auto-negotiate is not enabled.
+
+* Patch by Jarrett Redd, 29 Apr 2004:
+ Fix hang on reset on Ocotea board due to flash in wrong mode.
+
* Patch by Dave Peverley, 29 Apr 2004:
add MAC address detection to smc91111 driver
D: Support for PIP405 board
D: Support for MIP405 board
+N: Dave Peverley
+E: dpeverley@mpc-data.co.uk
+W: http://www.mpc-data.co.uk
+D: OMAP730 P2 board support
+
N: Bill Pitts
E: wlp@mindspring.com
D: BedBug embedded debugger code
omap1510inn ARM925T
omap1610inn ARM926EJS
+Dave Peverley <dpeverley@mpc-data.co.uk>
+ omap730p2 ARM926EJS
+
Nishant Kamat <nskamat@ti.com>
omap1610h2 ARM926EJS
LIST_ARM9=" \
at91rm9200dk integratorcp integratorap \
omap1510inn omap1610h2 omap1610inn \
- smdk2400 smdk2410 trab \
- VCMA9 versatile \
+ omap730p2 smdk2400 smdk2410 \
+ trab VCMA9 versatile \
"
#########################################################################
xtract_omap1610xxx = $(subst _cs0boot,,$(subst _cs3boot,, $(subst _config,,$1)))
+xtract_omap730p2 = $(subst _cs0boot,,$(subst _cs3boot,, $(subst _config,,$1)))
+
SX1_config : unconfig
@./mkconfig $(@:_config=) arm arm925t sx1
fi;
@./mkconfig -a $(call xtract_omap1610xxx,$@) arm arm926ejs omap1610inn
+omap730p2_config \
+omap730p2_cs0boot_config \
+omap730p2_cs3boot_config : unconfig
+ @if [ "$(findstring _cs0boot_, $@)" ] ; then \
+ echo "#define CONFIG_CS0_BOOT" >> ./include/config.h ; \
+ echo "... configured for CS0 boot"; \
+ else \
+ echo "#define CONFIG_CS3_BOOT" >> ./include/config.h ; \
+ echo "... configured for CS3 boot"; \
+ fi;
+ @./mkconfig -a $(call xtract_omap730p2,$@) arm arm926ejs omap730p2
+
smdk2400_config : unconfig
@./mkconfig $(@:_config=) arm arm920t smdk2400
CONFIG_AT91RM9200DK, CONFIG_DNP1110, CONFIG_EP7312,
CONFIG_H2_OMAP1610, CONFIG_HHP_CRADLE, CONFIG_IMPA7,
CONFIG_INNOVATOROMAP1510, CONFIG_INNOVATOROMAP1610, CONFIG_LART,
- CONFIG_LUBBOCK, CONFIG_SHANNON, CONFIG_SMDK2400,
- CONFIG_SMDK2410, CONFIG_TRAB, CONFIG_VCMA9,
+ CONFIG_LUBBOCK, CONFIG_SHANNON, CONFIG_P2_OMAP730,
+ CONFIG_SMDK2400, CONFIG_SMDK2410, CONFIG_TRAB,
+ CONFIG_VCMA9
MicroBlaze based boards:
------------------------
FADS823_config NETVIA_config TQM860L_config
FADS850SAR_config omap1510inn_config WALNUT405_config
FADS860T_config omap1610h2_config ZPC1900_config
+ omap730p2_config
Note: for some board special configuration names may exist; check if
additional information is available from the board vendor; for
/* Remap FLASH according to real size */
memctl->memc_or0 =
- ((((unsigned long) ~1) << i) & OR_AM_MSK) |
+ ((((unsigned long) ~0) << i) & OR_AM_MSK) |
CFG_OR_TIMING_FLASH;
memctl->memc_br0 = CFG_BR0_PRELIM;
info->protect[i] = addr2[2] & 1;
}
+ /* issue bank reset to return to read mode */
+ addr2[0] = (FLASH_WORD_SIZE) 0x00F000F0;
+
/*
* Prevent writes to uninitialized FLASH.
*/
if (info->flash_id != FLASH_UNKNOWN) {
+ /* ? ? ? */
}
return (info->size);
--- /dev/null
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS := omap730p2.o flash.o
+SOBJS := platform.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $^
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+#
+# (C) Copyright 2003
+# Texas Instruments, <www.ti.com>
+# Kshitij Gupta <Kshitij@ti.com>
+#
+# TI Perseus 2 board with OMAP720 (ARM925EJS) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# Innovator has 1 bank of 256 MB SDRAM
+# Physical Address:
+# 1000'0000 to 2000'0000
+#
+#
+# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000
+# (mem base + reserved)
+#
+# we load ourself to 1108'0000
+#
+#
+
+TEXT_BASE = 0x11080000
--- /dev/null
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/* Board support for 1 or 2 flash devices */
+#undef FLASH_PORT_WIDTH32
+#define FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH ushort
+#define FLASH_PORT_WIDTHV vu_short
+#define SWAP(x) __swab16(x)
+#else
+#define FLASH_PORT_WIDTH ulong
+#define FLASH_PORT_WIDTHV vu_long
+#define SWAP(x) __swab32(x)
+#endif
+
+#define FPW FLASH_PORT_WIDTH
+#define FPWV FLASH_PORT_WIDTHV
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+
+/* Flash Organization Structure */
+typedef struct OrgDef {
+ unsigned int sector_number;
+ unsigned int sector_size;
+} OrgDef;
+
+
+/* Flash Organizations */
+OrgDef OrgIntel_28F256L18T[] = {
+ {4, 32 * 1024}, /* 4 * 32kBytes sectors */
+ {255, 128 * 1024}, /* 255 * 128kBytes sectors */
+};
+
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+unsigned long flash_init (void);
+static ulong flash_get_size (FPW * addr, flash_info_t * info);
+static int write_data (flash_info_t * info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+void inline spin_wheel (void);
+void flash_print_info (flash_info_t * info);
+void flash_unprotect_sectors (FPWV * addr);
+int flash_erase (flash_info_t * info, int s_first, int s_last);
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+ int i;
+ ulong size = 0;
+ for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+ switch (i) {
+ case 0:
+ flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
+ flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+ break;
+ default:
+ panic ("configured too many flash banks!\n");
+ break;
+ }
+ size += flash_info[i].size;
+ }
+
+ /* Protect monitor and environment sectors
+ */
+ flash_protect (FLAG_PROTECT_SET,
+ CFG_FLASH_BASE,
+ CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]);
+
+ flash_protect (FLAG_PROTECT_SET,
+ CFG_ENV_ADDR,
+ CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+
+ return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+ int i;
+ OrgDef *pOrgDef;
+
+ pOrgDef = OrgIntel_28F256L18T;
+ if (info->flash_id == FLASH_UNKNOWN) {
+ return;
+ }
+
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+ for (i = 0; i < info->sector_count; i++) {
+ if (i > 255) {
+ info->start[i] = base + (i * 0x8000);
+ info->protect[i] = 0;
+ } else {
+ info->start[i] = base +
+ (i * PHYS_FLASH_SECT_SIZE);
+ info->protect[i] = 0;
+ }
+ }
+ }
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_INTEL:
+ printf ("INTEL ");
+ break;
+ default:
+ printf ("Unknown Vendor ");
+ break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_28F256L18T:
+ printf ("FLASH 28F256L18T\n");
+ break;
+ default:
+ printf ("Unknown Chip Type\n");
+ break;
+ }
+
+ printf (" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+
+ printf (" Sector Start Addresses:");
+ for (i = 0; i < info->sector_count; ++i) {
+ if ((i % 5) == 0)
+ printf ("\n ");
+ printf (" %08lX%s",
+ info->start[i], info->protect[i] ? " (RO)" : " ");
+ }
+ printf ("\n");
+ return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (FPW * addr, flash_info_t * info)
+{
+ volatile FPW value;
+
+ /* Write auto select command: read Manufacturer ID */
+ addr[0x5555] = (FPW) 0x00AA00AA;
+ addr[0x2AAA] = (FPW) 0x00550055;
+ addr[0x5555] = (FPW) 0x00900090;
+
+ mb ();
+ value = addr[0];
+
+ switch (value) {
+
+ case (FPW) INTEL_MANUFACT:
+ info->flash_id = FLASH_MAN_INTEL;
+ break;
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
+ return (0); /* no or unknown flash */
+ }
+
+ mb ();
+ value = addr[1]; /* device ID */
+ switch (value) {
+
+ case (FPW) (INTEL_ID_28F256L18T):
+ info->flash_id += FLASH_28F256L18T;
+ info->sector_count = 259;
+ info->size = 0x02000000;
+ break; /* => 32 MB */
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ break;
+ }
+
+ if (info->sector_count > CFG_MAX_FLASH_SECT) {
+ printf ("** ERROR: sector count %d > max (%d) **\n",
+ info->sector_count, CFG_MAX_FLASH_SECT);
+ info->sector_count = CFG_MAX_FLASH_SECT;
+ }
+
+ addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
+
+ return (info->size);
+}
+
+
+/* unprotects a sector for write and erase
+ * on some intel parts, this unprotects the entire chip, but it
+ * wont hurt to call this additional times per sector...
+ */
+void flash_unprotect_sectors (FPWV * addr)
+{
+#define PD_FINTEL_WSMS_READY_MASK 0x0080
+
+ *addr = (FPW) 0x00500050; /* clear status register */
+
+ /* this sends the clear lock bit command */
+ *addr = (FPW) 0x00600060;
+ *addr = (FPW) 0x00D000D0;
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+ int flag, prot, sect;
+ ulong type, start, last;
+ int rcode = 0;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("- missing\n");
+ } else {
+ printf ("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ type = (info->flash_id & FLASH_VENDMASK);
+ if ((type != FLASH_MAN_INTEL)) {
+ printf ("Can't erase unknown flash type %08lx - aborted\n",
+ info->flash_id);
+ return 1;
+ }
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf ("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf ("\n");
+ }
+
+
+ start = get_timer (0);
+ last = start;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts ();
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect <= s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ FPWV *addr = (FPWV *) (info->start[sect]);
+ FPW status;
+
+ printf ("Erasing sector %2d ... ", sect);
+
+ flash_unprotect_sectors (addr);
+
+ /* arm simple, non interrupt dependent timer */
+ reset_timer_masked ();
+
+ *addr = (FPW) 0x00500050;/* clear status register */
+ *addr = (FPW) 0x00200020;/* erase setup */
+ *addr = (FPW) 0x00D000D0;/* erase confirm */
+
+ while (((status =
+ *addr) & (FPW) 0x00800080) !=
+ (FPW) 0x00800080) {
+ if (get_timer_masked () >
+ CFG_FLASH_ERASE_TOUT) {
+ printf ("Timeout\n");
+ /* suspend erase */
+ *addr = (FPW) 0x00B000B0;
+ /* reset to read mode */
+ *addr = (FPW) 0x00FF00FF;
+ rcode = 1;
+ break;
+ }
+ }
+
+ /* clear status register cmd. */
+ *addr = (FPW) 0x00500050;
+ *addr = (FPW) 0x00FF00FF;/* resest to read mode */
+ printf (" done\n");
+ }
+ }
+ return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+ ulong cp, wp;
+ FPW data;
+ int count, i, l, rc, port_width;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ return 4;
+ }
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+ wp = (addr & ~1);
+ port_width = 2;
+#else
+ wp = (addr & ~3);
+ port_width = 4;
+#endif
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i = 0, cp = wp; i < l; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+ for (; i < port_width && cnt > 0; ++i) {
+ data = (data << 8) | *src++;
+ --cnt;
+ ++cp;
+ }
+ for (; cnt == 0 && i < port_width; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+
+ if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+ return (rc);
+ }
+ wp += port_width;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ count = 0;
+ while (cnt >= port_width) {
+ data = 0;
+ for (i = 0; i < port_width; ++i) {
+ data = (data << 8) | *src++;
+ }
+ if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+ return (rc);
+ }
+ wp += port_width;
+ cnt -= port_width;
+ if (count++ > 0x800) {
+ spin_wheel ();
+ count = 0;
+ }
+ }
+
+ if (cnt == 0) {
+ return (0);
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+ data = (data << 8) | *src++;
+ --cnt;
+ }
+ for (; i < port_width; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+
+ return (write_data (info, wp, SWAP (data)));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t * info, ulong dest, FPW data)
+{
+ FPWV *addr = (FPWV *) dest;
+ ulong status;
+ int flag;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*addr & data) != data) {
+ printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
+ return (2);
+ }
+ flash_unprotect_sectors (addr);
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts ();
+ *addr = (FPW) 0x00400040; /* write setup */
+ *addr = data;
+
+ /* arm simple, non interrupt dependent timer */
+ reset_timer_masked ();
+
+ /* wait while polling the status register */
+ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+ if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+ *addr = (FPW) 0x00FF00FF; /* restore read mode */
+ return (1);
+ }
+ }
+ *addr = (FPW) 0x00FF00FF; /* restore read mode */
+ return (0);
+}
+
+void inline spin_wheel (void)
+{
+ static int p = 0;
+ static char w[] = "\\/-";
+
+ printf ("\010%c", w[p]);
+ (++p == 3) ? (p = 0) : 0;
+}
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#if defined(CONFIG_OMAP730)
+#include <./configs/omap730.h>
+#endif
+
+int test_boot_mode(void);
+void spin_up_leds(void);
+void flash__init (void);
+void ether__init (void);
+void set_muxconf_regs (void);
+void peripheral_power_enable (void);
+
+#define FLASH_ON_CS0 1
+#define FLASH_ON_CS3 0
+
+static inline void delay (unsigned long loops)
+{
+ __asm__ volatile ("1:\n"
+ "subs %0, %1, #1\n"
+ "bne 1b":"=r" (loops):"0" (loops));
+}
+
+int test_boot_mode(void)
+{
+ /* Check for CS0 and CS3 address decode swapping */
+ if (*((volatile int *)EMIFS_CONFIG) & 0x00000002)
+ return(FLASH_ON_CS3);
+ else
+ return(FLASH_ON_CS0);
+}
+
+/* Toggle backup LED indication */
+void toggle_backup_led(void)
+{
+ static int backupLEDState = 0; /* Init variable so that the LED will be ON the first time */
+ volatile unsigned int *IOConfReg;
+
+
+ IOConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_5 + GPIO_DATA_OUTPUT);
+
+ if (backupLEDState != 0) {
+ *IOConfReg &= (0xFFFFEFFF);
+ backupLEDState = 0;
+ } else {
+ *IOConfReg |= (0x00001000);
+ backupLEDState = 1;
+ }
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+ volatile unsigned int *IOConfReg;
+
+
+ DECLARE_GLOBAL_DATA_PTR;
+
+ /* arch number of OMAP 730 P2 Board - Same as the Innovator! */
+ gd->bd->bi_arch_number = 491;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = 0x10000100;
+
+ /* Configure MUX settings */
+ set_muxconf_regs ();
+
+ peripheral_power_enable ();
+
+
+ /* Backup LED indication via GPIO_140 -> Red led if MUX correctly setup */
+ toggle_backup_led();
+
+ /* Hold GSM in reset until needed */
+ *((volatile unsigned short *)M_CTL) &= ~1;
+
+
+ /*
+ * CSx timings, GPIO Mux ... setup
+ */
+
+ /* Flash: CS0 timings setup */
+ *((volatile unsigned int *) FLASH_CFG_0) = 0x0000fff3;
+ *((volatile unsigned int *) FLASH_ACFG_0_1) = 0x00000088;
+
+ /* Ethernet support trough the debug board */
+ /* CS1 timings setup */
+ *((volatile unsigned int *) FLASH_CFG_1) = 0x0000fff3;
+ *((volatile unsigned int *) FLASH_ACFG_0_1) = 0x00000000;
+
+ /* this speeds up your boot a quite a bit. However to make it
+ * work, you need make sure your kernel startup flush bug is fixed.
+ * ... rkw ...
+ */
+ icache_enable ();
+
+ flash__init ();
+ ether__init ();
+
+ return 0;
+}
+
+int misc_init_r (void)
+{
+ /* currently empty */
+ return (0);
+}
+
+/******************************
+ Routine:
+ Description:
+******************************/
+void flash__init (void)
+{
+ unsigned int regval;
+
+ regval = *((volatile unsigned int *) EMIFS_CONFIG);
+ /* Turn off write protection for flash devices. */
+ regval = regval | 0x0001;
+ *((volatile unsigned int *) EMIFS_CONFIG) = regval;
+}
+
+/*************************************************************
+ Routine:ether__init
+ Description: take the Ethernet controller out of reset and wait
+ for the EEPROM load to complete.
+*************************************************************/
+void ether__init (void)
+{
+#define LAN_RESET_REGISTER 0x0400001c
+
+ *((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000;
+ do {
+ *((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0001;
+ udelay (100);
+ } while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0001);
+
+ do {
+ *((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000;
+ udelay (100);
+ } while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0000);
+
+#define ETH_CONTROL_REG 0x0400030b
+
+ *((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
+ udelay (100);
+}
+
+/******************************
+ Routine:
+ Description:
+******************************/
+int dram_init (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+ return 0;
+}
+
+/******************************************************
+ Routine: set_muxconf_regs
+ Description: Setting up the configuration Mux registers
+ specific to the hardware
+*******************************************************/
+void set_muxconf_regs (void)
+{
+ volatile unsigned int *MuxConfReg;
+ /* set each registers to its reset value; */
+
+ /*
+ * Backup LED Indication
+ */
+
+ /* Configure MUXed pin. Mode 6: GPIO_140 */
+ MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF10);
+ *MuxConfReg &= (0xFFFFFF1F); /* Clear D_MPU_LPG1 */
+ *MuxConfReg |= 0x000000C0; /* Set D_MPU_LPG1 to 0x6 */
+
+ /* Configure GPIO_140 as output */
+ MuxConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_5 + GPIO_DIRECTION_CONTROL);
+ *MuxConfReg &= (0xFFFFEFFF); /* Clear direction (output) for GPIO 140 */
+
+ /*
+ * Configure GPIOs for battery charge & feedback
+ */
+
+ /* Configure MUXed pin. Mode 6: GPIO_35 */
+ MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF3);
+ *MuxConfReg &= 0xFFFFFFF1; /* Clear M_CLK_OUT */
+ *MuxConfReg |= 0x0000000C; /* Set M_CLK_OUT = 0x6 (GPIOs) */
+
+ /* Configure MUXed pin. Mode 6: GPIO_72,73,74 */
+ MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF5);
+ *MuxConfReg &= 0xFFFF1FFF; /* Clear D_DDR */
+ *MuxConfReg |= 0x0000C000; /* Set D_DDR = 0x6 (GPIOs) */
+
+ MuxConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_3 + GPIO_DIRECTION_CONTROL);
+ *MuxConfReg |= 0x00000100; /* Configure GPIO_72 as input */
+ *MuxConfReg &= 0xFFFFFDFF; /* Configure GPIO_73 as output */
+
+ /*
+ * Allow battery charge
+ */
+
+ MuxConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_3 + GPIO_DATA_OUTPUT);
+ *MuxConfReg &= (0xFFFFFDFF); /* Clear GPIO_73 pin */
+
+ /*
+ * Configure MPU_EXT_NIRQ IO in IO_CONF9 register,
+ * It is used as the Ethernet controller interrupt
+ */
+ MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF9);
+ *MuxConfReg &= 0x1FFFFFFF;
+}
+
+/******************************************************
+ Routine: peripheral_power_enable
+ Description: Enable the power for UART1
+*******************************************************/
+void peripheral_power_enable (void)
+{
+ volatile unsigned int *MuxConfReg;
+
+
+ /* Set up pins used by UART */
+
+ /* Start UART clock (48MHz) */
+ MuxConfReg = (volatile unsigned int *) (PERSEUS_PCC_CONF_REG);
+ *MuxConfReg &= (0xFFFFFFF7);
+ *MuxConfReg |= (0x00000008);
+
+ /* Get the UART pin in mode0 */
+ MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF3);
+ *MuxConfReg &= (0xFF1FFFFF);
+ *MuxConfReg &= (0xF1FFFFFF);
+}
--- /dev/null
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2003-2004
+ *
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
+ *
+ * Modified for OMAP730 P2 Board by Dave Peverley, MPC-Data Limited
+ * (http://www.mpc-data.co.uk)
+ *
+ * TODO : Tidy up and change to use system register defines
+ * from omap730.h where possible.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+#if defined(CONFIG_OMAP730)
+#include <./configs/omap730.h>
+#endif
+
+_TEXT_BASE:
+ .word TEXT_BASE /* sdram load addr from config.mk */
+
+.globl platformsetup
+platformsetup:
+ /* Save callers address in r11 - r11 must never be modified */
+ mov r11, lr
+
+ /*------------------------------------------------------*
+ *mask all IRQs by setting all bits in the INTMR default*
+ *------------------------------------------------------*/
+ mov r1, #0xffffffff
+ ldr r0, =REG_IHL1_MIR
+ str r1, [r0]
+ ldr r0, =REG_IHL2_MIR
+ str r1, [r0]
+
+ /*------------------------------------------------------*
+ * Set up ARM CLM registers (IDLECT1) *
+ *------------------------------------------------------*/
+ ldr r0, REG_ARM_IDLECT1
+ ldr r1, VAL_ARM_IDLECT1
+ str r1, [r0]
+
+ /*------------------------------------------------------*
+ * Set up ARM CLM registers (IDLECT2) *
+ *------------------------------------------------------*/
+ ldr r0, REG_ARM_IDLECT2
+ ldr r1, VAL_ARM_IDLECT2
+ str r1, [r0]
+
+ /*------------------------------------------------------*
+ * Set up ARM CLM registers (IDLECT3) *
+ *------------------------------------------------------*/
+ ldr r0, REG_ARM_IDLECT3
+ ldr r1, VAL_ARM_IDLECT3
+ str r1, [r0]
+
+
+ mov r1, #0x01 /* PER_EN bit */
+ ldr r0, REG_ARM_RSTCT2
+ strh r1, [r0] /* CLKM; Peripheral reset. */
+
+ /* Set CLKM to Sync-Scalable */
+ /* I supposedly need to enable the dsp clock before switching */
+ mov r1, #0x1000
+ ldr r0, REG_ARM_SYSST
+ strh r1, [r0]
+ mov r0, #0x400
+1:
+ subs r0, r0, #0x1 /* wait for any bubbles to finish */
+ bne 1b
+ ldr r1, VAL_ARM_CKCTL
+ ldr r0, REG_ARM_CKCTL
+ strh r1, [r0]
+
+ /* a few nops to let settle */
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+
+ /* setup DPLL 1 */
+ /* Ramp up the clock to 96Mhz */
+ ldr r1, VAL_DPLL1_CTL
+ ldr r0, REG_DPLL1_CTL
+ strh r1, [r0]
+ ands r1, r1, #0x10 /* Check if PLL is enabled. */
+ beq lock_end /* Do not look for lock if BYPASS selected */
+2:
+ ldrh r1, [r0]
+ ands r1, r1, #0x01 /* Check the LOCK bit.*/
+ beq 2b /* loop until bit goes hi. */
+lock_end:
+
+ /*------------------------------------------------------*
+ * Turn off the watchdog during init... *
+ *------------------------------------------------------*/
+ ldr r0, REG_WATCHDOG
+ ldr r1, WATCHDOG_VAL1
+ str r1, [r0]
+ ldr r1, WATCHDOG_VAL2
+ str r1, [r0]
+ ldr r0, REG_WSPRDOG
+ ldr r1, WSPRDOG_VAL1
+ str r1, [r0]
+ ldr r0, REG_WWPSDOG
+
+watch1Wait:
+ ldr r1, [r0]
+ tst r1, #0x10
+ bne watch1Wait
+
+ ldr r0, REG_WSPRDOG
+ ldr r1, WSPRDOG_VAL2
+ str r1, [r0]
+ ldr r0, REG_WWPSDOG
+watch2Wait:
+ ldr r1, [r0]
+ tst r1, #0x10
+ bne watch2Wait
+
+ /* Set memory timings corresponding to the new clock speed */
+
+ /* Check execution location to determine current execution location
+ * and branch to appropriate initialization code.
+ */
+ /* Compare physical SDRAM base & current execution location. */
+ and r0, pc, #0xF0000000
+ /* Compare. */
+ cmp r0, #0
+ /* Skip over EMIF-fast initialization if running from SDRAM. */
+ bne skip_sdram
+
+ /*
+ * Delay for SDRAM initialization.
+ */
+ mov r3, #0x1800 /* value should be checked */
+3:
+ subs r3, r3, #0x1 /* Decrement count */
+ bne 3b
+
+ ldr r0, REG_SDRAM_CONFIG
+ ldr r1, SDRAM_CONFIG_VAL
+ str r1, [r0]
+
+ ldr r0, REG_SDRAM_MRS_LEGACY
+ ldr r1, SDRAM_MRS_VAL
+ str r1, [r0]
+
+skip_sdram:
+
+common_tc:
+ /* slow interface */
+ ldr r1, VAL_TC_EMIFS_CS0_CONFIG
+ ldr r0, REG_TC_EMIFS_CS0_CONFIG
+ str r1, [r0] /* Chip Select 0 */
+
+ ldr r1, VAL_TC_EMIFS_CS1_CONFIG
+ ldr r0, REG_TC_EMIFS_CS1_CONFIG
+ str r1, [r0] /* Chip Select 1 */
+ ldr r1, VAL_TC_EMIFS_CS2_CONFIG
+ ldr r0, REG_TC_EMIFS_CS2_CONFIG
+ str r1, [r0] /* Chip Select 2 */
+ ldr r1, VAL_TC_EMIFS_CS3_CONFIG
+ ldr r0, REG_TC_EMIFS_CS3_CONFIG
+ str r1, [r0] /* Chip Select 3 */
+
+ /* 48MHz clock request for UART1 */
+ ldr r1, PERSEUS2_CONFIG_BASE
+ ldrh r0, [r1, #CONFIG_PCC_CONF]
+ orr r0, r0, #CONF_MOD_UART1_CLK_MODE_R
+ strh r0, [r1, #CONFIG_PCC_CONF]
+
+ /* Initialize public and private rheas
+ * - set access factor 2 on both rhea / strobe
+ * - disable write buffer on strb0, enable write buffer on strb1
+ */
+
+ ldr R0, REG_RHEA_PUB_CTL
+ ldr R1, REG_RHEA_PRIV_CTL
+ ldr R2, VAL_RHEA_CTL
+ strh R2, [R0]
+ strh R2, [R1]
+ mov R3, #2 /* disable write buffer on strb0, enable write buffer on strb1 */
+ strh R3, [R0, #0x08] /* arm rhea control reg */
+ strh R3, [R1, #0x08]
+
+ /* enable IRQ and FIQ */
+
+ mrs r4, CPSR
+ bic r4, r4, #IRQ_MASK
+ bic r4, r4, #FIQ_MASK
+ msr CPSR, r4
+
+ /* set TAP CONF to TRI EMULATION */
+
+ ldr r1, [r0, #CONFIG_MODE2]
+ bic r1, r1, #0x18
+ orr r1, r1, #0x10
+ str r1, [r0, #CONFIG_MODE2]
+
+ /* set tdbgen to 1 */
+
+ ldr r0, PERSEUS2_CONFIG_BASE
+ ldr r1, [r0, #CONFIG_MODE1]
+ mov r2, #0x10000
+ orr r1, r1, r2
+ str r1, [r0, #CONFIG_MODE1]
+
+#ifdef CONFIG_P2_OMAP1610
+ /* inserting additional 2 clock cycle hold time for LAN */
+ ldr r0, REG_TC_EMIFS_CS1_ADVANCED
+ ldr r1, VAL_TC_EMIFS_CS1_ADVANCED
+ str r1, [r0]
+#endif
+ /* Start MPU Timer 1 */
+ ldr r0, REG_MPU_LOAD_TIMER
+ ldr r1, VAL_MPU_LOAD_TIMER
+ str r1, [r0]
+
+ ldr r0, REG_MPU_CNTL_TIMER
+ ldr r1, VAL_MPU_CNTL_TIMER
+ str r1, [r0]
+
+ /* back to arch calling code */
+ mov pc, r11
+
+ /* the literal pools origin */
+ .ltorg
+
+REG_TC_EMIFS_CONFIG: /* 32 bits */
+ .word 0xfffecc0c
+REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */
+ .word 0xfffecc10
+REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */
+ .word 0xfffecc14
+REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */
+ .word 0xfffecc18
+REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */
+ .word 0xfffecc1c
+
+#ifdef CONFIG_P2_OMAP730
+REG_TC_EMIFS_CS1_ADVANCED: /* 32 bits */
+ .word 0xfffecc54
+#endif
+
+/* MPU clock/reset/power mode control registers */
+REG_ARM_CKCTL: /* 16 bits */
+ .word 0xfffece00
+
+REG_ARM_IDLECT3: /* 16 bits */
+ .word 0xfffece24
+REG_ARM_IDLECT2: /* 16 bits */
+ .word 0xfffece08
+REG_ARM_IDLECT1: /* 16 bits */
+ .word 0xfffece04
+
+REG_ARM_RSTCT2: /* 16 bits */
+ .word 0xfffece14
+REG_ARM_SYSST: /* 16 bits */
+ .word 0xfffece18
+/* DPLL control registers */
+REG_DPLL1_CTL: /* 16 bits */
+ .word 0xfffecf00
+
+/* Watch Dog register */
+/* secure watchdog stop */
+REG_WSPRDOG:
+ .word 0xfffeb048
+/* watchdog write pending */
+REG_WWPSDOG:
+ .word 0xfffeb034
+
+WSPRDOG_VAL1:
+ .word 0x0000aaaa
+WSPRDOG_VAL2:
+ .word 0x00005555
+
+/* SDRAM config is: auto refresh enabled, 16 bit 4 bank,
+ counter @8192 rows, 10 ns, 8 burst */
+REG_SDRAM_CONFIG:
+ .word 0xfffecc20
+
+REG_SDRAM_MRS_LEGACY:
+ .word 0xfffecc24
+
+REG_WATCHDOG:
+ .word 0xfffec808
+
+REG_MPU_LOAD_TIMER:
+ .word 0xfffec600
+REG_MPU_CNTL_TIMER:
+ .word 0xfffec500
+
+/* Public and private rhea bridge registers definition */
+
+REG_RHEA_PUB_CTL:
+ .word 0xFFFECA00
+
+REG_RHEA_PRIV_CTL:
+ .word 0xFFFED300
+
+/* EMIFF SDRAM Configuration register
+ - self refresh disable
+ - auto refresh enabled
+ - SDRAM type 64 Mb, 16 bits bus 4 banks
+ - power down enabled
+ - SDRAM clock disabled
+ */
+SDRAM_CONFIG_VAL:
+ .word 0x0C017DF4
+
+/* Burst full page length ; cas latency = 3 */
+SDRAM_MRS_VAL:
+ .word 0x00000037
+
+VAL_ARM_CKCTL:
+ .word 0x6505
+VAL_DPLL1_CTL:
+ .word 0x3412
+
+#ifdef CONFIG_P2_OMAP730
+VAL_TC_EMIFS_CS0_CONFIG:
+ .word 0x0000FFF3
+VAL_TC_EMIFS_CS1_CONFIG:
+ .word 0x00004278
+VAL_TC_EMIFS_CS2_CONFIG:
+ .word 0x00004278
+VAL_TC_EMIFS_CS3_CONFIG:
+ .word 0x00004278
+VAL_TC_EMIFS_CS1_ADVANCED:
+ .word 0x00000022
+#endif
+
+VAL_ARM_IDLECT1:
+ .word 0x00000400
+VAL_ARM_IDLECT2:
+ .word 0x00000886
+VAL_ARM_IDLECT3:
+ .word 0x00000015
+
+WATCHDOG_VAL1:
+ .word 0x000000f5
+WATCHDOG_VAL2:
+ .word 0x000000a0
+
+VAL_MPU_LOAD_TIMER:
+ .word 0xffffffff
+VAL_MPU_CNTL_TIMER:
+ .word 0xffffffa1
+
+VAL_RHEA_CTL:
+ .word 0xFF22
+
+/* Config Register vals */
+PERSEUS2_CONFIG_BASE:
+ .word 0xFFFE1000
+
+.equ CONFIG_PCC_CONF, 0xB4
+.equ CONFIG_MODE1, 0x10
+.equ CONFIG_MODE2, 0x14
+.equ CONF_MOD_UART1_CLK_MODE_R, 0x0A
+
+/* misc values */
+.equ IRQ_MASK, 0x80 // IRQ mask value
+.equ FIQ_MASK, 0x40 // FIQ mask value
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/arm926ejs/start.o (.text)
+ *(.text)
+ }
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+ . = ALIGN(4);
+ .data : { *(.data) }
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
}
#endif /* CONFIG_PHY_GIGE */
- if (miiphy_read (addr, PHY_ANLPAR, ®)) {
- puts ("PHY speed1 read failed, assuming 10bT\n");
+ /* Check Basic Management Control Register first. */
+ if (miiphy_read (addr, PHY_BMCR, ®)) {
+ puts ("PHY speed read failed, assuming 10bT\n");
return (_10BASET);
}
- if ((reg & PHY_ANLPAR_100) != 0) {
+ /* Check if auto-negotiation is on. */
+ if ((reg & PHY_BMCR_AUTON) != 0) {
+ /* Get auto-negotiation results. */
+ if (miiphy_read (addr, PHY_ANLPAR, ®)) {
+ puts ("PHY AN speed read failed, assuming 10bT\n");
+ return (_10BASET);
+ }
+ if ((reg & PHY_ANLPAR_100) != 0) {
+ return (_100BASET);
+ } else {
+ return (_10BASET);
+ }
+ }
+ /* Get speed from basic control settings. */
+ else if (reg & PHY_BMCR_100MB) {
return (_100BASET);
} else {
return (_10BASET);
}
+
}
}
#endif /* CONFIG_PHY_GIGE */
- if (miiphy_read (addr, PHY_ANLPAR, ®)) {
+ /* Check Basic Management Control Register first. */
+ if (miiphy_read (addr, PHY_BMCR, ®)) {
puts ("PHY duplex read failed, assuming half duplex\n");
return (HALF);
}
+ /* Check if auto-negotiation is on. */
+ if ((reg & PHY_BMCR_AUTON) != 0) {
+ /* Get auto-negotiation results. */
+ if (miiphy_read (addr, PHY_ANLPAR, ®)) {
+ puts ("PHY AN duplex read failed, assuming half duplex\n");
+ return (HALF);
+ }
- if ((reg & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD)) != 0) {
+ if ((reg & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD)) != 0) {
+ return (FULL);
+ } else {
+ return (HALF);
+ }
+ }
+ /* Get speed from basic control settings. */
+ else if (reg & PHY_BMCR_DPLX) {
return (FULL);
} else {
return (HALF);
}
+
}
#ifdef CFG_FAULT_ECHO_LINK_DOWN
*
* Copyright (c) 2003 Texas Instruments
*
- * ----- Adapted for OMAP1610 from ARM925t code ------
+ * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
*
* Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
* Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
#if defined(CONFIG_OMAP1610)
#include <./configs/omap1510.h>
+#elif defined(CONFIG_OMAP730)
+#include <./configs/omap730.h>
#endif
/*
--- /dev/null
+
+ u-boot for the TI OMAP730 Perseus2
+
+ Dave Peverley, MPC-Data Limited
+ http://www.mpc-data.co.uk
+
+
+Overview :
+
+ As the OMAP730 is similar to the OMAP1610 in many ways, this port was based
+on the u-boot port to the OMAP1610 Innovator. Supported features are :
+
+ - Serial terminal support
+ - Onboard NOR Flash
+ - Ethernet via the seperate debug board
+ - Tested on Rev4 and Rev5 boards
+
+ It has also been tested to work correctly when built with a 'standard' GCC
+3.2.1 cross-compiler as well as Montavista Linux CEE 3.1's toolchain.
+
+
+
+Hardware Configuration :
+
+ The main dips on the P2 board should be set to 2,3,7 and 9 on with all
+others off. On the debug board, dips 1 and 7 should be on with the rest off.
+The serial console has been set up to run from the DB9 connector on the
+P2 board at 115200 baud, 8 data bits, no stop bits, 1 parity bit.
+
+ It should be noted that the P2 board has NOR flash that is addressable via
+either CS0 or CS3. This mode can be changed via DIP9 on the P2 board.
+
+
+
+Installing u-boot for the P2 :
+
+ You can simply build u-boot for the Perseus by following the instructions
+in the main readme file. The target configuration is "omap730p2_config".
+Once u-boot has been built, you should strip the executable so it can be
+loaded via CCS (which cant cope with the symbols in the ELF binary) :
+ $ cp u-boot u-boot.out
+ $ arm-linux-strip u-boot.out
+
+ The method we've used for installing u-boot the first time on a P2 is
+as follows :
+
+1) Configure TI Code Composer Studio to connect to the P2 board via JTAG
+ as described in the Users Guide.
+
+2) Set up the P2 to boot from CS3, and connect with CCS. Reset the CPU
+ and run the "init_mmu" GEL script.
+
+3) Use the "Load Program" option to send the u-boot.out file to the P2 and
+ run.
+
+ At this point, u-boot should run and you will see the boot menu on your
+serial terminal. You can then load the u-boot image to memory :
+
+ # loadb 0x10000000
+
+ Send the "u-boot.bin" binary via the serial using Kermit. Once loaded
+you can self-flash u-boot :
+
+ # protect off 1:0
+ # erase 1:0
+ # cp.b 0x10000000 0x0 0x20000
+
+ You should now be able to reset the board and run u-boot from flash.
+
+
+
+Alternative flash option :
+
+ Sometimes, if you've been silly, you can get the board into a state where
+whats in flash has upset the board so much that you can no longer connect
+to the P2 via JTAG. However, you can set DIP9 to off to swap the boot mode
+of the P2 so that you boot from RAM instead of NOR flash. This moves NOR
+flash up to 0x0C000000. You can build a special version of u-boot to
+utilise this by the following config :
+
+ $ make omap730p2_cs0boot_config
+
+ If you load this up via CCS it will detect flash at its alternate location
+and allow you to programme your u-boot image (which, remember must be built
+for CS3 boot!) Once you do this, you can revert to CS3 boot and it will work
+fine again.
+
+
+
+Errata :
+
+1) It's been observed that sometimes the tftp transfer of kernels to the
+ board can have checksum errors or stall. This appears to be an issue
+ with the lan91c96.c driver, and can normally be worked around by
+ resetting the board and trying again.
address |= smc_mac_addr[i];
SMC_outw (address, LAN91C96_IA0 + i);
}
-#else
+#else
for (i = 0; i < 6; i++)
SMC_outb (smc_mac_addr[i], LAN91C96_IA0 + i);
#endif
return (0);
}
-/*
+/*
* get_rom_mac()
* Note, this has omly been tested for the OMAP730 P2.
*/
#endif
}
-
-
#endif /* CONFIG_DRIVER_LAN91C96 */
com_port->lcr = LCRVAL;
com_port->mcr = MCRVAL;
com_port->fcr = FCRVAL;
-#if defined(CONFIG_OMAP1510) || defined(CONFIG_OMAP1610)
+#if defined(CONFIG_OMAP1510) || defined(CONFIG_OMAP1610) || defined(CONFIG_OMAP730)
com_port->mdr1 = 0; /* select uart mode */
#endif
}
--- /dev/null
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ * TI H2 and P2 Debug Board hardware map
+ *
+ * Copyright (C) 2004 MPC-Data Limited. (http://www.mpc-data.co.uk)
+ * Author: MPC-Data Limited
+ * Dave Peverley
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __INCLUDED_H2_P2_DBH_BOARD_H
+#define __INCLUDED_H2_P2_DBH_BOARD_H
+
+
+#include <asm/arch/sizes.h>
+
+
+/*
+ * The Debug board is designed to function with the P2 Sample, H2
+ * Sample and 1610 Innovator boards. The main difference AFAICT is
+ * the chip selects used with each system ;
+ *
+ * P2 Sample : CS1 of OMAP730 is used to select the CPLD & LAN regs
+ * H2 Sample : CS1a is used to select the CPLD registers.
+ *
+ */
+
+
+
+/***************************************************************************
+ * CPLD Registers
+ **************************************************************************/
+
+#define H2DBG_CPLD_REVISION 0x04000010
+#define H2DBG_BOARD_REVISION 0x04000012
+#define H2DBG_GPIO_REGISTER 0x04000014
+#define H2DBG_LED_CONTROL 0x04000016
+#define H2DBG_MISC_INPUT 0x04000018
+#define H2DBG_LAN_STATUS 0x0400001A
+#define H2DBG_LAN_RESET 0x0400001C
+#define H2DBG_ETH_REG_BASE 0x04000300
+
+
+
+/***************************************************************************
+ * Ethernet Control Registers
+ * These are for the LAN91C96 on the debug board
+ **************************************************************************/
+
+/* Bank 0 in IO space */
+
+#define ETH_TCR (H2DBG_ETH_REG_BASE + 0x00) /* Transmit Control Register */
+#define ETH_EPH_STATUS (H2DBG_ETH_REG_BASE + 0x02) /* EPH Status Register */
+#define ETH_RCR (H2DBG_ETH_REG_BASE + 0x04) /* Receive Control Register */
+#define ETH_COUNTER (H2DBG_ETH_REG_BASE + 0x06) /* Counter Register */
+#define ETH_MIR (H2DBG_ETH_REG_BASE + 0x08) /* Memory Information Register */
+#define ETH_MCR (H2DBG_ETH_REG_BASE + 0x0A) /* Memory Configuration Register */
+
+/* Bank 1 in IO space */
+
+#define ETH_CONFIG (H2DBG_ETH_REG_BASE + 0x00) /* Configuration Register */
+#define ETH_BASE (H2DBG_ETH_REG_BASE + 0x02) /* Base Address Register */
+#define ETH_IA0 (H2DBG_ETH_REG_BASE + 0x04) /* Individual Address Register - 0 */
+#define ETH_IA1 (H2DBG_ETH_REG_BASE + 0x05) /* Individual Address Register - 1 */
+#define ETH_IA2 (H2DBG_ETH_REG_BASE + 0x06) /* Individual Address Register - 2 */
+#define ETH_IA3 (H2DBG_ETH_REG_BASE + 0x07) /* Individual Address Register - 3 */
+#define ETH_IA4 (H2DBG_ETH_REG_BASE + 0x08) /* Individual Address Register - 4 */
+#define ETH_IA5 (H2DBG_ETH_REG_BASE + 0x09) /* Individual Address Register - 5 */
+#define ETH_GEN_PURPOSE (H2DBG_ETH_REG_BASE + 0x0A) /* General Address Registers */
+#define ETH_CONTROL (H2DBG_ETH_REG_BASE + 0x0B) /* Control Register */
+
+/* Bank 2 in IO space */
+
+#define ETH_MMU (H2DBG_ETH_REG_BASE + 0x00) /* MMU Command Register */
+#define ETH_AUTO_TX_START (H2DBG_ETH_REG_BASE + 0x01) /* Auto Tx Start Register */
+#define ETH_PNR (H2DBG_ETH_REG_BASE + 0x02) /* Packet Number Register */
+#define ETH_ARR (H2DBG_ETH_REG_BASE + 0x03) /* Allocation Result Register */
+#define ETH_FIFO (H2DBG_ETH_REG_BASE + 0x04) /* FIFO Ports Register */
+#define ETH_POINTER (H2DBG_ETH_REG_BASE + 0x06) /* Pointer Register */
+#define ETH_DATA_HIGH (H2DBG_ETH_REG_BASE + 0x08) /* Data High Register */
+#define ETH_DATA_LOW (H2DBG_ETH_REG_BASE + 0x0A) /* Data Low Register */
+#define ETH_INT_STATS (H2DBG_ETH_REG_BASE + 0x0C) /* Interrupt Status Register - RO */
+#define ETH_INT_ACK (H2DBG_ETH_REG_BASE + 0x0C) /* Interrupt Acknowledge Register -WO */
+#define ETH_INT_MASK (H2DBG_ETH_REG_BASE + 0x0D) /* Interrupt Mask Register */
+
+
+#ifndef __ASSEMBLY__
+
+/*
+ * A couple of utility inlines to aid debugging using the LED's on the
+ * debug board.
+ */
+
+static inline void set_led_state(int state)
+{
+ static unsigned long hw_led_state = 0;
+ volatile unsigned short *led_address = 0x04000016;
+
+ hw_led_state = ((unsigned long)state);
+ *((unsigned short *) (led_address)) = (unsigned short) (~hw_led_state & 0xFFFF);
+}
+
+
+static inline void spin_up_leds()
+{
+ volatile int i, j, k;
+
+ for (k = 0; k < 2; k++) {
+ for (i = 0; i < 16; i++) {
+ for (j = 0; j < 5000; j++) {
+ set_led_state(1 << i);
+ }
+ }
+ for (i = 15; i >= 0; i--) {
+ for (j = 0; j < 5000; j++) {
+ set_led_state(1 << i);
+ }
+ }
+ }
+}
+
+#endif /* ! __ASSEMBLY__ */
+
+#endif /* ! __INCLUDED_H2_P2_DBH_BOARD_H */
+
--- /dev/null
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ * OMAP730 hardware map
+ *
+ * Copyright (C) 2004 MPC-Data Limited. (http://www.mpc-data.co.uk)
+ * Author: MPC-Data Limited
+ * Dave Peverley
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+
+#ifndef __INCLUDED_OMAP730_H
+#define __INCLUDED_OMAP730_H
+
+#include <asm/arch/sizes.h>
+
+
+
+
+/***************************************************************************
+ * OMAP730 Configuration Registers
+ **************************************************************************/
+
+#define PERSEUS2_MPU_DEV_ID ((unsigned int)(0xFFFE1000))
+#define PERSEUS2_GSM_DEV_ID0 ((unsigned int)(0xFFFE1000))
+#define PERSEUS2_GDM_DEV_ID1 ((unsigned int)(0xFFFE1002))
+#define DSP_CONF ((unsigned int)(0xFFFE1004))
+#define PERSEUS2_MPU_DIE_ID0 ((unsigned int)(0xFFFE1008))
+#define GSM_ASIC_CONF ((unsigned int)(0xFFFE1008))
+#define PERSEUS2_MPU_DIE_ID1 ((unsigned int)(0xFFFE100C))
+#define PERSEUS2_MODE1 ((unsigned int)(0xFFFE1010))
+#define PERSEUS2_GSM_DIE_ID0 ((unsigned int)(0xFFFE1010))
+#define PERSEUS2_GSM_DIE_ID1 ((unsigned int)(0xFFFE1012))
+#define PERSEUS2_MODE2 ((unsigned int)(0xFFFE1014))
+#define PERSEUS2_GSM_DIE_ID2 ((unsigned int)(0xFFFE1014))
+#define PERSEUS2_GSM_DIE_ID3 ((unsigned int)(0xFFFE1016))
+#define PERSEUS2_ANALOG_CELLS_CONF ((unsigned int)(0xFFFE1018))
+#define SPECCTL ((unsigned int)(0xFFFE101C))
+#define SPARE1 ((unsigned int)(0xFFFE1020))
+#define SPARE2 ((unsigned int)(0xFFFE1024))
+#define GSM_PBG_IRQ ((unsigned int)(0xFFFE1028))
+#define DMA_REQ_CONF ((unsigned int)(0xFFFE1030))
+#define PE_CONF_NO_DUAL ((unsigned int)(0xFFFE1060))
+#define PERSEUS2_IO_CONF0 ((unsigned int)(0xFFFE1070))
+#define PERSEUS2_IO_CONF1 ((unsigned int)(0xFFFE1074))
+#define PERSEUS2_IO_CONF2 ((unsigned int)(0xFFFE1078))
+#define PERSEUS2_IO_CONF3 ((unsigned int)(0xFFFE107C))
+#define PERSEUS2_IO_CONF4 ((unsigned int)(0xFFFE1080))
+#define PERSEUS2_IO_CONF5 ((unsigned int)(0xFFFE1084))
+#define PERSEUS2_IO_CONF6 ((unsigned int)(0xFFFE1088))
+#define PERSEUS2_IO_CONF7 ((unsigned int)(0xFFFE108C))
+#define PERSEUS2_IO_CONF8 ((unsigned int)(0xFFFE1090))
+#define PERSEUS2_IO_CONF9 ((unsigned int)(0xFFFE1094))
+#define PERSEUS2_IO_CONF10 ((unsigned int)(0xFFFE1098))
+#define PERSEUS2_IO_CONF11 ((unsigned int)(0xFFFE109C))
+#define PERSEUS2_IO_CONF12 ((unsigned int)(0xFFFE10A0))
+#define PERSEUS2_IO_CONF13 ((unsigned int)(0xFFFE10A4))
+#define PERSEUS_PCC_CONF_REG ((unsigned int)(0xFFFE10B4))
+#define BIST_STATUS_INTERNAL ((unsigned int)(0xFFFE10B8))
+#define BIST_CONTROL ((unsigned int)(0xFFFE10C0))
+#define BOOT_ROM_REG ((unsigned int)(0xFFFE10C4))
+#define PRODUCTION_ID_REG ((unsigned int)(0xFFFE10C8))
+#define BIST_SECROM_SIGNATURE1_INTERNAL ((unsigned int)(0xFFFE10D0))
+#define BIST_SECROM_SIGNATURE2_INTERNAL ((unsigned int)(0xFFFE10D4))
+#define BIST_CONTROL_2 ((unsigned int)(0xFFFE10D8))
+#define DEBUG1 ((unsigned int)(0xFFFE10E0))
+#define DEBUG2 ((unsigned int)(0xFFFE10E4))
+#define DEBUG_DMA_IRQ ((unsigned int)(0xFFFE10E8))
+
+
+
+
+/***************************************************************************
+ * OMAP730 EMIFS Registers (TRM 2.5.7)
+ **************************************************************************/
+
+#define TCMIF_BASE 0xFFFECC00
+
+#define EMIFS_LRUREG (TCMIF_BASE + 0x04)
+#define EMIFS_CONFIG (TCMIF_BASE + 0x0C)
+#define FLASH_CFG_0 (TCMIF_BASE + 0x10)
+#define FLASH_CFG_1 (TCMIF_BASE + 0x14)
+#define FLASH_CFG_2 (TCMIF_BASE + 0x18)
+#define FLASH_CFG_3 (TCMIF_BASE + 0x1C)
+#define FL_CFG_DYN_WAIT (TCMIF_BASE + 0x40)
+#define EMIFS_TIMEOUT1_REG (TCMIF_BASE + 0x28)
+#define EMIFS_TIMEOUT2_REG (TCMIF_BASE + 0x2C)
+#define EMIFS_TIMEOUT3_REG (TCMIF_BASE + 0x30)
+#define EMIFS_ABORT_ADDR (TCMIF_BASE + 0x44)
+#define EMIFS_ABORT_TYPE (TCMIF_BASE + 0x48)
+#define EMIFS_ABORT_TOUT (TCMIF_BASE + 0x4C)
+#define FLASH_ACFG_0_1 (TCMIF_BASE + 0x50)
+#define FLASH_ACFG_1_1 (TCMIF_BASE + 0x54)
+#define FLASH_ACFG_2_1 (TCMIF_BASE + 0x58)
+#define FLASH_ACFG_3_1 (TCMIF_BASE + 0x5C)
+
+
+
+/***************************************************************************
+ * OMAP730 Interrupt handlers
+ **************************************************************************/
+
+#define OMAP_IH1_BASE 0xFFFECB00 /* MPU Level 1 IRQ handler */
+#define OMAP_IH2_BASE 0xfffe0000
+
+
+
+/***************************************************************************
+ * OMAP730 Timers
+ *
+ * There are three general purpose OS timers in the 730 that can be
+ * configured in autoreload or one-shot modes.
+ **************************************************************************/
+
+#define OMAP730_32kHz_TIMER_BASE 0xFFFB9000
+
+/* 32k Timer Registers */
+#define TIMER32k_CR 0x08
+#define TIMER32k_TVR 0x00
+#define TIMER32k_TCR 0x04
+
+/* 32k Timer Control Register definition */
+#define TIMER32k_TSS (1<<0)
+#define TIMER32k_TRB (1<<1)
+#define TIMER32k_INT (1<<2)
+#define TIMER32k_ARL (1<<3)
+
+/* MPU Timer base addresses */
+#define OMAP730_MPUTIMER_BASE 0xfffec500
+#define OMAP730_MPUTIMER_OFF 0x00000100
+
+#define OMAP730_TIMER1_BASE 0xFFFEC500
+#define OMAP730_TIMER2_BASE 0xFFFEC600
+#define OMAP730_TIMER3_BASE 0xFFFEC700
+
+/* MPU Timer Register offsets */
+#define CNTL_TIMER 0x00 /* MPU_CNTL_TIMER */
+#define LOAD_TIM 0x04 /* MPU_LOAD_TIMER */
+#define READ_TIM 0x08 /* MPU_READ_TIMER */
+
+/* MPU_CNTL_TIMER register bits */
+#define MPUTIM_FREE (1<<6)
+#define MPUTIM_CLOCK_ENABLE (1<<5)
+#define MPUTIM_PTV_MASK (0x7<<PTV_BIT)
+#define MPUTIM_PTV_BIT 2
+#define MPUTIM_AR (1<<1)
+#define MPUTIM_ST (1<<0)
+
+
+
+/***************************************************************************
+ * OMAP730 GPIO
+ *
+ * The GPIO control is split over 6 register bases in the OMAP730 to allow
+ * access to all the (6 x 32) GPIO pins!
+ **************************************************************************/
+
+#define OMAP730_GPIO_BASE_1 0xFFFBC000
+#define OMAP730_GPIO_BASE_2 0xFFFBC800
+#define OMAP730_GPIO_BASE_3 0xFFFBD000
+#define OMAP730_GPIO_BASE_4 0xFFFBD800
+#define OMAP730_GPIO_BASE_5 0xFFFBE000
+#define OMAP730_GPIO_BASE_6 0xFFFBE800
+
+#define GPIO_DATA_INPUT 0x00
+#define GPIO_DATA_OUTPUT 0x04
+#define GPIO_DIRECTION_CONTROL 0x08
+#define GPIO_INTERRUPT_CONTROL 0x0C
+#define GPIO_INTERRUPT_MASK 0x10
+#define GPIO_INTERRUPT_STATUS 0x14
+
+#define GPIO_DATA_INPUT_1 ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_DATA_INPUT))
+#define GPIO_DATA_OUTPUT_1 ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_DATA_OUTPUT))
+#define GPIO_DIRECTION_CONTROL_1 ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_DIRECTION_CONTROL))
+#define GPIO_INTERRUPT_CONTROL_1 ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_INTERRUPT_CONTROL))
+#define GPIO_INTERRUPT_MASK_1 ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_INTERRUPT_MASK))
+#define GPIO_INTERRUPT_STATUS_1 ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_INTERRUPT_STATUS))
+
+#define GPIO_DATA_INPUT_2 ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_DATA_INPUT))
+#define GPIO_DATA_OUTPUT_2 ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_DATA_OUTPUT))
+#define GPIO_DIRECTION_CONTROL_2 ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_DIRECTION_CONTROL))
+#define GPIO_INTERRUPT_CONTROL_2 ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_INTERRUPT_CONTROL))
+#define GPIO_INTERRUPT_MASK_2 ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_INTERRUPT_MASK))
+#define GPIO_INTERRUPT_STATUS_2 ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_INTERRUPT_STATUS))
+
+#define GPIO_DATA_INPUT_3 ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_DATA_INPUT))
+#define GPIO_DATA_OUTPUT_3 ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_DATA_OUTPUT))
+#define GPIO_DIRECTION_CONTROL_3 ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_DIRECTION_CONTROL))
+#define GPIO_INTERRUPT_CONTROL_3 ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_INTERRUPT_CONTROL))
+#define GPIO_INTERRUPT_MASK_3 ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_INTERRUPT_MASK))
+#define GPIO_INTERRUPT_STATUS_3 ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_INTERRUPT_STATUS))
+
+#define GPIO_DATA_INPUT_4 ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_DATA_INPUT))
+#define GPIO_DATA_OUTPUT_4 ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_DATA_OUTPUT))
+#define GPIO_DIRECTION_CONTROL_4 ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_DIRECTION_CONTROL))
+#define GPIO_INTERRUPT_CONTROL_4 ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_INTERRUPT_CONTROL))
+#define GPIO_INTERRUPT_MASK_4 ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_INTERRUPT_MASK))
+#define GPIO_INTERRUPT_STATUS_4 ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_INTERRUPT_STATUS))
+
+#define GPIO_DATA_INPUT_5 ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_DATA_INPUT))
+#define GPIO_DATA_OUTPUT_5 ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_DATA_OUTPUT))
+#define GPIO_DIRECTION_CONTROL_5 ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_DIRECTION_CONTROL))
+#define GPIO_INTERRUPT_CONTROL_5 ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_INTERRUPT_CONTROL))
+#define GPIO_INTERRUPT_MASK_5 ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_INTERRUPT_MASK))
+#define GPIO_INTERRUPT_STATUS_5 ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_INTERRUPT_STATUS))
+
+#define GPIO_DATA_INPUT_6 ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_DATA_INPUT))
+#define GPIO_DATA_OUTPUT_6 ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_DATA_OUTPUT))
+#define GPIO_DIRECTION_CONTROL_6 ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_DIRECTION_CONTROL))
+#define GPIO_INTERRUPT_CONTROL_6 ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_INTERRUPT_CONTROL))
+#define GPIO_INTERRUPT_MASK_6 ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_INTERRUPT_MASK))
+#define GPIO_INTERRUPT_STATUS_6 ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_INTERRUPT_STATUS))
+
+
+
+
+/***************************************************************************
+ * OMAP730 Watchdog timers
+ **************************************************************************/
+
+#define WDTIM_BASE 0xFFFEC800
+#define WDTIM_CONTROL (WDTIM_BASE + 0x00) /* MPU_CNTL_TIMER */
+#define WDTIM_LOAD (WDTIM_BASE + 0x04) /* MPU_LOAD_TIMER */
+#define WDTIM_READ (WDTIM_BASE + 0x04) /* MPU_READ_TIMER */
+#define WDTIM_MODE (WDTIM_BASE + 0x08) /* MPU_TIMER_MODE */
+
+
+
+
+/***************************************************************************
+ * OMAP730 Interrupt Registers
+ **************************************************************************/
+
+/* Interrupt Register offsets */
+
+#define IRQ_ITR 0x00
+#define IRQ_MIR 0x04
+#define IRQ_SIR_IRQ 0x10
+#define IRQ_SIR_FIQ 0x14
+#define IRQ_CONTROL_REG 0x18
+#define IRQ_ILR0 0x1C /* ILRx == ILR0 + (0x4 * x) */
+#define IRQ_SIR 0x9C /* a.k.a.IRQ_ISR */
+#define IRQ_GMIR 0xA0
+
+#define REG_IHL1_MIR (OMAP_IH1_BASE + IRQ_MIR)
+#define REG_IHL2_MIR (OMAP_IH2_BASE + IRQ_MIR)
+
+
+/***************************************************************************
+ * OMAP730 Intersystem Communication Register (TRM 4.5)
+ **************************************************************************/
+
+
+#define ICR_BASE 0xFFFBB800
+
+#define M_ICR (ICR_BASE + 0x00)
+#define G_ICR (ICR_BASE + 0x02)
+#define M_CTL (ICR_BASE + 0x04)
+#define G_CTL (ICR_BASE + 0x06)
+#define PM_BA (ICR_BASE + 0x0A)
+#define DM_BA (ICR_BASE + 0x0C)
+#define RM_BA (ICR_BASE + 0x0E)
+#define SSPI_TAS (ICR_BASE + 0x12)
+
+
+
+#endif /* ! __INCLUDED_OMAP730_H */
--- /dev/null
+/*
+ * (C) Copyright 2003-2004
+ * MPC Data Limited (http://www.mpc-data.co.uk)
+ * Dave Peverley <dpeverley at mpc-data.co.uk>
+ *
+ * Configuation settings for the TI OMAP Perseus 2 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+
+/*
+ * If we are developing, we might want to start armboot from ram
+ * so we MUST NOT initialize critical regs like mem-timing ...
+ */
+
+#define CONFIG_INIT_CRITICAL /* undef for developing */
+
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */
+#define CONFIG_OMAP 1 /* in a TI OMAP core */
+#define CONFIG_OMAP730 1 /* which is in a 730 */
+#define CONFIG_P2_OMAP730 1 /* a Perseus 2 Board */
+
+
+/*
+ * Input clock of PLL
+ * The OMAP730 Perseus 2 has 13MHz input clock
+ */
+
+#define CONFIG_SYS_CLK_FREQ 13000000
+
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+
+
+/*
+ * Size of malloc() pool
+ */
+
+#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+
+
+/*
+ * Hardware drivers
+ */
+
+#define CONFIG_DRIVER_LAN91C96
+#define CONFIG_LAN91C96_BASE 0x04000300
+#define CONFIG_LAN91C96_EXT_PHY
+
+
+/*
+ * NS16550 Configuration
+ */
+
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE (1)
+#define CFG_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */
+#define CFG_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart
+ * on perseus */
+
+/*
+ * select serial console configuration
+ */
+
+#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP730 Perseus 2 */
+
+
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP)
+#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
+
+/*
+ * This must be included AFTER the definition of CONFIG_COMMANDS (if any)
+ */
+
+#include <cmd_confdefs.h>
+#include <configs/omap730.h>
+#include <configs/h2_p2_dbg_board.h>
+
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd root=/dev/nfs rw ip=bootp"
+
+#define CONFIG_LOADADDR 0x10000000
+
+#define CONFIG_ETHADDR
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_IPADDR 192.168.0.23
+#define CONFIG_SERVERIP 192.150.0.100
+#define CONFIG_BOOTFILE "uImage" /* File to load */
+
+#if defined (CONFIG_COMMANDS) && defined (CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 115200 /* Speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 1 /* Which serial port to use */
+#endif
+
+
+/*
+ * Miscellaneous configurable options
+ */
+
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "OMAP730 P2 # " /* Monitor Command Prompt */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x10000000 /* memtest works on */
+#define CFG_MEMTEST_END 0x12000000 /* 32 MB in DRAM */
+
+#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR 0x10000000 /* default load address */
+
+
+/* The OMAP730 has 3 general purpose MPU timers, they can be driven by
+ * the RefClk (12Mhz) or by DPLL1. This time is further subdivided by a
+ * local divisor.
+ */
+
+#define CFG_TIMERBASE 0xFFFEC500 /* use timer 1 */
+#define CFG_PVT 7 /* 2^(pvt+1), divide by 256 */
+#define CFG_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT))
+
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+
+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
+#endif
+
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
+
+#if defined(CONFIG_CS0_BOOT)
+#define PHYS_FLASH_1 0x0C000000
+#elif defined(CONFIG_CS3_BOOT)
+#define PHYS_FLASH_1 0x00000000
+#else
+#error Unknown Boot Chip-Select number
+#endif
+
+#define CFG_FLASH_BASE PHYS_FLASH_1
+
+
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define PHYS_FLASH_SIZE 0x02000000 /* 32MB */
+#define CFG_MAX_FLASH_SECT (259) /* max number of sectors on one chip */
+/* addr of environment */
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x020000)
+
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT (20*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT (20*CFG_HZ) /* Timeout for Flash Write */
+
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
+#define CFG_ENV_OFFSET 0x20000 /* environment starts here */
+
+
+
+#endif /* ! __CONFIG_H */
unsigned char lsr; /* 5 */
unsigned char msr; /* 6 */
unsigned char scr; /* 7 */
+#if defined(CONFIG_OMAP730)
+ unsigned char mdr1; /* 8 */
+ unsigned char reg9; /* 9 */
+ unsigned char regA; /* A */
+ unsigned char regB; /* B */
+ unsigned char regC; /* C */
+ unsigned char regD; /* D */
+ unsigned char regE; /* E */
+ unsigned char regF; /* F */
+ unsigned char reg10; /* 10 */
+ unsigned char ssr; /* 11*/
+#endif
} __attribute__ ((packed));
#elif (CFG_NS16550_REG_SIZE == 2)
struct NS16550 {
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