trizepsiv xscale/pxa
twister omap3
vision2 i.MX51
+ woodburn i.MX35
Lukasz Dalek <luk0104@gmail.com>
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
MS7720SE SH7720
+ R0P77520000RZ SH7752
R0P77570030RL SH7757
R0P77850011RL SH7785
VERSION = 2013
PATCHLEVEL = 01
SUBLEVEL =
-EXTRAVERSION = -rc2
+EXTRAVERSION =
ifneq "$(SUBLEVEL)" ""
U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
else
endif
LIBS-y += drivers/rtc/librtc.o
LIBS-y += drivers/serial/libserial.o
+LIBS-y += drivers/sound/libsound.o
LIBS-$(CONFIG_GENERIC_LPC_TPM) += drivers/tpm/libtpm.o
LIBS-y += drivers/twserial/libtws.o
LIBS-y += drivers/usb/eth/libusb_eth.o
ELFTOSB_TARGET-$(CONFIG_MX28) = imx28
$(obj)u-boot.sb: $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin
- elftosb -zdf $(ELFTOSB_TARGET-y) -c $(TOPDIR)/$(CPUDIR)/$(SOC)/u-boot-$(ELFTOSB_TARGET-y).bd \
+ elftosb -zf $(ELFTOSB_TARGET-y) -c $(TOPDIR)/$(CPUDIR)/$(SOC)/u-boot-$(ELFTOSB_TARGET-y).bd \
-o $(obj)u-boot.sb
# On x600 (SPEAr600) U-Boot is appended to U-Boot SPL.
@rm -f $(obj)nand_spl/{u-boot-nand_spl.lds,u-boot-spl,u-boot-spl.map}
@rm -f $(obj)spl/{u-boot-spl,u-boot-spl.bin,u-boot-spl.map}
@rm -f $(obj)spl/{u-boot-spl.lds,u-boot.lst}
- @rm -f $(obj)MLO
+ @rm -f $(obj)MLO MLO.byteswap
+ @rm -f $(obj)SPL
@rm -f $(obj)tools/xway-swap-bytes
@rm -f $(obj)arch/powerpc/cpu/mpc824x/bedbug_603e.c
@rm -f $(obj)arch/powerpc/cpu/mpc83xx/ddr-gen?.c
boot loader that has already initialized the UART. Define this
variable to flush the UART at init time.
+ CONFIG_SYS_NS16550_BROKEN_TEMT
+
+ 16550 UART set the Transmitter Empty (TEMT) Bit when all output
+ has finished and the transmitter is totally empty. U-Boot waits
+ for this bit to be set to initialize the serial console. On some
+ broken platforms this bit is not set in SPL making U-Boot to
+ hang while waiting for TEMT. Define this option to avoid it.
+
- Console Interface:
Depending on board, define exactly one serial port
CONFIG_CMD_LOADS loads
CONFIG_CMD_MD5SUM print md5 message digest
(requires CONFIG_CMD_MEMORY and CONFIG_MD5)
+ CONFIG_CMD_MEMINFO * Display detailed memory information
CONFIG_CMD_MEMORY md, mm, nm, mw, cp, cmp, crc, base,
loop, loopw, mtest
CONFIG_CMD_MISC Misc functions like sleep etc
Normally display is black on white background; define
CONFIG_SYS_WHITE_ON_BLACK to get it inverted.
+ CONFIG_LCD_ALIGNMENT
+
+ Normally the LCD is page-aligned (tyically 4KB). If this is
+ defined then the LCD will be aligned to this value instead.
+ For ARM it is sometimes useful to use MMU_SECTION_SIZE
+ here, since it is cheaper to change data cache settings on
+ a per-section basis.
+
+ CONFIG_CONSOLE_SCROLL_LINES
+
+ When the console need to be scrolled, this is the number of
+ lines to scroll by. It defaults to 1. Increasing this makes
+ the console jump but can help speed up operation when scrolling
+ is slow.
+
CONFIG_LCD_BMP_RLE8
Support drawing of RLE8-compressed bitmaps on the LCD.
Enables an 'i2c edid' command which can read EDID
information over I2C from an attached LCD display.
-
- Splash Screen Support: CONFIG_SPLASH_SCREEN
If this option is set, the environment is checked for
run-time determined information about the hardware to the
environment. These will be named board_name, board_rev.
+ CONFIG_DELAY_ENVIRONMENT
+
+ Normally the environment is loaded when the board is
+ intialised so that it is available to U-Boot. This inhibits
+ that so that the environment is not available until
+ explicitly loaded later by U-Boot code. With CONFIG_OF_CONTROL
+ this is instead controlled by the value of
+ /config/load-environment.
+
- DataFlash Support:
CONFIG_HAS_DATAFLASH
CONFIG_SF_DEFAULT_MODE (see include/spi.h)
CONFIG_SF_DEFAULT_SPEED in Hz
+ CONFIG_CMD_SF_TEST
+
+ Define this option to include a destructive SPI flash
+ test ('sf test').
+
- SystemACE Support:
CONFIG_SYSTEMACE
CONFIG_FB_ADDR
Define CONFIG_FB_ADDR if you want to use specific
- address for frame buffer.
- Then system will reserve the frame buffer address to
- defined address instead of lcd_setmem (this function
- grabs the memory for frame buffer by panel's size).
+ address for frame buffer. This is typically the case
+ when using a graphics controller has separate video
+ memory. U-Boot will then place the frame buffer at
+ the given address instead of dynamically reserving it
+ in system RAM by calling lcd_setmem(), which grabs
+ the memory for the frame buffer depending on the
+ configured panel size.
Please see board_init_f function.
non page size aligned address and this could cause major
problems.
-- CONFIG_SYS_TFTP_LOADADDR:
- Default load address for network file downloads
-
- CONFIG_SYS_LOADS_BAUD_CHANGE:
Enable temporary baudrate change while serial download
space for already greatly restricted images, including but not
limited to NAND_SPL configurations.
+- CONFIG_DISPLAY_BOARDINFO
+ Display information about the board that U-Boot is running on
+ when U-Boot starts up. The board function checkboard() is called
+ to do this.
+
+- CONFIG_DISPLAY_BOARDINFO_LATE
+ Similar to the previous option, but display this information
+ later, once stdio is running and output goes to the LCD, if
+ present.
+
Low Level (hardware related) configuration options:
---------------------------------------------------
# =========================================================================
PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
+ifdef CONFIG_SPL_BUILD
+ALL-y += $(OBJTREE)/SPL
+endif
flush_dcache_range(start, start + size);
}
-void enable_caches(void)
-{
-#ifndef CONFIG_SYS_ICACHE_OFF
- icache_enable();
-#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
- dcache_enable();
-#endif
-}
-
#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
void invalidate_dcache_all(void)
{
{
}
#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+
+#if !defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF)
+void enable_caches(void)
+{
+#ifndef CONFIG_SYS_ICACHE_OFF
+ icache_enable();
+#endif
+#ifndef CONFIG_SYS_DCACHE_OFF
+ dcache_enable();
+#endif
+}
+#endif
{
return MXC_CLK32;
}
-
-void reset_cpu(ulong addr)
-{
- struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE;
- wdog->wcr = WDOG_ENABLE;
- while (1)
- ;
-}
-
-#ifdef CONFIG_HW_WATCHDOG
-void mxc_hw_watchdog_enable(void)
-{
- struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE;
- u16 secs;
-
- /*
- * The timer watchdog can be set between
- * 0.5 and 128 Seconds. If not defined
- * in configuration file, sets 64 Seconds
- */
-#ifdef CONFIG_SYS_WD_TIMER_SECS
- secs = (CONFIG_SYS_WD_TIMER_SECS << 1) & 0xFF;
- if (!secs) secs = 1;
-#else
- secs = 64;
-#endif
- setbits_le16(&wdog->wcr, (secs << WDOG_WT_SHIFT) | WDOG_ENABLE
- | WDOG_WDZST);
-}
-
-
-void mxc_hw_watchdog_reset(void)
-{
- struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE;
-
- writew(0x5555, &wdog->wsr);
- writew(0xAAAA, &wdog->wsr);
-}
-#endif
COBJS += generic.o
COBJS += timer.o
COBJS += iomux.o
+COBJS += mx35_sdram.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
#include <fsl_esdhc.h>
#endif
#include <netdev.h>
+#include <spl.h>
#define CLK_CODE(arm, ahb, sel) (((arm) << 16) + ((ahb) << 8) + (sel))
#define CLK_CODE_ARM(c) (((c) >> 16) & 0xFF)
return 0;
}
-void reset_cpu(ulong addr)
+#define RCSR_MEM_CTL_WEIM 0
+#define RCSR_MEM_CTL_NAND 1
+#define RCSR_MEM_CTL_ATA 2
+#define RCSR_MEM_CTL_EXPANSION 3
+#define RCSR_MEM_TYPE_NOR 0
+#define RCSR_MEM_TYPE_ONENAND 2
+#define RCSR_MEM_TYPE_SD 0
+#define RCSR_MEM_TYPE_I2C 2
+#define RCSR_MEM_TYPE_SPI 3
+
+u32 spl_boot_device(void)
{
- struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
- writew(4, &wdog->wcr);
+ struct ccm_regs *ccm =
+ (struct ccm_regs *)IMX_CCM_BASE;
+
+ u32 rcsr = readl(&ccm->rcsr);
+ u32 mem_type, mem_ctl;
+
+ /* In external mode, no boot device is returned */
+ if ((rcsr >> 10) & 0x03)
+ return BOOT_DEVICE_NONE;
+
+ mem_ctl = (rcsr >> 25) & 0x03;
+ mem_type = (rcsr >> 23) & 0x03;
+
+ switch (mem_ctl) {
+ case RCSR_MEM_CTL_WEIM:
+ switch (mem_type) {
+ case RCSR_MEM_TYPE_NOR:
+ return BOOT_DEVICE_NOR;
+ case RCSR_MEM_TYPE_ONENAND:
+ return BOOT_DEVICE_ONE_NAND;
+ default:
+ return BOOT_DEVICE_NONE;
+ }
+ case RCSR_MEM_CTL_NAND:
+ return BOOT_DEVICE_NAND;
+ case RCSR_MEM_CTL_EXPANSION:
+ switch (mem_type) {
+ case RCSR_MEM_TYPE_SD:
+ return BOOT_DEVICE_MMC1;
+ case RCSR_MEM_TYPE_I2C:
+ return BOOT_DEVICE_I2C;
+ case RCSR_MEM_TYPE_SPI:
+ return BOOT_DEVICE_SPI;
+ default:
+ return BOOT_DEVICE_NONE;
+ }
+ }
+
+ return BOOT_DEVICE_NONE;
}
+
+#ifdef CONFIG_SPL_BUILD
+u32 spl_boot_mode(void)
+{
+ switch (spl_boot_device()) {
+ case BOOT_DEVICE_MMC1:
+#ifdef CONFIG_SPL_FAT_SUPPORT
+ return MMCSD_MODE_FAT;
+#else
+ return MMCSD_MODE_RAW;
+#endif
+ break;
+ case BOOT_DEVICE_NAND:
+ return 0;
+ break;
+ default:
+ puts("spl: ERROR: unsupported device\n");
+ hang();
+ }
+}
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2012, Stefano Babic <sbabic@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/imx-regs.h>
+#include <linux/types.h>
+#include <asm/arch/sys_proto.h>
+
+#define ESDCTL_DDR2_EMR2 0x04000000
+#define ESDCTL_DDR2_EMR3 0x06000000
+#define ESDCTL_PRECHARGE 0x00000400
+#define ESDCTL_DDR2_EN_DLL 0x02000400
+#define ESDCTL_DDR2_RESET_DLL 0x00000333
+#define ESDCTL_DDR2_MR 0x00000233
+#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
+
+enum {
+ SMODE_NORMAL = 0,
+ SMODE_PRECHARGE,
+ SMODE_AUTO_REFRESH,
+ SMODE_LOAD_REG,
+ SMODE_MANUAL_REFRESH
+};
+
+#define set_mode(x, en, m) (x | (en << 31) | (m << 28))
+
+static inline void dram_wait(unsigned int count)
+{
+ volatile unsigned int wait = count;
+
+ while (wait--)
+ ;
+
+}
+
+void mx3_setup_sdram_bank(u32 start_address, u32 ddr2_config,
+ u32 row, u32 col, u32 dsize, u32 refresh)
+{
+ struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
+ u32 *cfg_reg, *ctl_reg;
+ u32 val;
+ u32 ctlval;
+
+ switch (start_address) {
+ case CSD0_BASE_ADDR:
+ cfg_reg = &esdc->esdcfg0;
+ ctl_reg = &esdc->esdctl0;
+ break;
+ case CSD1_BASE_ADDR:
+ cfg_reg = &esdc->esdcfg1;
+ ctl_reg = &esdc->esdctl1;
+ break;
+ default:
+ return;
+ }
+
+ /* The MX35 supports 11 up to 14 rows */
+ if (row < 11 || row > 14 || col < 8 || col > 10)
+ return;
+ ctlval = (row - 11) << 24 | (col - 8) << 20 | (dsize << 16);
+
+ /* Initialize MISC register for DDR2 */
+ val = ESDC_MISC_RST | ESDC_MISC_MDDR_EN | ESDC_MISC_MDDR_DL_RST |
+ ESDC_MISC_DDR_EN | ESDC_MISC_DDR2_EN;
+ writel(val, &esdc->esdmisc);
+ val &= ~(ESDC_MISC_RST | ESDC_MISC_MDDR_DL_RST);
+ writel(val, &esdc->esdmisc);
+
+ /*
+ * according to DDR2 specs, wait a while before
+ * the PRECHARGE_ALL command
+ */
+ dram_wait(0x20000);
+
+ /* Load DDR2 config and timing */
+ writel(ddr2_config, cfg_reg);
+
+ /* Precharge ALL */
+ writel(set_mode(ctlval, 1, SMODE_PRECHARGE),
+ ctl_reg);
+ writel(0xda, start_address + ESDCTL_PRECHARGE);
+
+ /* Load mode */
+ writel(set_mode(ctlval, 1, SMODE_LOAD_REG),
+ ctl_reg);
+ writeb(0xda, start_address + ESDCTL_DDR2_EMR2); /* EMRS2 */
+ writeb(0xda, start_address + ESDCTL_DDR2_EMR3); /* EMRS3 */
+ writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
+ writeb(0xda, start_address + ESDCTL_DDR2_RESET_DLL); /* Reset DLL */
+
+ /* Precharge ALL */
+ writel(set_mode(ctlval, 1, SMODE_PRECHARGE),
+ ctl_reg);
+ writel(0xda, start_address + ESDCTL_PRECHARGE);
+
+ /* Set mode auto refresh : at least two refresh are required */
+ writel(set_mode(ctlval, 1, SMODE_AUTO_REFRESH),
+ ctl_reg);
+ writel(0xda, start_address);
+ writel(0xda, start_address);
+
+ writel(set_mode(ctlval, 1, SMODE_LOAD_REG),
+ ctl_reg);
+ writeb(0xda, start_address + ESDCTL_DDR2_MR);
+ writeb(0xda, start_address + ESDCTL_DDR2_OCD_DEFAULT);
+
+ /* OCD mode exit */
+ writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
+
+ /* Set normal mode */
+ writel(set_mode(ctlval, 1, SMODE_NORMAL) | refresh,
+ ctl_reg);
+
+ dram_wait(0x20000);
+
+ /* Do not set delay lines, only for MDDR */
+}
_bss_start_ofs:
.word __bss_start - _start
+.global _image_copy_end_ofs
+_image_copy_end_ofs:
+ .word __image_copy_end - _start
+
.globl _bss_end_ofs
_bss_end_ofs:
.word __bss_end__ - _start
bl cpu_init_crit
#endif
-/* Set stackpointer in internal RAM to call board_init_f */
-call_board_init_f:
- ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
- bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
- ldr r0,=0x00000000
-
- bl board_init_f
+ bl _main
/*------------------------------------------------------------------------------*/
mov r5, r1 /* save addr of gd */
mov r6, r2 /* save addr of destination */
- /* Set up the stack */
-stack_setup:
- mov sp, r4
-
adr r0, _start
cmp r0, r6
moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
- beq clear_bss /* skip relocation */
+ beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
- ldr r3, _bss_start_ofs
+ ldr r3, _image_copy_end_ofs
add r2, r0, r3 /* r2 <- source end address */
copy_loop:
add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
cmp r2, r3
blo fixloop
+ bx lr
+
#endif
-clear_bss:
-#ifndef CONFIG_SPL_BUILD
- ldr r0, _bss_start_ofs
- ldr r1, _bss_end_ofs
- mov r4, r6 /* reloc addr */
- add r0, r0, r4
- add r1, r1, r4
- mov r2, #0x00000000 /* clear */
-
-clbss_l:cmp r0, r1 /* clear loop... */
- bhs clbss_e /* if reached end of bss, exit */
- str r2, [r0]
- add r0, r0, #4
- b clbss_l
-clbss_e:
-#endif /* #ifndef CONFIG_SPL_BUILD */
+relocate_done:
-/*
- * We are done. Do not return, instead branch to second part of board
- * initialization, now running from RAM.
- */
-#ifdef CONFIG_NAND_SPL
- ldr r0, _nand_boot_ofs
- mov pc, r0
+ bx lr
-_nand_boot_ofs:
- .word nand_boot
-#else
-jump_2_ram:
- ldr r0, _board_init_r_ofs
- ldr r1, _TEXT_BASE
- add lr, r0, r1
- add lr, lr, r9
- /* setup parameters for board_init_r */
- mov r0, r5 /* gd_t */
- mov r1, r6 /* dest_addr */
- /* jump to it ... */
- mov pc, lr
-
-_board_init_r_ofs:
- .word board_init_r - _start
-#endif
+#ifndef CONFIG_SPL_BUILD
_rel_dyn_start_ofs:
.word __rel_dyn_start - _start
_dynsym_start_ofs:
.word __dynsym_start - _start
+#endif
+
+ .globl c_runtime_cpu_setup
+c_runtime_cpu_setup:
+
+ bx lr
+
/*
*************************************************************************
*
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ * Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
+ LENGTH = CONFIG_SPL_MAX_SIZE }
+MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
+ LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ .text :
+ {
+ __start = .;
+ arch/arm/cpu/arm1136/start.o (.text)
+ *(.text*)
+ } >.sram
+
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
+
+ . = ALIGN(4);
+ .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
+ . = ALIGN(4);
+ __image_copy_end = .;
+ _end = .;
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start = .;
+ *(.bss*)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } >.sdram
+}
SOBJS = reset.o
COBJS-$(CONFIG_S3C6400) += cpu_init.o speed.o
-COBJS-y += timer.o
+COBJS-y += timer.o init.o
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
--- /dev/null
+/*
+ * (C) Copyright 2012 Ashok Kumar Reddy Kourla
+ * ashokkourla2000@gmail.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include<common.h>
+
+int arch_cpu_init(void)
+{
+ icache_enable();
+
+ return 0;
+}
*/
bl lowlevel_init /* go setup pll,mux,memory */
-/* Set stackpointer in internal RAM to call board_init_f */
-call_board_init_f:
- ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
- bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
- ldr r0,=0x00000000
- bl board_init_f
+ bl _main
/*------------------------------------------------------------------------------*/
mov r5, r1 /* save addr of gd */
mov r6, r2 /* save addr of destination */
- /* Set up the stack */
-stack_setup:
- mov sp, r4
-
adr r0, _start
cmp r0, r6
moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
- beq clear_bss /* skip relocation */
+ beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */
skip_hw_init:
#endif
-clear_bss:
-#ifndef CONFIG_SPL_BUILD
- ldr r0, _bss_start_ofs
- ldr r1, _bss_end_ofs
- mov r4, r6 /* reloc addr */
- add r0, r0, r4
- add r1, r1, r4
- mov r2, #0x00000000 /* clear */
-
-clbss_l:cmp r0, r1 /* clear loop... */
- bhs clbss_e /* if reached end of bss, exit */
- str r2, [r0]
- add r0, r0, #4
- b clbss_l
-clbss_e:
-#ifndef CONFIG_NAND_SPL
- bl coloured_LED_init
- bl red_led_on
-#endif
-#endif
+relocate_done:
-/*
- * We are done. Do not return, instead branch to second part of board
- * initialization, now running from RAM.
- */
-#ifdef CONFIG_NAND_SPL
- ldr pc, _nand_boot
-
-_nand_boot: .word nand_boot
-#else
- ldr r0, _board_init_r_ofs
- adr r1, _start
- add lr, r0, r1
- add lr, lr, r9
- /* setup parameters for board_init_r */
- mov r0, r5 /* gd_t */
- mov r1, r6 /* dest_addr */
- /* jump to it ... */
- mov pc, lr
-
-_board_init_r_ofs:
- .word board_init_r - _start
-#endif
+ bx lr
_rel_dyn_start_ofs:
.word __rel_dyn_start - _start
.word mmu_table
#endif
+ .globl c_runtime_cpu_setup
+c_runtime_cpu_setup:
+
+ mov pc, lr
+
#ifndef CONFIG_NAND_SPL
/*
* we assume that cache operation is done before. (eg. cleanup_before_linux())
bl cpu_init_crit
#endif
-/* Set stackpointer in internal RAM to call board_init_f */
-call_board_init_f:
- ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
- bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
- ldr r0,=0x00000000
- bl board_init_f
+ bl _main
/*------------------------------------------------------------------------------*/
mov r5, r1 /* save addr of gd */
mov r6, r2 /* save addr of destination */
- /* Set up the stack */
-stack_setup:
- mov sp, r4
-
adr r0, _start
cmp r0, r6
moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
- beq clear_bss /* skip relocation */
+ beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */
blo fixloop
#endif
-clear_bss:
-#ifndef CONFIG_SPL_BUILD
- ldr r0, _bss_start_ofs
- ldr r1, _bss_end_ofs
- mov r4, r6 /* reloc addr */
- add r0, r0, r4
- add r1, r1, r4
- mov r2, #0x00000000 /* clear */
-
-clbss_l:cmp r0, r1 /* clear loop... */
- bhs clbss_e /* if reached end of bss, exit */
- str r2, [r0]
- add r0, r0, #4
- b clbss_l
-clbss_e:
-
- bl coloured_LED_init
- bl red_led_on
-#endif
+relocate_done:
-/*
- * We are done. Do not return, instead branch to second part of board
- * initialization, now running from RAM.
- */
- ldr r0, _board_init_r_ofs
- adr r1, _start
- add lr, r0, r1
- add lr, lr, r9
- /* setup parameters for board_init_r */
- mov r0, r5 /* gd_t */
- mov r1, r6 /* dest_addr */
- /* jump to it ... */
mov pc, lr
-_board_init_r_ofs:
- .word board_init_r - _start
-
_rel_dyn_start_ofs:
.word __rel_dyn_start - _start
_rel_dyn_end_ofs:
_dynsym_start_ofs:
.word __dynsym_start - _start
+ .globl c_runtime_cpu_setup
+c_runtime_cpu_setup:
+
+ mov pc, lr
+
/*
*************************************************************************
*
bl cpu_init_crit
#endif
-/* Set stackpointer in internal RAM to call board_init_f */
-call_board_init_f:
- ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
- bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
- ldr r0,=0x00000000
- bl board_init_f
+ bl _main
/*------------------------------------------------------------------------------*/
mov r5, r1 /* save addr of gd */
mov r6, r2 /* save addr of destination */
- /* Set up the stack */
-stack_setup:
- mov sp, r4
-
adr r0, _start
cmp r0, r6
moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
- beq clear_bss /* skip relocation */
+ beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */
blo fixloop
#endif
-clear_bss:
-#ifndef CONFIG_SPL_BUILD
- ldr r0, _bss_start_ofs
- ldr r1, _bss_end_ofs
- mov r4, r6 /* reloc addr */
- add r0, r0, r4
- add r1, r1, r4
- mov r2, #0x00000000 /* clear */
-
-clbss_l:cmp r0, r1 /* clear loop... */
- bhs clbss_e /* if reached end of bss, exit */
- str r2, [r0]
- add r0, r0, #4
- b clbss_l
-clbss_e:
-
- bl coloured_LED_init
- bl red_led_on
-#endif
-
-/*
- * We are done. Do not return, instead branch to second part of board
- * initialization, now running from RAM.
- */
-#ifdef CONFIG_NAND_SPL
- ldr r0, _nand_boot_ofs
- mov pc, r0
+relocate_done:
-_nand_boot_ofs:
- .word nand_boot
-#else
- ldr r0, _board_init_r_ofs
- adr r1, _start
- add lr, r0, r1
- add lr, lr, r9
- /* setup parameters for board_init_r */
- mov r0, r5 /* gd_t */
- mov r1, r6 /* dest_addr */
- /* jump to it ... */
mov pc, lr
-_board_init_r_ofs:
- .word board_init_r - _start
-#endif
-
_rel_dyn_start_ofs:
.word __rel_dyn_start - _start
_rel_dyn_end_ofs:
_dynsym_start_ofs:
.word __dynsym_start - _start
+ .globl c_runtime_cpu_setup
+c_runtime_cpu_setup:
+
+ mov pc, lr
+
/*
*************************************************************************
*
#include <config.h>
#include <version.h>
-#if defined(CONFIG_OMAP1510)
-#include <./configs/omap1510.h>
-#endif
-
/*
*************************************************************************
*
bl cpu_init_crit
#endif
-/* Set stackpointer in internal RAM to call board_init_f */
-call_board_init_f:
- ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
- bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
- ldr r0,=0x00000000
- bl board_init_f
+ bl _main
/*------------------------------------------------------------------------------*/
mov r5, r1 /* save addr of gd */
mov r6, r2 /* save addr of destination */
- /* Set up the stack */
-stack_setup:
- mov sp, r4
-
adr r0, _start
cmp r0, r6
moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
- beq clear_bss /* skip relocation */
+ beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */
blo fixloop
#endif
-clear_bss:
-#ifndef CONFIG_SPL_BUILD
- ldr r0, _bss_start_ofs
- ldr r1, _bss_end_ofs
- mov r4, r6 /* reloc addr */
- add r0, r0, r4
- add r1, r1, r4
- mov r2, #0x00000000 /* clear */
-
-clbss_l:cmp r0, r1 /* clear loop... */
- bhs clbss_e /* if reached end of bss, exit */
- str r2, [r0]
- add r0, r0, #4
- b clbss_l
-clbss_e:
-
- bl coloured_LED_init
- bl red_led_on
-#endif
-
-/*
- * We are done. Do not return, instead branch to second part of board
- * initialization, now running from RAM.
- */
-#ifdef CONFIG_NAND_SPL
- ldr r0, _nand_boot_ofs
- mov pc, r0
+relocate_done:
-_nand_boot_ofs:
- .word nand_boot
-#else
- ldr r0, _board_init_r_ofs
- adr r1, _start
- add lr, r0, r1
- add lr, lr, r9
- /* setup parameters for board_init_r */
- mov r0, r5 /* gd_t */
- mov r1, r6 /* dest_addr */
- /* jump to it ... */
mov pc, lr
-_board_init_r_ofs:
- .word board_init_r - _start
-#endif
-
_rel_dyn_start_ofs:
.word __rel_dyn_start - _start
_rel_dyn_end_ofs:
_dynsym_start_ofs:
.word __dynsym_start - _start
+ .globl c_runtime_cpu_setup
+c_runtime_cpu_setup:
+
+ mov pc, lr
+
/*
*************************************************************************
*
}
#endif
+#if defined(CONFIG_USB_OHCI_NEW) || defined(CONFIG_USB_EHCI)
+void at91_uhp_hw_init(void)
+{
+ /* Enable VBus on UHP ports */
+ at91_set_pio_output(AT91_PIO_PORTD, 18, 0); /* port A */
+ at91_set_pio_output(AT91_PIO_PORTD, 19, 0); /* port B */
+#if defined(CONFIG_USB_OHCI_NEW)
+ /* port C is OHCI only */
+ at91_set_pio_output(AT91_PIO_PORTD, 20, 0); /* port C */
+#endif
+}
+#endif
+
#ifdef CONFIG_MACB
void at91_macb_hw_init(void)
{
void reset_cpu(unsigned long a)
{
struct davinci_timer *const wdttimer =
- (struct davinci_timer *)DAVINCI_TIMER1_BASE;
+ (struct davinci_timer *)DAVINCI_WDOG_BASE;
writel(0x08, &wdttimer->tgcr);
writel(readl(&wdttimer->tgcr) | 0x03, &wdttimer->tgcr);
writel(0, &wdttimer->tim12);
#define MPP_CTRL(i) (KW_MPP_BASE + (i* 4))
#define MPP_NR_REGS (1 + MPP_MAX/8)
-void kirkwood_mpp_conf(u32 *mpp_list, u32 *mpp_save)
+void kirkwood_mpp_conf(const u32 *mpp_list, u32 *mpp_save)
{
u32 mpp_ctrl[MPP_NR_REGS];
unsigned int variant_mask;
}
#define MUX_CONFIG_BOOTMODE_PAD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
-const iomux_cfg_t iomux_boot[] = {
+static const iomux_cfg_t iomux_boot[] = {
MX28_PAD_LCD_D00__GPIO_1_0 | MUX_CONFIG_BOOTMODE_PAD,
MX28_PAD_LCD_D01__GPIO_1_1 | MUX_CONFIG_BOOTMODE_PAD,
MX28_PAD_LCD_D02__GPIO_1_2 | MUX_CONFIG_BOOTMODE_PAD,
MX28_PAD_LCD_D05__GPIO_1_5 | MUX_CONFIG_BOOTMODE_PAD,
};
-uint8_t mxs_get_bootmode_index(void)
+static uint8_t mxs_get_bootmode_index(void)
{
uint8_t bootmode = 0;
int i;
#include "mxs_init.h"
-static uint32_t mx28_dram_vals[] = {
+static uint32_t dram_vals[] = {
+/*
+ * i.MX28 DDR2 at 200MHz
+ */
+#if defined(CONFIG_MX28)
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x06120612, 0x04320432, 0x04320432, 0x00040004,
0x00040004, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00010001
+#else
+#error Unsupported memory initialization
+#endif
};
void __mxs_adjust_memory_params(uint32_t *dram_vals)
void mxs_adjust_memory_params(uint32_t *dram_vals)
__attribute__((weak, alias("__mxs_adjust_memory_params")));
-void init_mx28_200mhz_ddr2(void)
+static void initialize_dram_values(void)
{
int i;
- mxs_adjust_memory_params(mx28_dram_vals);
+ mxs_adjust_memory_params(dram_vals);
- for (i = 0; i < ARRAY_SIZE(mx28_dram_vals); i++)
- writel(mx28_dram_vals[i], MXS_DRAM_BASE + (4 * i));
+ for (i = 0; i < ARRAY_SIZE(dram_vals); i++)
+ writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
}
-void mxs_mem_init_clock(void)
+static void mxs_mem_init_clock(void)
{
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
early_delay(10000);
}
-void mxs_mem_setup_cpu_and_hbus(void)
+static void mxs_mem_setup_cpu_and_hbus(void)
{
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
early_delay(15000);
}
-void mxs_mem_setup_vdda(void)
+static void mxs_mem_setup_vdda(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
&power_regs->hw_power_vddactrl);
}
-void mxs_mem_setup_vddd(void)
-{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
-
- writel((0x1c << POWER_VDDDCTRL_TRG_OFFSET) |
- (0x7 << POWER_VDDDCTRL_BO_OFFSET_OFFSET) |
- POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW,
- &power_regs->hw_power_vdddctrl);
-}
-
uint32_t mxs_mem_get_size(void)
{
uint32_t sz, da;
/* Clear START bit from DRAM_CTL16 */
clrbits_le32(MXS_DRAM_BASE + 0x40, 1);
- init_mx28_200mhz_ddr2();
+ initialize_dram_values();
/* Clear SREFRESH bit from DRAM_CTL17 */
clrbits_le32(MXS_DRAM_BASE + 0x44, 1);
while (!(readl(MXS_DRAM_BASE + 0xe8) & (1 << 20)))
;
- mxs_mem_setup_vddd();
-
early_delay(10000);
mxs_mem_setup_cpu_and_hbus();
#include "mxs_init.h"
-void mxs_power_clock2xtal(void)
+static void mxs_power_clock2xtal(void)
{
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
&clkctrl_regs->hw_clkctrl_clkseq_set);
}
-void mxs_power_clock2pll(void)
+static void mxs_power_clock2pll(void)
{
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
CLKCTRL_CLKSEQ_BYPASS_CPU);
}
-void mxs_power_clear_auto_restart(void)
+static void mxs_power_clear_auto_restart(void)
{
struct mxs_rtc_regs *rtc_regs =
(struct mxs_rtc_regs *)MXS_RTC_BASE;
;
}
-void mxs_power_set_linreg(void)
+static void mxs_power_set_linreg(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW);
}
-int mxs_get_batt_volt(void)
+static int mxs_get_batt_volt(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
return volt;
}
-int mxs_is_batt_ready(void)
+static int mxs_is_batt_ready(void)
{
return (mxs_get_batt_volt() >= 3600);
}
-int mxs_is_batt_good(void)
+static int mxs_is_batt_good(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
return 0;
}
-void mxs_power_setup_5v_detect(void)
+static void mxs_power_setup_5v_detect(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
POWER_5VCTRL_PWRUP_VBUS_CMPS);
}
-void mxs_src_power_init(void)
+static void mxs_src_power_init(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
}
-void mxs_power_init_4p2_params(void)
+static void mxs_power_init_4p2_params(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
}
-void mxs_enable_4p2_dcdc_input(int xfer)
+static void mxs_enable_4p2_dcdc_input(int xfer)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
POWER_CTRL_ENIRQ_VDD5V_DROOP);
}
-void mxs_power_init_4p2_regulator(void)
+static void mxs_power_init_4p2_regulator(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
}
-void mxs_power_init_dcdc_4p2_source(void)
+static void mxs_power_init_dcdc_4p2_source(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
}
}
-void mxs_power_enable_4p2(void)
+static void mxs_power_enable_4p2(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
&power_regs->hw_power_charge_clr);
}
-void mxs_boot_valid_5v(void)
+static void mxs_boot_valid_5v(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
mxs_power_enable_4p2();
}
-void mxs_powerdown(void)
+static void mxs_powerdown(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
&power_regs->hw_power_reset);
}
-void mxs_batt_boot(void)
+static void mxs_batt_boot(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
}
-void mxs_handle_5v_conflict(void)
+static void mxs_handle_5v_conflict(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
}
}
-void mxs_5v_boot(void)
+static void mxs_5v_boot(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
mxs_handle_5v_conflict();
}
-void mxs_init_batt_bo(void)
+static void mxs_init_batt_bo(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
}
-void mxs_switch_vddd_to_dcdc_source(void)
+static void mxs_switch_vddd_to_dcdc_source(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
POWER_VDDDCTRL_DISABLE_STEPPING);
}
-void mxs_power_configure_power_source(void)
+static void mxs_power_configure_power_source(void)
{
int batt_ready, batt_good;
struct mxs_power_regs *power_regs =
mxs_switch_vddd_to_dcdc_source();
}
-void mxs_enable_output_rail_protection(void)
+static void mxs_enable_output_rail_protection(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
POWER_VDDIOCTRL_PWDN_BRNOUT);
}
-int mxs_get_vddio_power_source_off(void)
+static int mxs_get_vddio_power_source_off(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
}
-int mxs_get_vddd_power_source_off(void)
+static int mxs_get_vddd_power_source_off(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
return 0;
}
-void mxs_power_set_vddio(uint32_t new_target, uint32_t new_brownout)
+struct mxs_vddx_cfg {
+ uint32_t *reg;
+ uint8_t step_mV;
+ uint16_t lowest_mV;
+ int (*powered_by_linreg)(void);
+ uint32_t trg_mask;
+ uint32_t bo_irq;
+ uint32_t bo_enirq;
+ uint32_t bo_offset_mask;
+ uint32_t bo_offset_offset;
+};
+
+static const struct mxs_vddx_cfg mxs_vddio_cfg = {
+ .reg = &(((struct mxs_power_regs *)MXS_POWER_BASE)->
+ hw_power_vddioctrl),
+ .step_mV = 50,
+ .lowest_mV = 2800,
+ .powered_by_linreg = mxs_get_vddio_power_source_off,
+ .trg_mask = POWER_VDDIOCTRL_TRG_MASK,
+ .bo_irq = POWER_CTRL_VDDIO_BO_IRQ,
+ .bo_enirq = POWER_CTRL_ENIRQ_VDDIO_BO,
+ .bo_offset_mask = POWER_VDDIOCTRL_BO_OFFSET_MASK,
+ .bo_offset_offset = POWER_VDDIOCTRL_BO_OFFSET_OFFSET,
+};
+
+static const struct mxs_vddx_cfg mxs_vddd_cfg = {
+ .reg = &(((struct mxs_power_regs *)MXS_POWER_BASE)->
+ hw_power_vdddctrl),
+ .step_mV = 25,
+ .lowest_mV = 800,
+ .powered_by_linreg = mxs_get_vddd_power_source_off,
+ .trg_mask = POWER_VDDDCTRL_TRG_MASK,
+ .bo_irq = POWER_CTRL_VDDD_BO_IRQ,
+ .bo_enirq = POWER_CTRL_ENIRQ_VDDD_BO,
+ .bo_offset_mask = POWER_VDDDCTRL_BO_OFFSET_MASK,
+ .bo_offset_offset = POWER_VDDDCTRL_BO_OFFSET_OFFSET,
+};
+
+static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg,
+ uint32_t new_target, uint32_t new_brownout)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t cur_target, diff, bo_int = 0;
uint32_t powered_by_linreg = 0;
+ int adjust_up, tmp;
- new_brownout = (new_target - new_brownout + 25) / 50;
+ new_brownout = DIV_ROUND(new_target - new_brownout, cfg->step_mV);
- cur_target = readl(&power_regs->hw_power_vddioctrl);
- cur_target &= POWER_VDDIOCTRL_TRG_MASK;
- cur_target *= 50; /* 50 mV step*/
- cur_target += 2800; /* 2800 mV lowest */
+ cur_target = readl(cfg->reg);
+ cur_target &= cfg->trg_mask;
+ cur_target *= cfg->step_mV;
+ cur_target += cfg->lowest_mV;
- powered_by_linreg = mxs_get_vddio_power_source_off();
- if (new_target > cur_target) {
+ adjust_up = new_target > cur_target;
+ powered_by_linreg = cfg->powered_by_linreg();
+ if (adjust_up) {
if (powered_by_linreg) {
- bo_int = readl(&power_regs->hw_power_vddioctrl);
- clrbits_le32(&power_regs->hw_power_vddioctrl,
- POWER_CTRL_ENIRQ_VDDIO_BO);
+ bo_int = readl(cfg->reg);
+ clrbits_le32(cfg->reg, cfg->bo_enirq);
}
+ setbits_le32(cfg->reg, cfg->bo_offset_mask);
+ }
- setbits_le32(&power_regs->hw_power_vddioctrl,
- POWER_VDDIOCTRL_BO_OFFSET_MASK);
- do {
- if (new_target - cur_target > 100)
+ do {
+ if (abs(new_target - cur_target) > 100) {
+ if (adjust_up)
diff = cur_target + 100;
else
- diff = new_target;
-
- diff -= 2800;
- diff /= 50;
-
- clrsetbits_le32(&power_regs->hw_power_vddioctrl,
- POWER_VDDIOCTRL_TRG_MASK, diff);
-
- if (powered_by_linreg ||
- (readl(&power_regs->hw_power_sts) &
- POWER_STS_VDD5V_GT_VDDIO))
- early_delay(500);
- else {
- while (!(readl(&power_regs->hw_power_sts) &
- POWER_STS_DC_OK))
- ;
-
- }
-
- cur_target = readl(&power_regs->hw_power_vddioctrl);
- cur_target &= POWER_VDDIOCTRL_TRG_MASK;
- cur_target *= 50; /* 50 mV step*/
- cur_target += 2800; /* 2800 mV lowest */
- } while (new_target > cur_target);
-
- if (powered_by_linreg) {
- writel(POWER_CTRL_VDDIO_BO_IRQ,
- &power_regs->hw_power_ctrl_clr);
- if (bo_int & POWER_CTRL_ENIRQ_VDDIO_BO)
- setbits_le32(&power_regs->hw_power_vddioctrl,
- POWER_CTRL_ENIRQ_VDDIO_BO);
- }
- } else {
- do {
- if (cur_target - new_target > 100)
diff = cur_target - 100;
- else
- diff = new_target;
-
- diff -= 2800;
- diff /= 50;
-
- clrsetbits_le32(&power_regs->hw_power_vddioctrl,
- POWER_VDDIOCTRL_TRG_MASK, diff);
-
- if (powered_by_linreg ||
- (readl(&power_regs->hw_power_sts) &
- POWER_STS_VDD5V_GT_VDDIO))
- early_delay(500);
- else {
- while (!(readl(&power_regs->hw_power_sts) &
- POWER_STS_DC_OK))
- ;
-
- }
-
- cur_target = readl(&power_regs->hw_power_vddioctrl);
- cur_target &= POWER_VDDIOCTRL_TRG_MASK;
- cur_target *= 50; /* 50 mV step*/
- cur_target += 2800; /* 2800 mV lowest */
- } while (new_target < cur_target);
- }
-
- clrsetbits_le32(&power_regs->hw_power_vddioctrl,
- POWER_VDDIOCTRL_BO_OFFSET_MASK,
- new_brownout << POWER_VDDIOCTRL_BO_OFFSET_OFFSET);
-}
-
-void mxs_power_set_vddd(uint32_t new_target, uint32_t new_brownout)
-{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
- uint32_t cur_target, diff, bo_int = 0;
- uint32_t powered_by_linreg = 0;
-
- new_brownout = (new_target - new_brownout + 12) / 25;
-
- cur_target = readl(&power_regs->hw_power_vdddctrl);
- cur_target &= POWER_VDDDCTRL_TRG_MASK;
- cur_target *= 25; /* 25 mV step*/
- cur_target += 800; /* 800 mV lowest */
-
- powered_by_linreg = mxs_get_vddd_power_source_off();
- if (new_target > cur_target) {
- if (powered_by_linreg) {
- bo_int = readl(&power_regs->hw_power_vdddctrl);
- clrbits_le32(&power_regs->hw_power_vdddctrl,
- POWER_CTRL_ENIRQ_VDDD_BO);
+ } else {
+ diff = new_target;
}
- setbits_le32(&power_regs->hw_power_vdddctrl,
- POWER_VDDDCTRL_BO_OFFSET_MASK);
-
- do {
- if (new_target - cur_target > 100)
- diff = cur_target + 100;
- else
- diff = new_target;
-
- diff -= 800;
- diff /= 25;
-
- clrsetbits_le32(&power_regs->hw_power_vdddctrl,
- POWER_VDDDCTRL_TRG_MASK, diff);
+ diff -= cfg->lowest_mV;
+ diff /= cfg->step_mV;
- if (powered_by_linreg ||
- (readl(&power_regs->hw_power_sts) &
- POWER_STS_VDD5V_GT_VDDIO))
- early_delay(500);
- else {
- while (!(readl(&power_regs->hw_power_sts) &
- POWER_STS_DC_OK))
- ;
+ clrsetbits_le32(cfg->reg, cfg->trg_mask, diff);
+ if (powered_by_linreg ||
+ (readl(&power_regs->hw_power_sts) &
+ POWER_STS_VDD5V_GT_VDDIO))
+ early_delay(500);
+ else {
+ for (;;) {
+ tmp = readl(&power_regs->hw_power_sts);
+ if (tmp & POWER_STS_DC_OK)
+ break;
}
-
- cur_target = readl(&power_regs->hw_power_vdddctrl);
- cur_target &= POWER_VDDDCTRL_TRG_MASK;
- cur_target *= 25; /* 25 mV step*/
- cur_target += 800; /* 800 mV lowest */
- } while (new_target > cur_target);
-
- if (powered_by_linreg) {
- writel(POWER_CTRL_VDDD_BO_IRQ,
- &power_regs->hw_power_ctrl_clr);
- if (bo_int & POWER_CTRL_ENIRQ_VDDD_BO)
- setbits_le32(&power_regs->hw_power_vdddctrl,
- POWER_CTRL_ENIRQ_VDDD_BO);
}
- } else {
- do {
- if (cur_target - new_target > 100)
- diff = cur_target - 100;
- else
- diff = new_target;
- diff -= 800;
- diff /= 25;
+ cur_target = readl(cfg->reg);
+ cur_target &= cfg->trg_mask;
+ cur_target *= cfg->step_mV;
+ cur_target += cfg->lowest_mV;
+ } while (new_target > cur_target);
- clrsetbits_le32(&power_regs->hw_power_vdddctrl,
- POWER_VDDDCTRL_TRG_MASK, diff);
-
- if (powered_by_linreg ||
- (readl(&power_regs->hw_power_sts) &
- POWER_STS_VDD5V_GT_VDDIO))
- early_delay(500);
- else {
- while (!(readl(&power_regs->hw_power_sts) &
- POWER_STS_DC_OK))
- ;
-
- }
-
- cur_target = readl(&power_regs->hw_power_vdddctrl);
- cur_target &= POWER_VDDDCTRL_TRG_MASK;
- cur_target *= 25; /* 25 mV step*/
- cur_target += 800; /* 800 mV lowest */
- } while (new_target < cur_target);
+ if (adjust_up && powered_by_linreg) {
+ writel(cfg->bo_irq, &power_regs->hw_power_ctrl_clr);
+ if (bo_int & cfg->bo_enirq)
+ setbits_le32(cfg->reg, cfg->bo_enirq);
}
- clrsetbits_le32(&power_regs->hw_power_vdddctrl,
- POWER_VDDDCTRL_BO_OFFSET_MASK,
- new_brownout << POWER_VDDDCTRL_BO_OFFSET_OFFSET);
+ clrsetbits_le32(cfg->reg, cfg->bo_offset_mask,
+ new_brownout << cfg->bo_offset_offset);
}
-void mxs_setup_batt_detect(void)
+static void mxs_setup_batt_detect(void)
{
mxs_lradc_init();
mxs_lradc_enable_batt_measurement();
mxs_power_configure_power_source();
mxs_enable_output_rail_protection();
- mxs_power_set_vddio(3300, 3150);
-
- mxs_power_set_vddd(1350, 1200);
+ mxs_power_set_vddx(&mxs_vddio_cfg, 3300, 3150);
+ mxs_power_set_vddx(&mxs_vddd_cfg, 1500, 1000);
writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ |
#include <common.h>
#include <version.h>
-#if defined(CONFIG_OMAP1610)
-#include <./configs/omap1510.h>
-#elif defined(CONFIG_OMAP730)
-#include <./configs/omap730.h>
-#endif
-
/*
*************************************************************************
*
bl cpu_init_crit
#endif
-/* Set stackpointer in internal RAM to call board_init_f */
-call_board_init_f:
-#ifdef CONFIG_NAND_SPL /* deprecated, use instead CONFIG_SPL_BUILD */
- ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
-#else
-#ifdef CONFIG_SPL_BUILD
- ldr sp, =(CONFIG_SPL_STACK)
-#else
- ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
-#endif
-#endif
- bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
- ldr r0,=0x00000000
- bl board_init_f
+ bl _main
/*------------------------------------------------------------------------------*/
mov r5, r1 /* save addr of gd */
mov r6, r2 /* save addr of destination */
- /* Set up the stack */
-stack_setup:
- mov sp, r4
-
adr r0, _start
sub r9, r6, r0 /* r9 <- relocation offset */
cmp r0, r6
- moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
- beq clear_bss /* skip relocation */
+ moveq r9, #0 /* no relocation. offset(r9) = 0 */
+ beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy loop */
ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */
blo fixloop
#endif
-clear_bss:
-#ifdef CONFIG_SPL_BUILD
- /* No relocation for SPL */
- ldr r0, =__bss_start
- ldr r1, =__bss_end__
-#else
- ldr r0, _bss_start_ofs
- ldr r1, _bss_end_ofs
- mov r4, r6 /* reloc addr */
- add r0, r0, r4
- add r1, r1, r4
-#endif
- mov r2, #0x00000000 /* clear */
-
-clbss_l:cmp r0, r1 /* clear loop... */
- bhs clbss_e /* if reached end of bss, exit */
- str r2, [r0]
- add r0, r0, #4
- b clbss_l
-clbss_e:
-
-#ifndef CONFIG_SPL_BUILD
- bl coloured_LED_init
- bl red_led_on
-#endif
-
-/*
- * We are done. Do not return, instead branch to second part of board
- * initialization, now running from RAM.
- */
-#ifdef CONFIG_NAND_SPL
- ldr r0, _nand_boot_ofs
- mov pc, r0
+relocate_done:
-_nand_boot_ofs:
- .word nand_boot
-#else
- ldr r0, _board_init_r_ofs
- ldr r1, _TEXT_BASE
- add lr, r0, r1
- add lr, lr, r9
- /* setup parameters for board_init_r */
- mov r0, r5 /* gd_t */
- mov r1, r6 /* dest_addr */
- /* jump to it ... */
- mov pc, lr
-
-_board_init_r_ofs:
- .word board_init_r - _start
-#endif
+ bx lr
_rel_dyn_start_ofs:
.word __rel_dyn_start - _start
.word __rel_dyn_end - _start
_dynsym_start_ofs:
.word __dynsym_start - _start
+
#endif
+ .globl c_runtime_cpu_setup
+c_runtime_cpu_setup:
+
+ bx lr
+
/*
*************************************************************************
*
bl cpu_init_crit
#endif
-/* Set stackpointer in internal RAM to call board_init_f */
-call_board_init_f:
- ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
- bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
- ldr r0,=0x00000000
- bl board_init_f
+ bl _main
/*------------------------------------------------------------------------------*/
mov r5, r1 /* save addr of gd */
mov r6, r2 /* save addr of destination */
- /* Set up the stack */
-stack_setup:
- mov sp, r4
-
adr r0, _start
cmp r0, r6
moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
- beq clear_bss /* skip relocation */
+ beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */
blo fixloop
#endif
-clear_bss:
-#ifndef CONFIG_SPL_BUILD
- ldr r0, _bss_start_ofs
- ldr r1, _bss_end_ofs
- mov r4, r6 /* reloc addr */
- add r0, r0, r4
- add r1, r1, r4
- mov r2, #0x00000000 /* clear */
-
-clbss_l:cmp r0, r1 /* clear loop... */
- bhs clbss_e /* if reached end of bss, exit */
- str r2, [r0]
- add r0, r0, #4
- b clbss_l
-clbss_e:
-#endif
-
-/*
- * We are done. Do not return, instead branch to second part of board
- * initialization, now running from RAM.
- */
-#ifdef CONFIG_NAND_SPL
- ldr pc, _nand_boot
+relocate_done:
-_nand_boot: .word nand_boot
-#else
- ldr r0, _board_init_r_ofs
- adr r1, _start
- add lr, r0, r1
- add lr, lr, r9
- /* setup parameters for board_init_r */
- mov r0, r5 /* gd_t */
- mov r1, r6 /* dest_addr */
- /* jump to it ... */
mov pc, lr
-_board_init_r_ofs:
- .word board_init_r - _start
-#endif
-
_rel_dyn_start_ofs:
.word __rel_dyn_start - _start
_rel_dyn_end_ofs:
_dynsym_start_ofs:
.word __dynsym_start - _start
+ .globl c_runtime_cpu_setup
+c_runtime_cpu_setup:
+
+ mov pc, lr
+
/*
*************************************************************************
*
bl cpu_init_crit
#endif
-/* Set stackpointer in internal RAM to call board_init_f */
-call_board_init_f:
- ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
- bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
- ldr r0,=0x00000000
- bl board_init_f
+ bl _main
/*------------------------------------------------------------------------------*/
mov r5, r1 /* save addr of gd */
mov r6, r2 /* save addr of destination */
- /* Set up the stack */
-stack_setup:
- mov sp, r4
-
adr r0, _start
cmp r0, r6
moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
- beq clear_bss /* skip relocation */
+ beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */
blo fixloop
#endif
-clear_bss:
-#ifndef CONFIG_SPL_BUILD
- ldr r0, _bss_start_ofs
- ldr r1, _bss_end_ofs
- mov r4, r6 /* reloc addr */
- add r0, r0, r4
- add r1, r1, r4
- mov r2, #0x00000000 /* clear */
-
-clbss_l:cmp r0, r1 /* clear loop... */
- bhs clbss_e /* if reached end of bss, exit */
- str r2, [r0]
- add r0, r0, #4
- b clbss_l
-clbss_e:
-
- bl coloured_LED_init
- bl red_led_on
-#endif
+relocate_done:
-/*
- * We are done. Do not return, instead branch to second part of board
- * initialization, now running from RAM.
- */
-#ifdef CONFIG_NAND_SPL
- ldr r0, _nand_boot_ofs
- mov pc, r0
-
-_nand_boot_ofs:
- .word nand_boot
-#else
- ldr r0, _board_init_r_ofs
- adr r1, _start
- add lr, r0, r1
- add lr, lr, r9
- /* setup parameters for board_init_r */
- mov r0, r5 /* gd_t */
- mov r1, r6 /* dest_addr */
- /* jump to it ... */
- mov pc, lr
-
-_board_init_r_ofs:
- .word board_init_r - _start
-#endif
+ bx lr
_rel_dyn_start_ofs:
.word __rel_dyn_start - _start
_dynsym_start_ofs:
.word __dynsym_start - _start
+ .globl c_runtime_cpu_setup
+c_runtime_cpu_setup:
+
+ mov pc, lr
+
/*
*************************************************************************
*
COBJS += clock.o
COBJS += sys_info.o
+COBJS += mem.o
COBJS += ddr.o
COBJS += emif4.o
COBJS += board.o
COBJS += mux.o
+COBJS-$(CONFIG_NAND_OMAP_GPMC) += elm.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(COBJS-y) $(SOBJS))
#include <asm/arch/ddr_defs.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
+#include <asm/arch/mem.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
;
#endif /* CONFIG_SERIAL6 */
+ /* GPMC */
+ writel(PRCM_MOD_EN, &cmper->gpmcclkctrl);
+ while (readl(&cmper->gpmcclkctrl) != PRCM_MOD_EN)
+ ;
+
+ /* ELM */
+ writel(PRCM_MOD_EN, &cmper->elmclkctrl);
+ while (readl(&cmper->elmclkctrl) != PRCM_MOD_EN)
+ ;
+
/* MMC0*/
writel(PRCM_MOD_EN, &cmper->mmc0clkctrl);
while (readl(&cmper->mmc0clkctrl) != PRCM_MOD_EN)
--- /dev/null
+/*
+ * (C) Copyright 2010-2011 Texas Instruments, <www.ti.com>
+ * Mansoor Ahamed <mansoor.ahamed@ti.com>
+ *
+ * BCH Error Location Module (ELM) support.
+ *
+ * NOTE:
+ * 1. Supports only continuous mode. Dont see need for page mode in uboot
+ * 2. Supports only syndrome polynomial 0. i.e. poly local variable is
+ * always set to ELM_DEFAULT_POLY. Dont see need for other polynomial
+ * sets in uboot
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/omap_gpmc.h>
+#include <asm/arch/elm.h>
+
+#define ELM_DEFAULT_POLY (0)
+
+struct elm *elm_cfg;
+
+/**
+ * elm_load_syndromes - Load BCH syndromes based on nibble selection
+ * @syndrome: BCH syndrome
+ * @nibbles:
+ * @poly: Syndrome Polynomial set to use
+ *
+ * Load BCH syndromes based on nibble selection
+ */
+static void elm_load_syndromes(u8 *syndrome, u32 nibbles, u8 poly)
+{
+ u32 *ptr;
+ u32 val;
+
+ /* reg 0 */
+ ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[0];
+ val = syndrome[0] | (syndrome[1] << 8) | (syndrome[2] << 16) |
+ (syndrome[3] << 24);
+ writel(val, ptr);
+ /* reg 1 */
+ ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[1];
+ val = syndrome[4] | (syndrome[5] << 8) | (syndrome[6] << 16) |
+ (syndrome[7] << 24);
+ writel(val, ptr);
+
+ /* BCH 8-bit with 26 nibbles (4*8=32) */
+ if (nibbles > 13) {
+ /* reg 2 */
+ ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[2];
+ val = syndrome[8] | (syndrome[9] << 8) | (syndrome[10] << 16) |
+ (syndrome[11] << 24);
+ writel(val, ptr);
+ /* reg 3 */
+ ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[3];
+ val = syndrome[12] | (syndrome[13] << 8) |
+ (syndrome[14] << 16) | (syndrome[15] << 24);
+ writel(val, ptr);
+ }
+
+ /* BCH 16-bit with 52 nibbles (7*8=56) */
+ if (nibbles > 26) {
+ /* reg 4 */
+ ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[4];
+ val = syndrome[16] | (syndrome[17] << 8) |
+ (syndrome[18] << 16) | (syndrome[19] << 24);
+ writel(val, ptr);
+
+ /* reg 5 */
+ ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[5];
+ val = syndrome[20] | (syndrome[21] << 8) |
+ (syndrome[22] << 16) | (syndrome[23] << 24);
+ writel(val, ptr);
+
+ /* reg 6 */
+ ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[6];
+ val = syndrome[24] | (syndrome[25] << 8) |
+ (syndrome[26] << 16) | (syndrome[27] << 24);
+ writel(val, ptr);
+ }
+}
+
+/**
+ * elm_check_errors - Check for BCH errors and return error locations
+ * @syndrome: BCH syndrome
+ * @nibbles:
+ * @error_count: Returns number of errrors in the syndrome
+ * @error_locations: Returns error locations (in decimal) in this array
+ *
+ * Check the provided syndrome for BCH errors and return error count
+ * and locations in the array passed. Returns -1 if error is not correctable,
+ * else returns 0
+ */
+int elm_check_error(u8 *syndrome, u32 nibbles, u32 *error_count,
+ u32 *error_locations)
+{
+ u8 poly = ELM_DEFAULT_POLY;
+ s8 i;
+ u32 location_status;
+
+ elm_load_syndromes(syndrome, nibbles, poly);
+
+ /* start processing */
+ writel((readl(&elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[6])
+ | ELM_SYNDROME_FRAGMENT_6_SYNDROME_VALID),
+ &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[6]);
+
+ /* wait for processing to complete */
+ while ((readl(&elm_cfg->irqstatus) & (0x1 << poly)) != 0x1)
+ ;
+ /* clear status */
+ writel((readl(&elm_cfg->irqstatus) | (0x1 << poly)),
+ &elm_cfg->irqstatus);
+
+ /* check if correctable */
+ location_status = readl(&elm_cfg->error_location[poly].location_status);
+ if (!(location_status & ELM_LOCATION_STATUS_ECC_CORRECTABLE_MASK))
+ return -1;
+
+ /* get error count */
+ *error_count = readl(&elm_cfg->error_location[poly].location_status) &
+ ELM_LOCATION_STATUS_ECC_NB_ERRORS_MASK;
+
+ for (i = 0; i < *error_count; i++) {
+ error_locations[i] =
+ readl(&elm_cfg->error_location[poly].error_location_x[i]);
+ }
+
+ return 0;
+}
+
+
+/**
+ * elm_config - Configure ELM module
+ * @level: 4 / 8 / 16 bit BCH
+ *
+ * Configure ELM module based on BCH level.
+ * Set mode as continuous mode.
+ * Currently we are using only syndrome 0 and syndromes 1 to 6 are not used.
+ * Also, the mode is set only for syndrome 0
+ */
+int elm_config(enum bch_level level)
+{
+ u32 val;
+ u8 poly = ELM_DEFAULT_POLY;
+ u32 buffer_size = 0x7FF;
+
+ /* config size and level */
+ val = (u32)(level) & ELM_LOCATION_CONFIG_ECC_BCH_LEVEL_MASK;
+ val |= ((buffer_size << ELM_LOCATION_CONFIG_ECC_SIZE_POS) &
+ ELM_LOCATION_CONFIG_ECC_SIZE_MASK);
+ writel(val, &elm_cfg->location_config);
+
+ /* config continous mode */
+ /* enable interrupt generation for syndrome polynomial set */
+ writel((readl(&elm_cfg->irqenable) | (0x1 << poly)),
+ &elm_cfg->irqenable);
+ /* set continuous mode for the syndrome polynomial set */
+ writel((readl(&elm_cfg->page_ctrl) & ~(0x1 << poly)),
+ &elm_cfg->page_ctrl);
+
+ return 0;
+}
+
+/**
+ * elm_reset - Do a soft reset of ELM
+ *
+ * Perform a soft reset of ELM and return after reset is done.
+ */
+void elm_reset(void)
+{
+ /* initiate reset */
+ writel((readl(&elm_cfg->sysconfig) | ELM_SYSCONFIG_SOFTRESET),
+ &elm_cfg->sysconfig);
+
+ /* wait for reset complete and normal operation */
+ while ((readl(&elm_cfg->sysstatus) & ELM_SYSSTATUS_RESETDONE) !=
+ ELM_SYSSTATUS_RESETDONE)
+ ;
+}
+
+/**
+ * elm_init - Initialize ELM module
+ *
+ * Initialize ELM support. Currently it does only base address init
+ * and ELM reset.
+ */
+void elm_init(void)
+{
+ elm_cfg = (struct elm *)ELM_BASE;
+ elm_reset();
+}
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ * Mansoor Ahamed <mansoor.ahamed@ti.com>
+ *
+ * Initial Code from:
+ * Manikandan Pillai <mani.pillai@ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/sys_proto.h>
+#include <command.h>
+
+struct gpmc *gpmc_cfg;
+
+#if defined(CONFIG_CMD_NAND)
+static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
+ M_NAND_GPMC_CONFIG1,
+ M_NAND_GPMC_CONFIG2,
+ M_NAND_GPMC_CONFIG3,
+ M_NAND_GPMC_CONFIG4,
+ M_NAND_GPMC_CONFIG5,
+ M_NAND_GPMC_CONFIG6, 0
+};
+#endif
+
+
+void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
+ u32 size)
+{
+ writel(0, &cs->config7);
+ sdelay(1000);
+ /* Delay for settling */
+ writel(gpmc_config[0], &cs->config1);
+ writel(gpmc_config[1], &cs->config2);
+ writel(gpmc_config[2], &cs->config3);
+ writel(gpmc_config[3], &cs->config4);
+ writel(gpmc_config[4], &cs->config5);
+ writel(gpmc_config[5], &cs->config6);
+ /* Enable the config */
+ writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) |
+ (1 << 6)), &cs->config7);
+ sdelay(2000);
+}
+
+/*****************************************************
+ * gpmc_init(): init gpmc bus
+ * Init GPMC for x16, MuxMode (SDRAM in x32).
+ * This code can only be executed from SRAM or SDRAM.
+ *****************************************************/
+void gpmc_init(void)
+{
+ /* putting a blanket check on GPMC based on ZeBu for now */
+ gpmc_cfg = (struct gpmc *)GPMC_BASE;
+
+#ifdef CONFIG_CMD_NAND
+ const u32 *gpmc_config = NULL;
+ u32 base = 0;
+ u32 size = 0;
+#endif
+ /* global settings */
+ writel(0x00000008, &gpmc_cfg->sysconfig);
+ writel(0x00000100, &gpmc_cfg->irqstatus);
+ writel(0x00000200, &gpmc_cfg->irqenable);
+ writel(0x00000012, &gpmc_cfg->config);
+ /*
+ * Disable the GPMC0 config set by ROM code
+ */
+ writel(0, &gpmc_cfg->cs[0].config7);
+ sdelay(1000);
+
+#ifdef CONFIG_CMD_NAND
+ gpmc_config = gpmc_m_nand;
+
+ base = PISMO1_NAND_BASE;
+ size = PISMO1_NAND_SIZE;
+ enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
+#endif
+}
v7_inval_tlb();
}
+void mmu_page_table_flush(unsigned long start, unsigned long stop)
+{
+ flush_dcache_range(start, stop);
+ v7_inval_tlb();
+}
+
/*
* Flush range from all levels of d-cache/unified-cache used:
* Affects the range [start, start + size - 1]
void flush_cache(unsigned long start, unsigned long size)
{
}
+
+void mmu_page_table_flush(unsigned long start, unsigned long stop)
+{
+}
+
#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
#ifndef CONFIG_SYS_ICACHE_OFF
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/clk.h>
-
-/* exynos4: return pll clock frequency */
-static unsigned long exynos4_get_pll_clk(int pllreg)
+#include <asm/arch/periph.h>
+
+/* Epll Clock division values to achive different frequency output */
+static struct set_epll_con_val exynos5_epll_div[] = {
+ { 192000000, 0, 48, 3, 1, 0 },
+ { 180000000, 0, 45, 3, 1, 0 },
+ { 73728000, 1, 73, 3, 3, 47710 },
+ { 67737600, 1, 90, 4, 3, 20762 },
+ { 49152000, 0, 49, 3, 3, 9961 },
+ { 45158400, 0, 45, 3, 3, 10381 },
+ { 180633600, 0, 45, 3, 1, 10381 }
+};
+
+/* exynos: return pll clock frequency */
+static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
{
- struct exynos4_clock *clk =
- (struct exynos4_clock *)samsung_get_base_clock();
- unsigned long r, m, p, s, k = 0, mask, fout;
+ unsigned long m, p, s = 0, mask, fout;
unsigned int freq;
-
- switch (pllreg) {
- case APLL:
- r = readl(&clk->apll_con0);
- break;
- case MPLL:
- r = readl(&clk->mpll_con0);
- break;
- case EPLL:
- r = readl(&clk->epll_con0);
- k = readl(&clk->epll_con1);
- break;
- case VPLL:
- r = readl(&clk->vpll_con0);
- k = readl(&clk->vpll_con1);
- break;
- default:
- printf("Unsupported PLL (%d)\n", pllreg);
- return 0;
- }
-
/*
* APLL_CON: MIDV [25:16]
* MPLL_CON: MIDV [25:16]
* EPLL_CON: MIDV [24:16]
* VPLL_CON: MIDV [24:16]
+ * BPLL_CON: MIDV [25:16]: Exynos5
*/
- if (pllreg == APLL || pllreg == MPLL)
+ if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL)
mask = 0x3ff;
else
mask = 0x1ff;
return fout;
}
+/* exynos4: return pll clock frequency */
+static unsigned long exynos4_get_pll_clk(int pllreg)
+{
+ struct exynos4_clock *clk =
+ (struct exynos4_clock *)samsung_get_base_clock();
+ unsigned long r, k = 0;
+
+ switch (pllreg) {
+ case APLL:
+ r = readl(&clk->apll_con0);
+ break;
+ case MPLL:
+ r = readl(&clk->mpll_con0);
+ break;
+ case EPLL:
+ r = readl(&clk->epll_con0);
+ k = readl(&clk->epll_con1);
+ break;
+ case VPLL:
+ r = readl(&clk->vpll_con0);
+ k = readl(&clk->vpll_con1);
+ break;
+ default:
+ printf("Unsupported PLL (%d)\n", pllreg);
+ return 0;
+ }
+
+ return exynos_get_pll_clk(pllreg, r, k);
+}
+
+/* exynos4x12: return pll clock frequency */
+static unsigned long exynos4x12_get_pll_clk(int pllreg)
+{
+ struct exynos4x12_clock *clk =
+ (struct exynos4x12_clock *)samsung_get_base_clock();
+ unsigned long r, k = 0;
+
+ switch (pllreg) {
+ case APLL:
+ r = readl(&clk->apll_con0);
+ break;
+ case MPLL:
+ r = readl(&clk->mpll_con0);
+ break;
+ case EPLL:
+ r = readl(&clk->epll_con0);
+ k = readl(&clk->epll_con1);
+ break;
+ case VPLL:
+ r = readl(&clk->vpll_con0);
+ k = readl(&clk->vpll_con1);
+ break;
+ default:
+ printf("Unsupported PLL (%d)\n", pllreg);
+ return 0;
+ }
+
+ return exynos_get_pll_clk(pllreg, r, k);
+}
+
/* exynos5: return pll clock frequency */
static unsigned long exynos5_get_pll_clk(int pllreg)
{
struct exynos5_clock *clk =
(struct exynos5_clock *)samsung_get_base_clock();
- unsigned long r, m, p, s, k = 0, mask, fout;
- unsigned int freq, pll_div2_sel, fout_sel;
+ unsigned long r, k = 0, fout;
+ unsigned int pll_div2_sel, fout_sel;
switch (pllreg) {
case APLL:
return 0;
}
- /*
- * APLL_CON: MIDV [25:16]
- * MPLL_CON: MIDV [25:16]
- * EPLL_CON: MIDV [24:16]
- * VPLL_CON: MIDV [24:16]
- * BPLL_CON: MIDV [25:16]
- */
- if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL)
- mask = 0x3ff;
- else
- mask = 0x1ff;
-
- m = (r >> 16) & mask;
-
- /* PDIV [13:8] */
- p = (r >> 8) & 0x3f;
- /* SDIV [2:0] */
- s = r & 0x7;
-
- freq = CONFIG_SYS_CLK_FREQ;
-
- if (pllreg == EPLL) {
- k = k & 0xffff;
- /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
- fout = (m + k / 65536) * (freq / (p * (1 << s)));
- } else if (pllreg == VPLL) {
- k = k & 0xfff;
- /* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */
- fout = (m + k / 1024) * (freq / (p * (1 << s)));
- } else {
- if (s < 1)
- s = 1;
- /* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */
- fout = m * (freq / (p * (1 << (s - 1))));
- }
+ fout = exynos_get_pll_clk(pllreg, r, k);
/* According to the user manual, in EVT1 MPLL and BPLL always gives
* 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/
return armclk;
}
+/* exynos4x12: return ARM clock frequency */
+static unsigned long exynos4x12_get_arm_clk(void)
+{
+ struct exynos4x12_clock *clk =
+ (struct exynos4x12_clock *)samsung_get_base_clock();
+ unsigned long div;
+ unsigned long armclk;
+ unsigned int core_ratio;
+ unsigned int core2_ratio;
+
+ div = readl(&clk->div_cpu0);
+
+ /* CORE_RATIO: [2:0], CORE2_RATIO: [30:28] */
+ core_ratio = (div >> 0) & 0x7;
+ core2_ratio = (div >> 28) & 0x7;
+
+ armclk = get_pll_clk(APLL) / (core_ratio + 1);
+ armclk /= (core2_ratio + 1);
+
+ return armclk;
+}
+
/* exynos5: return ARM clock frequency */
static unsigned long exynos5_get_arm_clk(void)
{
return pclk;
}
+/* exynos4x12: return pwm clock frequency */
+static unsigned long exynos4x12_get_pwm_clk(void)
+{
+ unsigned long pclk, sclk;
+ unsigned int ratio;
+
+ sclk = get_pll_clk(MPLL);
+ ratio = 8;
+
+ pclk = sclk / (ratio + 1);
+
+ return pclk;
+}
+
/* exynos5: return pwm clock frequency */
static unsigned long exynos5_get_pwm_clk(void)
{
return uclk;
}
+/* exynos4x12: return uart clock frequency */
+static unsigned long exynos4x12_get_uart_clk(int dev_index)
+{
+ struct exynos4x12_clock *clk =
+ (struct exynos4x12_clock *)samsung_get_base_clock();
+ unsigned long uclk, sclk;
+ unsigned int sel;
+ unsigned int ratio;
+
+ /*
+ * CLK_SRC_PERIL0
+ * UART0_SEL [3:0]
+ * UART1_SEL [7:4]
+ * UART2_SEL [8:11]
+ * UART3_SEL [12:15]
+ * UART4_SEL [16:19]
+ */
+ sel = readl(&clk->src_peril0);
+ sel = (sel >> (dev_index << 2)) & 0xf;
+
+ if (sel == 0x6)
+ sclk = get_pll_clk(MPLL);
+ else if (sel == 0x7)
+ sclk = get_pll_clk(EPLL);
+ else if (sel == 0x8)
+ sclk = get_pll_clk(VPLL);
+ else
+ return 0;
+
+ /*
+ * CLK_DIV_PERIL0
+ * UART0_RATIO [3:0]
+ * UART1_RATIO [7:4]
+ * UART2_RATIO [8:11]
+ * UART3_RATIO [12:15]
+ * UART4_RATIO [16:19]
+ */
+ ratio = readl(&clk->div_peril0);
+ ratio = (ratio >> (dev_index << 2)) & 0xf;
+
+ uclk = sclk / (ratio + 1);
+
+ return uclk;
+}
+
/* exynos5: return uart clock frequency */
static unsigned long exynos5_get_uart_clk(int dev_index)
{
return uclk;
}
+static unsigned long exynos4_get_mmc_clk(int dev_index)
+{
+ struct exynos4_clock *clk =
+ (struct exynos4_clock *)samsung_get_base_clock();
+ unsigned long uclk, sclk;
+ unsigned int sel, ratio, pre_ratio;
+ int shift;
+
+ sel = readl(&clk->src_fsys);
+ sel = (sel >> (dev_index << 2)) & 0xf;
+
+ if (sel == 0x6)
+ sclk = get_pll_clk(MPLL);
+ else if (sel == 0x7)
+ sclk = get_pll_clk(EPLL);
+ else if (sel == 0x8)
+ sclk = get_pll_clk(VPLL);
+ else
+ return 0;
+
+ switch (dev_index) {
+ case 0:
+ case 1:
+ ratio = readl(&clk->div_fsys1);
+ pre_ratio = readl(&clk->div_fsys1);
+ break;
+ case 2:
+ case 3:
+ ratio = readl(&clk->div_fsys2);
+ pre_ratio = readl(&clk->div_fsys2);
+ break;
+ case 4:
+ ratio = readl(&clk->div_fsys3);
+ pre_ratio = readl(&clk->div_fsys3);
+ break;
+ default:
+ return 0;
+ }
+
+ if (dev_index == 1 || dev_index == 3)
+ shift = 16;
+
+ ratio = (ratio >> shift) & 0xf;
+ pre_ratio = (pre_ratio >> (shift + 8)) & 0xff;
+ uclk = (sclk / (ratio + 1)) / (pre_ratio + 1);
+
+ return uclk;
+}
+
+static unsigned long exynos5_get_mmc_clk(int dev_index)
+{
+ struct exynos5_clock *clk =
+ (struct exynos5_clock *)samsung_get_base_clock();
+ unsigned long uclk, sclk;
+ unsigned int sel, ratio, pre_ratio;
+ int shift;
+
+ sel = readl(&clk->src_fsys);
+ sel = (sel >> (dev_index << 2)) & 0xf;
+
+ if (sel == 0x6)
+ sclk = get_pll_clk(MPLL);
+ else if (sel == 0x7)
+ sclk = get_pll_clk(EPLL);
+ else if (sel == 0x8)
+ sclk = get_pll_clk(VPLL);
+ else
+ return 0;
+
+ switch (dev_index) {
+ case 0:
+ case 1:
+ ratio = readl(&clk->div_fsys1);
+ pre_ratio = readl(&clk->div_fsys1);
+ break;
+ case 2:
+ case 3:
+ ratio = readl(&clk->div_fsys2);
+ pre_ratio = readl(&clk->div_fsys2);
+ break;
+ default:
+ return 0;
+ }
+
+ if (dev_index == 1 || dev_index == 3)
+ shift = 16;
+
+ ratio = (ratio >> shift) & 0xf;
+ pre_ratio = (pre_ratio >> (shift + 8)) & 0xff;
+ uclk = (sclk / (ratio + 1)) / (pre_ratio + 1);
+
+ return uclk;
+}
+
/* exynos4: set the mmc clock */
static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
{
unsigned int addr;
unsigned int val;
+ /*
+ * CLK_DIV_FSYS1
+ * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
+ * CLK_DIV_FSYS2
+ * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
+ * CLK_DIV_FSYS3
+ * MMC4_PRE_RATIO [15:8]
+ */
+ if (dev_index < 2) {
+ addr = (unsigned int)&clk->div_fsys1;
+ } else if (dev_index == 4) {
+ addr = (unsigned int)&clk->div_fsys3;
+ dev_index -= 4;
+ } else {
+ addr = (unsigned int)&clk->div_fsys2;
+ dev_index -= 2;
+ }
+
+ val = readl(addr);
+ val &= ~(0xff << ((dev_index << 4) + 8));
+ val |= (div & 0xff) << ((dev_index << 4) + 8);
+ writel(val, addr);
+}
+
+/* exynos4x12: set the mmc clock */
+static void exynos4x12_set_mmc_clk(int dev_index, unsigned int div)
+{
+ struct exynos4x12_clock *clk =
+ (struct exynos4x12_clock *)samsung_get_base_clock();
+ unsigned int addr;
+ unsigned int val;
+
/*
* CLK_DIV_FSYS1
* MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
*/
cfg = readl(&clk->src_disp1_0);
cfg &= ~(0xf);
- cfg |= 0x8;
+ cfg |= 0x6;
writel(cfg, &clk->src_disp1_0);
/*
return aclk_66;
}
+int exynos5_set_epll_clk(unsigned long rate)
+{
+ unsigned int epll_con, epll_con_k;
+ unsigned int i;
+ unsigned int lockcnt;
+ unsigned int start;
+ struct exynos5_clock *clk =
+ (struct exynos5_clock *)samsung_get_base_clock();
+
+ epll_con = readl(&clk->epll_con0);
+ epll_con &= ~((EPLL_CON0_LOCK_DET_EN_MASK <<
+ EPLL_CON0_LOCK_DET_EN_SHIFT) |
+ EPLL_CON0_MDIV_MASK << EPLL_CON0_MDIV_SHIFT |
+ EPLL_CON0_PDIV_MASK << EPLL_CON0_PDIV_SHIFT |
+ EPLL_CON0_SDIV_MASK << EPLL_CON0_SDIV_SHIFT);
+
+ for (i = 0; i < ARRAY_SIZE(exynos5_epll_div); i++) {
+ if (exynos5_epll_div[i].freq_out == rate)
+ break;
+ }
+
+ if (i == ARRAY_SIZE(exynos5_epll_div))
+ return -1;
+
+ epll_con_k = exynos5_epll_div[i].k_dsm << 0;
+ epll_con |= exynos5_epll_div[i].en_lock_det <<
+ EPLL_CON0_LOCK_DET_EN_SHIFT;
+ epll_con |= exynos5_epll_div[i].m_div << EPLL_CON0_MDIV_SHIFT;
+ epll_con |= exynos5_epll_div[i].p_div << EPLL_CON0_PDIV_SHIFT;
+ epll_con |= exynos5_epll_div[i].s_div << EPLL_CON0_SDIV_SHIFT;
+
+ /*
+ * Required period ( in cycles) to genarate a stable clock output.
+ * The maximum clock time can be up to 3000 * PDIV cycles of PLLs
+ * frequency input (as per spec)
+ */
+ lockcnt = 3000 * exynos5_epll_div[i].p_div;
+
+ writel(lockcnt, &clk->epll_lock);
+ writel(epll_con, &clk->epll_con0);
+ writel(epll_con_k, &clk->epll_con1);
+
+ start = get_timer(0);
+
+ while (!(readl(&clk->epll_con0) &
+ (0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT))) {
+ if (get_timer(start) > TIMEOUT_EPLL_LOCK) {
+ debug("%s: Timeout waiting for EPLL lock\n", __func__);
+ return -1;
+ }
+ }
+ return 0;
+}
+
+void exynos5_set_i2s_clk_source(void)
+{
+ struct exynos5_clock *clk =
+ (struct exynos5_clock *)samsung_get_base_clock();
+
+ clrsetbits_le32(&clk->src_peric1, AUDIO1_SEL_MASK,
+ (CLK_SRC_SCLK_EPLL));
+}
+
+int exynos5_set_i2s_clk_prescaler(unsigned int src_frq,
+ unsigned int dst_frq)
+{
+ struct exynos5_clock *clk =
+ (struct exynos5_clock *)samsung_get_base_clock();
+ unsigned int div;
+
+ if ((dst_frq == 0) || (src_frq == 0)) {
+ debug("%s: Invalid requency input for prescaler\n", __func__);
+ debug("src frq = %d des frq = %d ", src_frq, dst_frq);
+ return -1;
+ }
+
+ div = (src_frq / dst_frq);
+ if (div > AUDIO_1_RATIO_MASK) {
+ debug("%s: Frequency ratio is out of range\n", __func__);
+ debug("src frq = %d des frq = %d ", src_frq, dst_frq);
+ return -1;
+ }
+ clrsetbits_le32(&clk->div_peric4, AUDIO_1_RATIO_MASK,
+ (div & AUDIO_1_RATIO_MASK));
+ return 0;
+}
+
+/**
+ * Linearly searches for the most accurate main and fine stage clock scalars
+ * (divisors) for a specified target frequency and scalar bit sizes by checking
+ * all multiples of main_scalar_bits values. Will always return scalars up to or
+ * slower than target.
+ *
+ * @param main_scalar_bits Number of main scalar bits, must be > 0 and < 32
+ * @param fine_scalar_bits Number of fine scalar bits, must be > 0 and < 32
+ * @param input_freq Clock frequency to be scaled in Hz
+ * @param target_freq Desired clock frequency in Hz
+ * @param best_fine_scalar Pointer to store the fine stage divisor
+ *
+ * @return best_main_scalar Main scalar for desired frequency or -1 if none
+ * found
+ */
+static int clock_calc_best_scalar(unsigned int main_scaler_bits,
+ unsigned int fine_scalar_bits, unsigned int input_rate,
+ unsigned int target_rate, unsigned int *best_fine_scalar)
+{
+ int i;
+ int best_main_scalar = -1;
+ unsigned int best_error = target_rate;
+ const unsigned int cap = (1 << fine_scalar_bits) - 1;
+ const unsigned int loops = 1 << main_scaler_bits;
+
+ debug("Input Rate is %u, Target is %u, Cap is %u\n", input_rate,
+ target_rate, cap);
+
+ assert(best_fine_scalar != NULL);
+ assert(main_scaler_bits <= fine_scalar_bits);
+
+ *best_fine_scalar = 1;
+
+ if (input_rate == 0 || target_rate == 0)
+ return -1;
+
+ if (target_rate >= input_rate)
+ return 1;
+
+ for (i = 1; i <= loops; i++) {
+ const unsigned int effective_div = max(min(input_rate / i /
+ target_rate, cap), 1);
+ const unsigned int effective_rate = input_rate / i /
+ effective_div;
+ const int error = target_rate - effective_rate;
+
+ debug("%d|effdiv:%u, effrate:%u, error:%d\n", i, effective_div,
+ effective_rate, error);
+
+ if (error >= 0 && error <= best_error) {
+ best_error = error;
+ best_main_scalar = i;
+ *best_fine_scalar = effective_div;
+ }
+ }
+
+ return best_main_scalar;
+}
+
+static int exynos5_set_spi_clk(enum periph_id periph_id,
+ unsigned int rate)
+{
+ struct exynos5_clock *clk =
+ (struct exynos5_clock *)samsung_get_base_clock();
+ int main;
+ unsigned int fine;
+ unsigned shift, pre_shift;
+ unsigned mask = 0xff;
+ u32 *reg;
+
+ main = clock_calc_best_scalar(4, 8, 400000000, rate, &fine);
+ if (main < 0) {
+ debug("%s: Cannot set clock rate for periph %d",
+ __func__, periph_id);
+ return -1;
+ }
+ main = main - 1;
+ fine = fine - 1;
+
+ switch (periph_id) {
+ case PERIPH_ID_SPI0:
+ reg = &clk->div_peric1;
+ shift = 0;
+ pre_shift = 8;
+ break;
+ case PERIPH_ID_SPI1:
+ reg = &clk->div_peric1;
+ shift = 16;
+ pre_shift = 24;
+ break;
+ case PERIPH_ID_SPI2:
+ reg = &clk->div_peric2;
+ shift = 0;
+ pre_shift = 8;
+ break;
+ case PERIPH_ID_SPI3:
+ reg = &clk->sclk_div_isp;
+ shift = 0;
+ pre_shift = 4;
+ break;
+ case PERIPH_ID_SPI4:
+ reg = &clk->sclk_div_isp;
+ shift = 12;
+ pre_shift = 16;
+ break;
+ default:
+ debug("%s: Unsupported peripheral ID %d\n", __func__,
+ periph_id);
+ return -1;
+ }
+ clrsetbits_le32(reg, mask << shift, (main & mask) << shift);
+ clrsetbits_le32(reg, mask << pre_shift, (fine & mask) << pre_shift);
+
+ return 0;
+}
+
static unsigned long exynos4_get_i2c_clk(void)
{
struct exynos4_clock *clk =
{
if (cpu_is_exynos5())
return exynos5_get_pll_clk(pllreg);
- else
+ else {
+ if (proid_is_exynos4412())
+ return exynos4x12_get_pll_clk(pllreg);
return exynos4_get_pll_clk(pllreg);
+ }
}
unsigned long get_arm_clk(void)
{
if (cpu_is_exynos5())
return exynos5_get_arm_clk();
- else
+ else {
+ if (proid_is_exynos4412())
+ return exynos4x12_get_arm_clk();
return exynos4_get_arm_clk();
+ }
}
unsigned long get_i2c_clk(void)
{
if (cpu_is_exynos5())
return exynos5_get_pwm_clk();
- else
+ else {
+ if (proid_is_exynos4412())
+ return exynos4x12_get_pwm_clk();
return exynos4_get_pwm_clk();
+ }
}
unsigned long get_uart_clk(int dev_index)
{
if (cpu_is_exynos5())
return exynos5_get_uart_clk(dev_index);
- else
+ else {
+ if (proid_is_exynos4412())
+ return exynos4x12_get_uart_clk(dev_index);
return exynos4_get_uart_clk(dev_index);
+ }
+}
+
+unsigned long get_mmc_clk(int dev_index)
+{
+ if (cpu_is_exynos5())
+ return exynos5_get_mmc_clk(dev_index);
+ else
+ return exynos4_get_mmc_clk(dev_index);
}
void set_mmc_clk(int dev_index, unsigned int div)
{
if (cpu_is_exynos5())
exynos5_set_mmc_clk(dev_index, div);
- else
+ else {
+ if (proid_is_exynos4412())
+ exynos4x12_set_mmc_clk(dev_index, div);
exynos4_set_mmc_clk(dev_index, div);
+ }
}
unsigned long get_lcd_clk(void)
if (cpu_is_exynos4())
exynos4_set_mipi_clk();
}
+
+int set_spi_clk(int periph_id, unsigned int rate)
+{
+ if (cpu_is_exynos5())
+ return exynos5_set_spi_clk(periph_id, rate);
+ else
+ return 0;
+}
+
+int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq)
+{
+
+ if (cpu_is_exynos5())
+ return exynos5_set_i2s_clk_prescaler(src_frq, dst_frq);
+ else
+ return 0;
+}
+
+void set_i2s_clk_source(void)
+{
+ if (cpu_is_exynos5())
+ exynos5_set_i2s_clk_source();
+}
+
+int set_epll_clk(unsigned long rate)
+{
+ if (cpu_is_exynos5())
+ return exynos5_set_epll_clk(rate);
+ else
+ return 0;
+}
*/
#include <common.h>
+#include <fdtdec.h>
#include <asm/arch/gpio.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/sromc.h>
s5p_gpio_set_pull(bank, i, GPIO_PULL_UP);
s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
}
+
return 0;
}
}
}
+static void exynos5_i2s_config(int peripheral)
+{
+ int i;
+ struct exynos5_gpio_part1 *gpio1 =
+ (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
+
+ for (i = 0; i < 5; i++)
+ s5p_gpio_cfg_pin(&gpio1->b0, i, GPIO_FUNC(0x02));
+}
+
+void exynos5_spi_config(int peripheral)
+{
+ int cfg = 0, pin = 0, i;
+ struct s5p_gpio_bank *bank = NULL;
+ struct exynos5_gpio_part1 *gpio1 =
+ (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
+ struct exynos5_gpio_part2 *gpio2 =
+ (struct exynos5_gpio_part2 *) samsung_get_base_gpio_part2();
+
+ switch (peripheral) {
+ case PERIPH_ID_SPI0:
+ bank = &gpio1->a2;
+ cfg = GPIO_FUNC(0x2);
+ pin = 0;
+ break;
+ case PERIPH_ID_SPI1:
+ bank = &gpio1->a2;
+ cfg = GPIO_FUNC(0x2);
+ pin = 4;
+ break;
+ case PERIPH_ID_SPI2:
+ bank = &gpio1->b1;
+ cfg = GPIO_FUNC(0x5);
+ pin = 1;
+ break;
+ case PERIPH_ID_SPI3:
+ bank = &gpio2->f1;
+ cfg = GPIO_FUNC(0x2);
+ pin = 0;
+ break;
+ case PERIPH_ID_SPI4:
+ for (i = 0; i < 2; i++) {
+ s5p_gpio_cfg_pin(&gpio2->f0, i + 2, GPIO_FUNC(0x4));
+ s5p_gpio_cfg_pin(&gpio2->e0, i + 4, GPIO_FUNC(0x4));
+ }
+ break;
+ }
+ if (peripheral != PERIPH_ID_SPI4) {
+ for (i = pin; i < pin + 4; i++)
+ s5p_gpio_cfg_pin(bank, i, cfg);
+ }
+}
+
static int exynos5_pinmux_config(int peripheral, int flags)
{
switch (peripheral) {
case PERIPH_ID_I2C7:
exynos5_i2c_config(peripheral, flags);
break;
+ case PERIPH_ID_I2S1:
+ exynos5_i2s_config(peripheral);
+ break;
+ case PERIPH_ID_SPI0:
+ case PERIPH_ID_SPI1:
+ case PERIPH_ID_SPI2:
+ case PERIPH_ID_SPI3:
+ case PERIPH_ID_SPI4:
+ exynos5_spi_config(peripheral);
+ break;
default:
debug("%s: invalid peripheral %d", __func__, peripheral);
return -1;
}
}
+static int exynos4_mmc_config(int peripheral, int flags)
+{
+ struct exynos4_gpio_part2 *gpio2 =
+ (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
+ struct s5p_gpio_bank *bank, *bank_ext;
+ int i;
+
+ switch (peripheral) {
+ case PERIPH_ID_SDMMC0:
+ bank = &gpio2->k0;
+ bank_ext = &gpio2->k1;
+ break;
+ case PERIPH_ID_SDMMC2:
+ bank = &gpio2->k2;
+ bank_ext = &gpio2->k3;
+ break;
+ default:
+ return -1;
+ }
+ for (i = 0; i < 7; i++) {
+ if (i == 2)
+ continue;
+ s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+ s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
+ s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
+ }
+ if (flags & PINMUX_FLAG_8BIT_MODE) {
+ for (i = 3; i < 7; i++) {
+ s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x3));
+ s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_NONE);
+ s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
+ }
+ }
+
+ return 0;
+}
+
static int exynos4_pinmux_config(int peripheral, int flags)
{
switch (peripheral) {
case PERIPH_ID_I2C7:
exynos4_i2c_config(peripheral, flags);
break;
+ case PERIPH_ID_SDMMC0:
+ case PERIPH_ID_SDMMC2:
+ return exynos4_mmc_config(peripheral, flags);
+ case PERIPH_ID_SDMMC1:
+ case PERIPH_ID_SDMMC3:
+ case PERIPH_ID_SDMMC4:
+ printf("SDMMC device %d not implemented\n", peripheral);
+ return -1;
default:
debug("%s: invalid peripheral %d", __func__, peripheral);
return -1;
return -1;
}
}
+
+#ifdef CONFIG_OF_CONTROL
+static int exynos5_pinmux_decode_periph_id(const void *blob, int node)
+{
+ int err;
+ u32 cell[3];
+
+ err = fdtdec_get_int_array(blob, node, "interrupts", cell,
+ ARRAY_SIZE(cell));
+ if (err)
+ return PERIPH_ID_NONE;
+
+ /* check for invalid peripheral id */
+ if ((PERIPH_ID_SDMMC4 > cell[1]) || (cell[1] < PERIPH_ID_UART0))
+ return cell[1];
+
+ debug(" invalid peripheral id\n");
+ return PERIPH_ID_NONE;
+}
+
+int pinmux_decode_periph_id(const void *blob, int node)
+{
+ if (cpu_is_exynos5())
+ return exynos5_pinmux_decode_periph_id(blob, node);
+ else
+ return PERIPH_ID_NONE;
+}
+#endif
printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
-
+#ifdef CONFIG_MXC_SPI
+ printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
+#endif
return 0;
}
mov r10, lr
mov r4, #0 /* Fix R4 to 0 */
-#if defined(CONFIG_MX51)
+#if defined(CONFIG_SYS_MAIN_PWR_ON)
ldr r0, =GPIO1_BASE_ADDR
ldr r1, [r0, #0x0]
orr r1, r1, #1 << 23
printf("\n");
printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
+#ifdef CONFIG_MXC_SPI
printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
+#endif
printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
#include <linux/linkage.h>
+.macro init_arm_errata
+ /* ARM erratum ID #743622 */
+ mrc p15, 0, r10, c15, c0, 1 /* read diagnostic register */
+ orr r10, r10, #1 << 6 /* set bit #6 */
+ /* ARM erratum ID #751472 */
+ orr r10, r10, #1 << 11 /* set bit #11 */
+ mcr p15, 0, r10, c15, c0, 1 /* write diagnostic register */
+.endm
+
ENTRY(lowlevel_init)
+ init_arm_errata
mov pc, lr
ENDPROC(lowlevel_init)
#include <asm/arch/sys_proto.h>
#include <asm/imx-common/boot_mode.h>
+struct scu_regs {
+ u32 ctrl;
+ u32 config;
+ u32 status;
+ u32 invalidate;
+ u32 fpga_rev;
+};
+
u32 get_cpu_rev(void)
{
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
- int reg = readl(&anatop->digprog);
-
- /* Read mx6 variant: quad, dual or solo */
- int system_rev = (reg >> 4) & 0xFF000;
- /* Read mx6 silicon revision */
- system_rev |= (reg & 0xFF) + 0x10;
-
- return system_rev;
+ u32 reg = readl(&anatop->digprog_sololite);
+ u32 type = ((reg >> 16) & 0xff);
+
+ if (type != MXC_CPU_MX6SL) {
+ reg = readl(&anatop->digprog);
+ type = ((reg >> 16) & 0xff);
+ if (type == MXC_CPU_MX6DL) {
+ struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
+ u32 cfg = readl(&scu->config) & 3;
+
+ if (!cfg)
+ type = MXC_CPU_MX6SOLO;
+ }
+ }
+ reg &= 0xff; /* mx6 silicon revision */
+ return (type << 12) | (reg + 0x10);
}
void init_aips(void)
LIB = $(obj)libomap-common.o
-SOBJS := reset.o
-
-COBJS := timer.o
+COBJS := reset.o
+COBJS += timer.o
COBJS += utils.o
ifneq ($(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
#include <asm/omap_common.h>
#include <asm/arch/omap.h>
#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
/*
* This is used to verify if the configuration header
#include <asm/utils.h>
#include <linux/compiler.h>
+static int emif1_enabled = -1, emif2_enabled = -1;
+
void set_lpmode_selfrefresh(u32 base)
{
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
void dmm_init(u32 base)
{
const struct dmm_lisa_map_regs *lisa_map_regs;
+ u32 i, section, valid;
#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
emif_get_dmm_regs(&lisa_map_regs);
writel(lisa_map_regs->dmm_lisa_map_0,
&hw_lisa_map_regs->dmm_lisa_map_0);
}
+
+ /*
+ * EMIF should be configured only when
+ * memory is mapped on it. Using emif1_enabled
+ * and emif2_enabled variables for this.
+ */
+ emif1_enabled = 0;
+ emif2_enabled = 0;
+ for (i = 0; i < 4; i++) {
+ section = __raw_readl(DMM_BASE + i*4);
+ valid = (section & EMIF_SDRC_MAP_MASK) >>
+ (EMIF_SDRC_MAP_SHIFT);
+ if (valid == 3) {
+ emif1_enabled = 1;
+ emif2_enabled = 1;
+ break;
+ } else if (valid == 1) {
+ emif1_enabled = 1;
+ } else if (valid == 2) {
+ emif2_enabled = 1;
+ }
+ }
+
}
/*
writel(CM_DLL_CTRL_NO_OVERRIDE, &prcm->cm_dll_ctrl);
}
- do_sdram_init(EMIF1_BASE);
- do_sdram_init(EMIF2_BASE);
-
if (!in_sdram)
dmm_init(DMM_BASE);
+ if (emif1_enabled)
+ do_sdram_init(EMIF1_BASE);
+
+ if (emif2_enabled)
+ do_sdram_init(EMIF2_BASE);
+
if (!(in_sdram || warm_reset())) {
- emif_post_init_config(EMIF1_BASE);
- emif_post_init_config(EMIF2_BASE);
+ if (emif1_enabled)
+ emif_post_init_config(EMIF1_BASE);
+ if (emif2_enabled)
+ emif_post_init_config(EMIF2_BASE);
}
/* for the shadow registers to take effect */
*/
omap3_update_aux_cr(0, 0x2);
}
-#endif
+#endif /* !CONFIG_SYS_L2CACHE_OFF */
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
/* Enable D-cache. I-cache is already enabled in start.S */
dcache_enable();
}
-#endif
+#endif /* !CONFIG_SYS_DCACHE_OFF */
M_NAND_GPMC_CONFIG5,
M_NAND_GPMC_CONFIG6, 0
};
-
-#if defined(CONFIG_ENV_IS_IN_NAND)
-#define GPMC_CS 0
-#else
-#define GPMC_CS 1
-#endif
-
-#endif
+#endif /* CONFIG_CMD_NAND */
#if defined(CONFIG_CMD_ONENAND)
static const u32 gpmc_onenand[GPMC_MAX_REG] = {
ONENAND_GPMC_CONFIG5,
ONENAND_GPMC_CONFIG6, 0
};
-
-#if defined(CONFIG_ENV_IS_IN_ONENAND)
-#define GPMC_CS 0
-#else
-#define GPMC_CS 1
-#endif
-
-#endif
+#endif /* CONFIG_CMD_ONENAND */
/********************************************************
* mem_ok() - test used to see if timings are correct
* - Test CS to make sure it's OK for use
*/
static void write_sdrc_timings(u32 cs, struct sdrc_actim *sdrc_actim_base,
- u32 mcfg, u32 ctrla, u32 ctrlb, u32 rfr_ctrl, u32 mr)
+ struct board_sdrc_timings *timings)
{
/* Setup timings we got from the board. */
- writel(mcfg, &sdrc_base->cs[cs].mcfg);
- writel(ctrla, &sdrc_actim_base->ctrla);
- writel(ctrlb, &sdrc_actim_base->ctrlb);
- writel(rfr_ctrl, &sdrc_base->cs[cs].rfr_ctrl);
+ writel(timings->mcfg, &sdrc_base->cs[cs].mcfg);
+ writel(timings->ctrla, &sdrc_actim_base->ctrla);
+ writel(timings->ctrlb, &sdrc_actim_base->ctrlb);
+ writel(timings->rfr_ctrl, &sdrc_base->cs[cs].rfr_ctrl);
writel(CMD_NOP, &sdrc_base->cs[cs].manual);
writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
- writel(mr, &sdrc_base->cs[cs].mr);
+ writel(timings->mr, &sdrc_base->cs[cs].mr);
/*
* Test ram in this bank
void do_sdrc_init(u32 cs, u32 early)
{
struct sdrc_actim *sdrc_actim_base0, *sdrc_actim_base1;
- u32 mcfg, ctrla, ctrlb, rfr_ctrl, mr;
+ struct board_sdrc_timings timings;
sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
* setup CS1.
*/
#ifdef CONFIG_SPL_BUILD
- get_board_mem_timings(&mcfg, &ctrla, &ctrlb, &rfr_ctrl, &mr);
+ get_board_mem_timings(&timings);
#endif
if (early) {
/* reset sdrc controller */
writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
sdelay(0x20000);
#ifdef CONFIG_SPL_BUILD
- write_sdrc_timings(CS0, sdrc_actim_base0, mcfg, ctrla, ctrlb,
- rfr_ctrl, mr);
+ write_sdrc_timings(CS0, sdrc_actim_base0, &timings);
make_cs1_contiguous();
- write_sdrc_timings(CS1, sdrc_actim_base1, mcfg, ctrla, ctrlb,
- rfr_ctrl, mr);
+ write_sdrc_timings(CS1, sdrc_actim_base1, &timings);
#endif
}
* so we may be asked now to setup CS1.
*/
if (cs == CS1) {
- mcfg = readl(&sdrc_base->cs[CS0].mcfg),
- rfr_ctrl = readl(&sdrc_base->cs[CS0].rfr_ctrl);
- ctrla = readl(&sdrc_actim_base0->ctrla),
- ctrlb = readl(&sdrc_actim_base0->ctrlb);
- mr = readl(&sdrc_base->cs[CS0].mr);
- write_sdrc_timings(cs, sdrc_actim_base1, mcfg, ctrla, ctrlb,
- rfr_ctrl, mr);
-
+ timings.mcfg = readl(&sdrc_base->cs[CS0].mcfg),
+ timings.rfr_ctrl = readl(&sdrc_base->cs[CS0].rfr_ctrl);
+ timings.ctrla = readl(&sdrc_actim_base0->ctrla);
+ timings.ctrlb = readl(&sdrc_actim_base0->ctrlb);
+ timings.mr = readl(&sdrc_base->cs[CS0].mr);
+ write_sdrc_timings(cs, sdrc_actim_base1, &timings);
}
}
*/
#define printf(fmt, args...)
#define puts(s)
-#endif
+#endif /* !CONFIG_SPL_BUILD */
struct omap4_prcm_regs *const prcm = (struct omap4_prcm_regs *)0x4A004100;
if ((omap4_rev < OMAP4460_ES1_0) || !readl(&ctrl->control_efuse_2))
writel(CONTROL_EFUSE_2_OVERRIDE, &ctrl->control_efuse_2);
}
-#endif
+#endif /* CONFIG_SPL_BUILD */
/* dummy fuction for omap4 */
void config_data_eye_leveling_samples(u32 emif_base)
{
set_pl310_ctrl_reg(0);
}
-#endif
+#endif /* !CONFIG_SYS_L2CACHE_OFF */
COBJS-y += cpu_info.o
COBJS-y += timer.o
COBJS-y += sromc.o
-COBJS-y += wdt.o
COBJS-$(CONFIG_PWM) += pwm.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+++ /dev/null
-/*
- * Copyright (C) 2012 Samsung Electronics
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/watchdog.h>
-
-#define PRESCALER_VAL 255
-
-void wdt_stop(void)
-{
- struct s5p_watchdog *wdt =
- (struct s5p_watchdog *)samsung_get_base_watchdog();
- unsigned int wtcon;
-
- wtcon = readl(&wdt->wtcon);
- wtcon &= ~(WTCON_EN | WTCON_INT | WTCON_RESET);
-
- writel(wtcon, &wdt->wtcon);
-}
-
-void wdt_start(unsigned int timeout)
-{
- struct s5p_watchdog *wdt =
- (struct s5p_watchdog *)samsung_get_base_watchdog();
- unsigned int wtcon;
-
- wdt_stop();
-
- wtcon = readl(&wdt->wtcon);
- wtcon |= (WTCON_EN | WTCON_CLK(WTCON_CLK_128));
- wtcon &= ~WTCON_INT;
- wtcon |= WTCON_RESET;
- wtcon |= WTCON_PRESCALER(PRESCALER_VAL);
-
- writel(timeout, &wdt->wtdat);
- writel(timeout, &wdt->wtcnt);
- writel(wtcon, &wdt->wtcon);
-}
bl cpu_init_crit
#endif
-/* Set stackpointer in internal RAM to call board_init_f */
-call_board_init_f:
- ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
- bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
- ldr r0,=0x00000000
- bl board_init_f
+ bl _main
/*------------------------------------------------------------------------------*/
mov r5, r1 /* save addr of gd */
mov r6, r2 /* save addr of destination */
- /* Set up the stack */
-stack_setup:
- mov sp, r4
-
adr r0, _start
cmp r0, r6
moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
- beq clear_bss /* skip relocation */
+ beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _image_copy_end_ofs
add r2, r0, r3 /* r2 <- source end address */
add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
cmp r2, r3
blo fixloop
- b clear_bss
+
+relocate_done:
+
+ bx lr
+
_rel_dyn_start_ofs:
.word __rel_dyn_start - _start
_rel_dyn_end_ofs:
.word __rel_dyn_end - _start
_dynsym_start_ofs:
.word __dynsym_start - _start
+ENDPROC(relocate_code)
-clear_bss:
- ldr r0, _bss_start_ofs
- ldr r1, _bss_end_ofs
- mov r4, r6 /* reloc addr */
- add r0, r0, r4
- add r1, r1, r4
- mov r2, #0x00000000 /* clear */
-
-clbss_l:cmp r0, r1 /* clear loop... */
- bhs clbss_e /* if reached end of bss, exit */
- str r2, [r0]
- add r0, r0, #4
- b clbss_l
-clbss_e:
+#endif
-/*
- * We are done. Do not return, instead branch to second part of board
- * initialization, now running from RAM.
- */
-jump_2_ram:
+ENTRY(c_runtime_cpu_setup)
/*
* If I-cache is enabled invalidate it
*/
mcr p15, 0, r0, c12, c0, 0 @Set VBAR
#endif /* !Tegra20 */
- ldr r0, _board_init_r_ofs
- adr r1, _start
- add lr, r0, r1
- add lr, lr, r9
- /* setup parameters for board_init_r */
- mov r0, r5 /* gd_t */
- mov r1, r6 /* dest_addr */
- /* jump to it ... */
- mov pc, lr
-
-_board_init_r_ofs:
- .word board_init_r - _start
-ENDPROC(relocate_code)
-#endif
+ bx lr
+
+ENDPROC(c_runtime_cpu_setup)
/*************************************************************************
*
LIB = $(obj)lib$(SOC).o
COBJS-$(CONFIG_USB_EHCI_TEGRA) += usb.o
+COBJS-$(CONFIG_PWM_TEGRA) += pwm.o
+COBJS-$(CONFIG_VIDEO_TEGRA) += display.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch/display.h>
+#include <asm/arch/dc.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/timer.h>
+
+static struct fdt_disp_config config;
+
+static void update_window(struct dc_ctlr *dc, struct disp_ctl_win *win)
+{
+ unsigned h_dda, v_dda;
+ unsigned long val;
+
+ val = readl(&dc->cmd.disp_win_header);
+ val |= WINDOW_A_SELECT;
+ writel(val, &dc->cmd.disp_win_header);
+
+ writel(win->fmt, &dc->win.color_depth);
+
+ clrsetbits_le32(&dc->win.byte_swap, BYTE_SWAP_MASK,
+ BYTE_SWAP_NOSWAP << BYTE_SWAP_SHIFT);
+
+ val = win->out_x << H_POSITION_SHIFT;
+ val |= win->out_y << V_POSITION_SHIFT;
+ writel(val, &dc->win.pos);
+
+ val = win->out_w << H_SIZE_SHIFT;
+ val |= win->out_h << V_SIZE_SHIFT;
+ writel(val, &dc->win.size);
+
+ val = (win->w * win->bpp / 8) << H_PRESCALED_SIZE_SHIFT;
+ val |= win->h << V_PRESCALED_SIZE_SHIFT;
+ writel(val, &dc->win.prescaled_size);
+
+ writel(0, &dc->win.h_initial_dda);
+ writel(0, &dc->win.v_initial_dda);
+
+ h_dda = (win->w * 0x1000) / max(win->out_w - 1, 1);
+ v_dda = (win->h * 0x1000) / max(win->out_h - 1, 1);
+
+ val = h_dda << H_DDA_INC_SHIFT;
+ val |= v_dda << V_DDA_INC_SHIFT;
+ writel(val, &dc->win.dda_increment);
+
+ writel(win->stride, &dc->win.line_stride);
+ writel(0, &dc->win.buf_stride);
+
+ val = WIN_ENABLE;
+ if (win->bpp < 24)
+ val |= COLOR_EXPAND;
+ writel(val, &dc->win.win_opt);
+
+ writel((unsigned long)win->phys_addr, &dc->winbuf.start_addr);
+ writel(win->x, &dc->winbuf.addr_h_offset);
+ writel(win->y, &dc->winbuf.addr_v_offset);
+
+ writel(0xff00, &dc->win.blend_nokey);
+ writel(0xff00, &dc->win.blend_1win);
+
+ val = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
+ val |= GENERAL_UPDATE | WIN_A_UPDATE;
+ writel(val, &dc->cmd.state_ctrl);
+}
+
+static void write_pair(struct fdt_disp_config *config, int item, u32 *reg)
+{
+ writel(config->horiz_timing[item] |
+ (config->vert_timing[item] << 16), reg);
+}
+
+static int update_display_mode(struct dc_disp_reg *disp,
+ struct fdt_disp_config *config)
+{
+ unsigned long val;
+ unsigned long rate;
+ unsigned long div;
+
+ writel(0x0, &disp->disp_timing_opt);
+ write_pair(config, FDT_LCD_TIMING_REF_TO_SYNC, &disp->ref_to_sync);
+ write_pair(config, FDT_LCD_TIMING_SYNC_WIDTH, &disp->sync_width);
+ write_pair(config, FDT_LCD_TIMING_BACK_PORCH, &disp->back_porch);
+ write_pair(config, FDT_LCD_TIMING_FRONT_PORCH, &disp->front_porch);
+
+ writel(config->width | (config->height << 16), &disp->disp_active);
+
+ val = DE_SELECT_ACTIVE << DE_SELECT_SHIFT;
+ val |= DE_CONTROL_NORMAL << DE_CONTROL_SHIFT;
+ writel(val, &disp->data_enable_opt);
+
+ val = DATA_FORMAT_DF1P1C << DATA_FORMAT_SHIFT;
+ val |= DATA_ALIGNMENT_MSB << DATA_ALIGNMENT_SHIFT;
+ val |= DATA_ORDER_RED_BLUE << DATA_ORDER_SHIFT;
+ writel(val, &disp->disp_interface_ctrl);
+
+ /*
+ * The pixel clock divider is in 7.1 format (where the bottom bit
+ * represents 0.5). Here we calculate the divider needed to get from
+ * the display clock (typically 600MHz) to the pixel clock. We round
+ * up or down as requried.
+ */
+ rate = clock_get_periph_rate(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL);
+ div = ((rate * 2 + config->pixel_clock / 2) / config->pixel_clock) - 2;
+ debug("Display clock %lu, divider %lu\n", rate, div);
+
+ writel(0x00010001, &disp->shift_clk_opt);
+
+ val = PIXEL_CLK_DIVIDER_PCD1 << PIXEL_CLK_DIVIDER_SHIFT;
+ val |= div << SHIFT_CLK_DIVIDER_SHIFT;
+ writel(val, &disp->disp_clk_ctrl);
+
+ return 0;
+}
+
+/* Start up the display and turn on power to PWMs */
+static void basic_init(struct dc_cmd_reg *cmd)
+{
+ u32 val;
+
+ writel(0x00000100, &cmd->gen_incr_syncpt_ctrl);
+ writel(0x0000011a, &cmd->cont_syncpt_vsync);
+ writel(0x00000000, &cmd->int_type);
+ writel(0x00000000, &cmd->int_polarity);
+ writel(0x00000000, &cmd->int_mask);
+ writel(0x00000000, &cmd->int_enb);
+
+ val = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE;
+ val |= PW3_ENABLE | PW4_ENABLE | PM0_ENABLE;
+ val |= PM1_ENABLE;
+ writel(val, &cmd->disp_pow_ctrl);
+
+ val = readl(&cmd->disp_cmd);
+ val |= CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT;
+ writel(val, &cmd->disp_cmd);
+}
+
+static void basic_init_timer(struct dc_disp_reg *disp)
+{
+ writel(0x00000020, &disp->mem_high_pri);
+ writel(0x00000001, &disp->mem_high_pri_timer);
+}
+
+static const u32 rgb_enb_tab[PIN_REG_COUNT] = {
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+};
+
+static const u32 rgb_polarity_tab[PIN_REG_COUNT] = {
+ 0x00000000,
+ 0x01000000,
+ 0x00000000,
+ 0x00000000,
+};
+
+static const u32 rgb_data_tab[PIN_REG_COUNT] = {
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+};
+
+static const u32 rgb_sel_tab[PIN_OUTPUT_SEL_COUNT] = {
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00210222,
+ 0x00002200,
+ 0x00020000,
+};
+
+static void rgb_enable(struct dc_com_reg *com)
+{
+ int i;
+
+ for (i = 0; i < PIN_REG_COUNT; i++) {
+ writel(rgb_enb_tab[i], &com->pin_output_enb[i]);
+ writel(rgb_polarity_tab[i], &com->pin_output_polarity[i]);
+ writel(rgb_data_tab[i], &com->pin_output_data[i]);
+ }
+
+ for (i = 0; i < PIN_OUTPUT_SEL_COUNT; i++)
+ writel(rgb_sel_tab[i], &com->pin_output_sel[i]);
+}
+
+int setup_window(struct disp_ctl_win *win, struct fdt_disp_config *config)
+{
+ win->x = 0;
+ win->y = 0;
+ win->w = config->width;
+ win->h = config->height;
+ win->out_x = 0;
+ win->out_y = 0;
+ win->out_w = config->width;
+ win->out_h = config->height;
+ win->phys_addr = config->frame_buffer;
+ win->stride = config->width * (1 << config->log2_bpp) / 8;
+ debug("%s: depth = %d\n", __func__, config->log2_bpp);
+ switch (config->log2_bpp) {
+ case 5:
+ case 24:
+ win->fmt = COLOR_DEPTH_R8G8B8A8;
+ win->bpp = 32;
+ break;
+ case 4:
+ win->fmt = COLOR_DEPTH_B5G6R5;
+ win->bpp = 16;
+ break;
+
+ default:
+ debug("Unsupported LCD bit depth");
+ return -1;
+ }
+
+ return 0;
+}
+
+struct fdt_disp_config *tegra_display_get_config(void)
+{
+ return config.valid ? &config : NULL;
+}
+
+static void debug_timing(const char *name, unsigned int timing[])
+{
+#ifdef DEBUG
+ int i;
+
+ debug("%s timing: ", name);
+ for (i = 0; i < FDT_LCD_TIMING_COUNT; i++)
+ debug("%d ", timing[i]);
+ debug("\n");
+#endif
+}
+
+/**
+ * Decode panel information from the fdt, according to a standard binding
+ *
+ * @param blob fdt blob
+ * @param node offset of fdt node to read from
+ * @param config structure to store fdt config into
+ * @return 0 if ok, -ve on error
+ */
+static int tegra_decode_panel(const void *blob, int node,
+ struct fdt_disp_config *config)
+{
+ int front, back, ref;
+
+ config->width = fdtdec_get_int(blob, node, "xres", -1);
+ config->height = fdtdec_get_int(blob, node, "yres", -1);
+ config->pixel_clock = fdtdec_get_int(blob, node, "clock", 0);
+ if (!config->pixel_clock || config->width == -1 ||
+ config->height == -1) {
+ debug("%s: Pixel parameters missing\n", __func__);
+ return -FDT_ERR_NOTFOUND;
+ }
+
+ back = fdtdec_get_int(blob, node, "left-margin", -1);
+ front = fdtdec_get_int(blob, node, "right-margin", -1);
+ ref = fdtdec_get_int(blob, node, "hsync-len", -1);
+ if ((back | front | ref) == -1) {
+ debug("%s: Horizontal parameters missing\n", __func__);
+ return -FDT_ERR_NOTFOUND;
+ }
+
+ /* Use a ref-to-sync of 1 always, and take this from the front porch */
+ config->horiz_timing[FDT_LCD_TIMING_REF_TO_SYNC] = 1;
+ config->horiz_timing[FDT_LCD_TIMING_SYNC_WIDTH] = ref;
+ config->horiz_timing[FDT_LCD_TIMING_BACK_PORCH] = back;
+ config->horiz_timing[FDT_LCD_TIMING_FRONT_PORCH] = front -
+ config->horiz_timing[FDT_LCD_TIMING_REF_TO_SYNC];
+ debug_timing("horiz", config->horiz_timing);
+
+ back = fdtdec_get_int(blob, node, "upper-margin", -1);
+ front = fdtdec_get_int(blob, node, "lower-margin", -1);
+ ref = fdtdec_get_int(blob, node, "vsync-len", -1);
+ if ((back | front | ref) == -1) {
+ debug("%s: Vertical parameters missing\n", __func__);
+ return -FDT_ERR_NOTFOUND;
+ }
+
+ config->vert_timing[FDT_LCD_TIMING_REF_TO_SYNC] = 1;
+ config->vert_timing[FDT_LCD_TIMING_SYNC_WIDTH] = ref;
+ config->vert_timing[FDT_LCD_TIMING_BACK_PORCH] = back;
+ config->vert_timing[FDT_LCD_TIMING_FRONT_PORCH] = front -
+ config->vert_timing[FDT_LCD_TIMING_REF_TO_SYNC];
+ debug_timing("vert", config->vert_timing);
+
+ return 0;
+}
+
+/**
+ * Decode the display controller information from the fdt.
+ *
+ * @param blob fdt blob
+ * @param config structure to store fdt config into
+ * @return 0 if ok, -ve on error
+ */
+static int tegra_display_decode_config(const void *blob,
+ struct fdt_disp_config *config)
+{
+ int node, rgb;
+ int bpp, bit;
+
+ /* TODO: Support multiple controllers */
+ node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA20_DC);
+ if (node < 0) {
+ debug("%s: Cannot find display controller node in fdt\n",
+ __func__);
+ return node;
+ }
+ config->disp = (struct disp_ctlr *)fdtdec_get_addr(blob, node, "reg");
+ if (!config->disp) {
+ debug("%s: No display controller address\n", __func__);
+ return -1;
+ }
+
+ rgb = fdt_subnode_offset(blob, node, "rgb");
+
+ config->panel_node = fdtdec_lookup_phandle(blob, rgb, "nvidia,panel");
+ if (!config->panel_node < 0) {
+ debug("%s: Cannot find panel information\n", __func__);
+ return -1;
+ }
+
+ if (tegra_decode_panel(blob, config->panel_node, config)) {
+ debug("%s: Failed to decode panel information\n", __func__);
+ return -1;
+ }
+
+ bpp = fdtdec_get_int(blob, config->panel_node, "nvidia,bits-per-pixel",
+ -1);
+ bit = ffs(bpp) - 1;
+ if (bpp == (1 << bit))
+ config->log2_bpp = bit;
+ else
+ config->log2_bpp = bpp;
+ if (bpp == -1) {
+ debug("%s: Pixel bpp parameters missing\n", __func__);
+ return -FDT_ERR_NOTFOUND;
+ }
+ config->bpp = bpp;
+
+ config->valid = 1; /* we have a valid configuration */
+
+ return 0;
+}
+
+int tegra_display_probe(const void *blob, void *default_lcd_base)
+{
+ struct disp_ctl_win window;
+ struct dc_ctlr *dc;
+
+ if (tegra_display_decode_config(blob, &config))
+ return -1;
+
+ config.frame_buffer = (u32)default_lcd_base;
+
+ dc = (struct dc_ctlr *)config.disp;
+
+ /*
+ * A header file for clock constants was NAKed upstream.
+ * TODO: Put this into the FDT and fdt_lcd struct when we have clock
+ * support there
+ */
+ clock_start_periph_pll(PERIPH_ID_HOST1X, CLOCK_ID_PERIPH,
+ 144 * 1000000);
+ clock_start_periph_pll(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL,
+ 600 * 1000000);
+ basic_init(&dc->cmd);
+ basic_init_timer(&dc->disp);
+ rgb_enable(&dc->com);
+
+ if (config.pixel_clock)
+ update_display_mode(&dc->disp, &config);
+
+ if (setup_window(&window, &config))
+ return -1;
+
+ update_window(dc, &window);
+
+ return 0;
+}
--- /dev/null
+/*
+ * Tegra2 pulse width frequency modulator definitions
+ *
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/pwm.h>
+
+struct pwm_info {
+ struct pwm_ctlr *pwm; /* Registers for our pwm controller */
+ int pwm_node; /* PWM device tree node */
+} local;
+
+void pwm_enable(unsigned channel, int rate, int pulse_width, int freq_divider)
+{
+ u32 reg;
+
+ assert(channel < PWM_NUM_CHANNELS);
+
+ /* TODO: Can we use clock_adjust_periph_pll_div() here? */
+ clock_start_periph_pll(PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ, rate);
+
+ reg = PWM_ENABLE_MASK;
+ reg |= pulse_width << PWM_WIDTH_SHIFT;
+ reg |= freq_divider << PWM_DIVIDER_SHIFT;
+ writel(reg, &local.pwm[channel].control);
+ debug("%s: channel=%d, rate=%d\n", __func__, channel, rate);
+}
+
+int pwm_request(const void *blob, int node, const char *prop_name)
+{
+ int pwm_node;
+ u32 data[3];
+
+ if (fdtdec_get_int_array(blob, node, prop_name, data,
+ ARRAY_SIZE(data))) {
+ debug("%s: Cannot decode PWM property '%s'\n", __func__,
+ prop_name);
+ return -1;
+ }
+
+ pwm_node = fdt_node_offset_by_phandle(blob, data[0]);
+ if (pwm_node != local.pwm_node) {
+ debug("%s: PWM property '%s' phandle %d not recognised"
+ "- expecting %d\n", __func__, prop_name, data[0],
+ local.pwm_node);
+ return -1;
+ }
+ if (data[1] >= PWM_NUM_CHANNELS) {
+ debug("%s: PWM property '%s': invalid channel %u\n", __func__,
+ prop_name, data[1]);
+ return -1;
+ }
+
+ /*
+ * TODO: We could maintain a list of requests, but it might not be
+ * worth it for U-Boot.
+ */
+ return data[1];
+}
+
+int pwm_init(const void *blob)
+{
+ local.pwm_node = fdtdec_next_compatible(blob, 0,
+ COMPAT_NVIDIA_TEGRA20_PWM);
+ if (local.pwm_node < 0) {
+ debug("%s: Cannot find device tree node\n", __func__);
+ return -1;
+ }
+
+ local.pwm = (struct pwm_ctlr *)fdtdec_get_addr(blob, local.pwm_node,
+ "reg");
+ if (local.pwm == (struct pwm_ctlr *)FDT_ADDR_T_NONE) {
+ debug("%s: Cannot find pwm reg address\n", __func__);
+ return -1;
+ }
+ debug("Tegra PWM at %p, node %d\n", local.pwm, local.pwm_node);
+
+ return 0;
+}
orr r0,r0,#0x13
msr cpsr,r0
-/* Set initial stackpointer in SDRAM to call board_init_f */
-call_board_init_f:
- ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
- bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
- ldr r0,=0x00000000
- bl board_init_f
+ bl _main
/*------------------------------------------------------------------------------*/
mov r5, r1 /* save addr of gd */
mov r6, r2 /* save addr of destination */
- /* Set up the stack */
-stack_setup:
- mov sp, r4
-
adr r0, _start
cmp r0, r6
moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
- beq clear_bss /* skip relocation */
+ beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */
blo fixloop
#endif
-clear_bss:
-#ifndef CONFIG_SPL_BUILD
- ldr r0, _bss_start_ofs
- ldr r1, _bss_end_ofs
- mov r4, r6 /* reloc addr */
- add r0, r0, r4
- add r1, r1, r4
- mov r2, #0x00000000 /* clear */
-
-clbss_l:cmp r0, r1 /* clear loop... */
- bhs clbss_e /* if reached end of bss, exit */
- str r2, [r0]
- add r0, r0, #4
- b clbss_l
-clbss_e:
-
- bl coloured_LED_init
- bl red_led_on
-#endif
+relocate_done:
-/*
- * We are done. Do not return, instead branch to second part of board
- * initialization, now running from RAM.
- */
- ldr r0, _board_init_r_ofs
- adr r1, _start
- add lr, r0, r1
- add lr, lr, r9
- /* setup parameters for board_init_r */
- mov r0, r5 /* gd_t */
- mov r1, r6 /* dest_addr */
- /* jump to it ... */
- mov pc, lr
-
-_board_init_r_ofs:
- .word board_init_r - _start
+ bx lr
_rel_dyn_start_ofs:
.word __rel_dyn_start - _start
_dynsym_start_ofs:
.word __dynsym_start - _start
+ .globl c_runtime_cpu_setup
+c_runtime_cpu_setup:
+
+ bx lr
+
/****************************************************************************/
/* */
/* Interrupt handling */
bl lock_cache_for_stack
#endif
-/* Set stackpointer in internal RAM to call board_init_f */
-call_board_init_f:
- ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
- bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
- ldr r0, =0x00000000
- bl board_init_f
+ bl _main
/*------------------------------------------------------------------------------*/
#ifndef CONFIG_SPL_BUILD
mov r5, r1 /* save addr of gd */
mov r6, r2 /* save addr of destination */
- /* Set up the stack */
-stack_setup:
- mov sp, r4
-
/* Disable the Dcache RAM lock for stack now */
#ifdef CONFIG_CPU_PXA25X
+ mov r12, lr
bl cpu_init_crit
+ mov lr, r12
#endif
adr r0, _start
cmp r0, r6
moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
- beq clear_bss /* skip relocation */
+ beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */
blo fixloop
#endif
-clear_bss:
-#ifndef CONFIG_SPL_BUILD
- ldr r0, _bss_start_ofs
- ldr r1, _bss_end_ofs
- mov r4, r6 /* reloc addr */
- add r0, r0, r4
- add r1, r1, r4
- mov r2, #0x00000000 /* clear */
-
-clbss_l:cmp r0, r1 /* clear loop... */
- bhs clbss_e /* if reached end of bss, exit */
- str r2, [r0]
- add r0, r0, #4
- b clbss_l
-clbss_e:
-#endif /* #ifndef CONFIG_SPL_BUILD */
+relocate_done:
-/*
- * We are done. Do not return, instead branch to second part of board
- * initialization, now running from RAM.
- */
-#ifdef CONFIG_ONENAND_SPL
- ldr r0, _onenand_boot_ofs
- mov pc, r0
-
-_onenand_boot_ofs:
- .word onenand_boot
-#else
-jump_2_ram:
- ldr r0, _board_init_r_ofs
- ldr r1, _TEXT_BASE
- add lr, r0, r1
- add lr, lr, r9
- /* setup parameters for board_init_r */
- mov r0, r5 /* gd_t */
- mov r1, r6 /* dest_addr */
- /* jump to it ... */
- mov pc, lr
-
-_board_init_r_ofs:
- .word board_init_r - _start
-#endif
+ bx lr
_rel_dyn_start_ofs:
.word __rel_dyn_start - _start
.word __rel_dyn_end - _start
_dynsym_start_ofs:
.word __dynsym_start - _start
+
#endif
+
+ .globl c_runtime_cpu_setup
+c_runtime_cpu_setup:
+
+ bx lr
+
/*
*************************************************************************
*
bl lowlevel_init
#endif
-/* Set stackpointer in internal RAM to call board_init_f */
-call_board_init_f:
- ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
- bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
- ldr r0,=0x00000000
- bl board_init_f
+ bl _main
/*------------------------------------------------------------------------------*/
mov r5, r1 /* save addr of gd */
mov r6, r2 /* save addr of destination */
- /* Set up the stack */
-stack_setup:
- mov sp, r4
-
adr r0, _start
cmp r0, r6
moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
- beq clear_bss /* skip relocation */
+ beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */
blo fixloop
#endif
-clear_bss:
-#ifndef CONFIG_SPL_BUILD
- ldr r0, _bss_start_ofs
- ldr r1, _bss_end_ofs
- mov r4, r6 /* reloc addr */
- add r0, r0, r4
- add r1, r1, r4
- mov r2, #0x00000000 /* clear */
-
-clbss_l:cmp r0, r1 /* clear loop... */
- bhs clbss_e /* if reached end of bss, exit */
- str r2, [r0]
- add r0, r0, #4
- b clbss_l
-clbss_e:
-
- bl coloured_LED_init
- bl red_led_on
-#endif
+relocate_done:
-/*
- * We are done. Do not return, instead branch to second part of board
- * initialization, now running from RAM.
- */
- ldr r0, _board_init_r_ofs
- adr r1, _start
- add lr, r0, r1
- add lr, lr, r9
- /* setup parameters for board_init_r */
- mov r0, r5 /* gd_t */
- mov r1, r6 /* dest_addr */
- /* jump to it ... */
- mov pc, lr
-
-_board_init_r_ofs:
- .word board_init_r - _start
+ bx lr
_rel_dyn_start_ofs:
.word __rel_dyn_start - _start
_dynsym_start_ofs:
.word __dynsym_start - _start
+ .globl c_runtime_cpu_setup
+c_runtime_cpu_setup:
+
+ bx lr
+
/*
*************************************************************************
*
bl cpu_init_crit
#endif
-/* Set stackpointer in internal RAM to call board_init_f */
-call_board_init_f:
- ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
- bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
- ldr r0,=0x00000000
- bl board_init_f
+ bl _main
/*------------------------------------------------------------------------------*/
mov r5, r1 /* save addr of gd */
mov r6, r2 /* save addr of destination */
- /* Set up the stack */
-stack_setup:
- mov sp, r4
-
adr r0, _start
cmp r0, r6
moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
- beq clear_bss /* skip relocation */
+ beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */
blo fixloop
#endif
-clear_bss:
-#ifndef CONFIG_SPL_BUILD
- ldr r0, _bss_start_ofs
- ldr r1, _bss_end_ofs
- mov r4, r6 /* reloc addr */
- add r0, r0, r4
- add r1, r1, r4
- mov r2, #0x00000000 /* clear */
-
-clbss_l:cmp r0, r1 /* clear loop... */
- bhs clbss_e /* if reached end of bss, exit */
- str r2, [r0]
- add r0, r0, #4
- b clbss_l
-clbss_e:
-#endif
+relocate_done:
-/*
- * We are done. Do not return, instead branch to second part of board
- * initialization, now running from RAM.
- */
- ldr r0, _board_init_r_ofs
- adr r1, _start
- add lr, r0, r1
- add lr, lr, r9
- /* setup parameters for board_init_r */
- mov r0, r5 /* gd_t */
- mov r1, r6 /* dest_addr */
- /* jump to it ... */
mov pc, lr
-_board_init_r_ofs:
- .word board_init_r - _start
-
_rel_dyn_start_ofs:
.word __rel_dyn_start - _start
_rel_dyn_end_ofs:
_dynsym_start_ofs:
.word __dynsym_start - _start
+ .globl c_runtime_cpu_setup
+c_runtime_cpu_setup:
+
+ mov pc, lr
+
/*
*************************************************************************
*
#include <asm/arch/funcmux.h>
#include <asm/arch/pinmux.h>
+/*
+ * The PINMUX macro is used to set up pinmux tables.
+ */
+#define PINMUX(grp, mux, pupd, tri) \
+ {PINGRP_##grp, PMUX_FUNC_##mux, PMUX_PULL_##pupd, PMUX_TRI_##tri}
+
+static const struct pingroup_config disp1_default[] = {
+ PINMUX(LDI, DISPA, NORMAL, NORMAL),
+ PINMUX(LHP0, DISPA, NORMAL, NORMAL),
+ PINMUX(LHP1, DISPA, NORMAL, NORMAL),
+ PINMUX(LHP2, DISPA, NORMAL, NORMAL),
+ PINMUX(LHS, DISPA, NORMAL, NORMAL),
+ PINMUX(LM0, RSVD4, NORMAL, NORMAL),
+ PINMUX(LPP, DISPA, NORMAL, NORMAL),
+ PINMUX(LPW0, DISPA, NORMAL, NORMAL),
+ PINMUX(LPW2, DISPA, NORMAL, NORMAL),
+ PINMUX(LSC0, DISPA, NORMAL, NORMAL),
+ PINMUX(LSPI, DISPA, NORMAL, NORMAL),
+ PINMUX(LVP1, DISPA, NORMAL, NORMAL),
+ PINMUX(LVS, DISPA, NORMAL, NORMAL),
+ PINMUX(SLXD, SPDIF, NORMAL, NORMAL),
+};
+
+
int funcmux_select(enum periph_id id, int config)
{
int bad_config = config != FUNCMUX_DEFAULT;
break;
}
break;
+ case PERIPH_ID_DISP1:
+ if (config == FUNCMUX_DEFAULT) {
+ int i;
+
+ for (i = PINGRP_LD0; i <= PINGRP_LD17; i++) {
+ pinmux_set_func(i, PMUX_FUNC_DISPA);
+ pinmux_tristate_disable(i);
+ pinmux_set_pullupdown(i, PMUX_PULL_NORMAL);
+ }
+ pinmux_config_table(disp1_default,
+ ARRAY_SIZE(disp1_default));
+ }
+ break;
default:
debug("%s: invalid periph_id %d", __func__, id);
writel(reg, muxctl);
}
-void pinmux_config_pingroup(struct pingroup_config *config)
+void pinmux_config_pingroup(const struct pingroup_config *config)
{
enum pmux_pingrp pin = config->pingroup;
pinmux_set_tristate(pin, config->tristate);
}
-void pinmux_config_table(struct pingroup_config *config, int len)
+void pinmux_config_table(const struct pingroup_config *config, int len)
{
int i;
--- /dev/null
+/*
+ * SAMSUNG EXYNOS5250 SoC device tree source
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
+ * EXYNOS5250 based board files can include this file and provide
+ * values for board specfic bindings.
+ *
+ * Note: This file does not include device nodes for all the controllers in
+ * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
+ * additional nodes can be added to this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/include/ "skeleton.dtsi"
+
+/ {
+ compatible = "samsung,exynos5250";
+
+ sromc@12250000 {
+ compatible = "samsung,exynos-sromc";
+ reg = <0x12250000 0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c@12c60000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-i2c";
+ reg = <0x12C60000 0x100>;
+ interrupts = <0 56 0>;
+ };
+
+ i2c@12c70000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-i2c";
+ reg = <0x12C70000 0x100>;
+ interrupts = <0 57 0>;
+ };
+
+ i2c@12c80000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-i2c";
+ reg = <0x12C80000 0x100>;
+ interrupts = <0 58 0>;
+ };
+
+ i2c@12c90000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-i2c";
+ reg = <0x12C90000 0x100>;
+ interrupts = <0 59 0>;
+ };
+
+ i2c@12ca0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-i2c";
+ reg = <0x12CA0000 0x100>;
+ interrupts = <0 60 0>;
+ };
+
+ i2c@12cb0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-i2c";
+ reg = <0x12CB0000 0x100>;
+ interrupts = <0 61 0>;
+ };
+
+ i2c@12cc0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-i2c";
+ reg = <0x12CC0000 0x100>;
+ interrupts = <0 62 0>;
+ };
+
+ i2c@12cd0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,s3c2440-i2c";
+ reg = <0x12CD0000 0x100>;
+ interrupts = <0 63 0>;
+ };
+
+ sound@12d60000 {
+ compatible = "samsung,exynos-sound";
+ reg = <0x12d60000 0x20>;
+ };
+
+ spi@12d20000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,exynos-spi";
+ reg = <0x12d20000 0x30>;
+ interrupts = <0 68 0>;
+ };
+
+ spi@12d30000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,exynos-spi";
+ reg = <0x12d30000 0x30>;
+ interrupts = <0 69 0>;
+ };
+
+ spi@12d40000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,exynos-spi";
+ reg = <0x12d40000 0x30>;
+ clock-frequency = <50000000>;
+ interrupts = <0 70 0>;
+ };
+
+ spi@131a0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,exynos-spi";
+ reg = <0x131a0000 0x30>;
+ interrupts = <0 129 0>;
+ };
+
+ spi@131b0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,exynos-spi";
+ reg = <0x131b0000 0x30>;
+ interrupts = <0 130 0>;
+ };
+
+ ehci@12110000 {
+ compatible = "samsung,exynos-ehci";
+ reg = <0x12110000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ phy {
+ compatible = "samsung,exynos-usb-phy";
+ reg = <0x12130000 0x100>;
+ };
+ };
+
+};
compatible = "nvidia,tegra20-nand";
reg = <0x70008000 0x100>;
};
+
+ pwm: pwm@7000a000 {
+ compatible = "nvidia,tegra20-pwm";
+ reg = <0x7000a000 0x100>;
+ #pwm-cells = <2>;
+ };
+
+ host1x {
+ compatible = "nvidia,tegra20-host1x", "simple-bus";
+ reg = <0x50000000 0x00024000>;
+ interrupts = <0 65 0x04 /* mpcore syncpt */
+ 0 67 0x04>; /* mpcore general */
+ status = "disabled";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ranges = <0x54000000 0x54000000 0x04000000>;
+
+ /* video-encoding/decoding */
+ mpe {
+ reg = <0x54040000 0x00040000>;
+ interrupts = <0 68 0x04>;
+ status = "disabled";
+ };
+
+ /* video input */
+ vi {
+ reg = <0x54080000 0x00040000>;
+ interrupts = <0 69 0x04>;
+ status = "disabled";
+ };
+
+ /* EPP */
+ epp {
+ reg = <0x540c0000 0x00040000>;
+ interrupts = <0 70 0x04>;
+ status = "disabled";
+ };
+
+ /* ISP */
+ isp {
+ reg = <0x54100000 0x00040000>;
+ interrupts = <0 71 0x04>;
+ status = "disabled";
+ };
+
+ /* 2D engine */
+ gr2d {
+ reg = <0x54140000 0x00040000>;
+ interrupts = <0 72 0x04>;
+ status = "disabled";
+ };
+
+ /* 3D engine */
+ gr3d {
+ reg = <0x54180000 0x00040000>;
+ status = "disabled";
+ };
+
+ /* display controllers */
+ dc@54200000 {
+ compatible = "nvidia,tegra20-dc";
+ reg = <0x54200000 0x00040000>;
+ interrupts = <0 73 0x04>;
+ status = "disabled";
+
+ rgb {
+ status = "disabled";
+ };
+ };
+
+ dc@54240000 {
+ compatible = "nvidia,tegra20-dc";
+ reg = <0x54240000 0x00040000>;
+ interrupts = <0 74 0x04>;
+ status = "disabled";
+
+ rgb {
+ status = "disabled";
+ };
+ };
+
+ /* outputs */
+ hdmi {
+ compatible = "nvidia,tegra20-hdmi";
+ reg = <0x54280000 0x00040000>;
+ interrupts = <0 75 0x04>;
+ status = "disabled";
+ };
+
+ tvo {
+ compatible = "nvidia,tegra20-tvo";
+ reg = <0x542c0000 0x00040000>;
+ interrupts = <0 76 0x04>;
+ status = "disabled";
+ };
+
+ dsi {
+ compatible = "nvidia,tegra20-dsi";
+ reg = <0x54300000 0x00040000>;
+ status = "disabled";
+ };
+ };
+
};
}
}
+#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
+#if defined(CONFIG_MX53)
+#define MEMCTL_BASE ESDCTL_BASE_ADDR;
+#else
+#define MEMCTL_BASE MMDC_P0_BASE_ADDR;
+#endif
+static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9};
+static const unsigned char bank_lookup[] = {3, 2};
+
+struct esd_mmdc_regs {
+ uint32_t ctl;
+ uint32_t pdc;
+ uint32_t otc;
+ uint32_t cfg0;
+ uint32_t cfg1;
+ uint32_t cfg2;
+ uint32_t misc;
+ uint32_t scr;
+ uint32_t ref;
+ uint32_t rsvd1;
+ uint32_t rsvd2;
+ uint32_t rwd;
+ uint32_t or;
+ uint32_t mrr;
+ uint32_t cfg3lp;
+ uint32_t mr4;
+};
+
+#define ESD_MMDC_CTL_GET_ROW(mdctl) ((ctl >> 24) & 7)
+#define ESD_MMDC_CTL_GET_COLUMN(mdctl) ((ctl >> 20) & 7)
+#define ESD_MMDC_CTL_GET_WIDTH(mdctl) ((ctl >> 16) & 3)
+#define ESD_MMDC_CTL_GET_CS1(mdctl) ((ctl >> 30) & 1)
+#define ESD_MMDC_MISC_GET_BANK(mdmisc) ((misc >> 5) & 1)
+
+unsigned imx_ddr_size(void)
+{
+ struct esd_mmdc_regs *mem = (struct esd_mmdc_regs *)MEMCTL_BASE;
+ unsigned ctl = readl(&mem->ctl);
+ unsigned misc = readl(&mem->misc);
+ int bits = 11 + 0 + 0 + 1; /* row + col + bank + width */
+
+ bits += ESD_MMDC_CTL_GET_ROW(ctl);
+ bits += col_lookup[ESD_MMDC_CTL_GET_COLUMN(ctl)];
+ bits += bank_lookup[ESD_MMDC_MISC_GET_BANK(misc)];
+ bits += ESD_MMDC_CTL_GET_WIDTH(ctl);
+ bits += ESD_MMDC_CTL_GET_CS1(ctl);
+ return 1 << bits;
+}
+#endif
+
#if defined(CONFIG_DISPLAY_CPUINFO)
-static const char *get_imx_type(u32 imxtype)
+const char *get_imx_type(u32 imxtype)
{
switch (imxtype) {
- case 0x63:
+ case MXC_CPU_MX6Q:
return "6Q"; /* Quad-core version of the mx6 */
- case 0x61:
- return "6DS"; /* Dual/Solo version of the mx6 */
- case 0x60:
+ case MXC_CPU_MX6DL:
+ return "6DL"; /* Dual Lite version of the mx6 */
+ case MXC_CPU_MX6SOLO:
+ return "6SOLO"; /* Solo version of the mx6 */
+ case MXC_CPU_MX6SL:
return "6SL"; /* Solo-Lite version of the mx6 */
- case 0x51:
+ case MXC_CPU_MX51:
return "51";
- case 0x53:
+ case MXC_CPU_MX53:
return "53";
default:
return "??";
}
#endif
-void reset_cpu(ulong addr)
-{
- __raw_writew(4, WDOG1_BASE_ADDR);
-}
-
u32 get_ahb_clk(void)
{
struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
#ifndef __KERNEL_STRICT_NAMES
#ifndef __ASSEMBLY__
+struct gpmc_cs {
+ u32 config1; /* 0x00 */
+ u32 config2; /* 0x04 */
+ u32 config3; /* 0x08 */
+ u32 config4; /* 0x0C */
+ u32 config5; /* 0x10 */
+ u32 config6; /* 0x14 */
+ u32 config7; /* 0x18 */
+ u32 nand_cmd; /* 0x1C */
+ u32 nand_adr; /* 0x20 */
+ u32 nand_dat; /* 0x24 */
+ u8 res[8]; /* blow up to 0x30 byte */
+};
+
+struct bch_res_0_3 {
+ u32 bch_result_x[4];
+};
+
+struct gpmc {
+ u8 res1[0x10];
+ u32 sysconfig; /* 0x10 */
+ u8 res2[0x4];
+ u32 irqstatus; /* 0x18 */
+ u32 irqenable; /* 0x1C */
+ u8 res3[0x20];
+ u32 timeout_control; /* 0x40 */
+ u8 res4[0xC];
+ u32 config; /* 0x50 */
+ u32 status; /* 0x54 */
+ u8 res5[0x8]; /* 0x58 */
+ struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */
+ u8 res6[0x14]; /* 0x1E0 */
+ u32 ecc_config; /* 0x1F4 */
+ u32 ecc_control; /* 0x1F8 */
+ u32 ecc_size_config; /* 0x1FC */
+ u32 ecc1_result; /* 0x200 */
+ u32 ecc2_result; /* 0x204 */
+ u32 ecc3_result; /* 0x208 */
+ u32 ecc4_result; /* 0x20C */
+ u32 ecc5_result; /* 0x210 */
+ u32 ecc6_result; /* 0x214 */
+ u32 ecc7_result; /* 0x218 */
+ u32 ecc8_result; /* 0x21C */
+ u32 ecc9_result; /* 0x220 */
+ u8 res7[12]; /* 0x224 */
+ u32 testmomde_ctrl; /* 0x230 */
+ u8 res8[12]; /* 0x234 */
+ struct bch_res_0_3 bch_result_0_3[2]; /* 0x240 */
+};
+
+/* Used for board specific gpmc initialization */
+extern struct gpmc *gpmc_cfg;
+
/* Encapsulating core pll registers */
struct cm_wkuppll {
unsigned int wkclkstctrl; /* offset 0x00 */
--- /dev/null
+/*
+ * (C) Copyright 2010-2011 Texas Instruments, <www.ti.com>
+ * Mansoor Ahamed <mansoor.ahamed@ti.com>
+ *
+ * Derived from work done by Rohit Choraria <rohitkc@ti.com> for omap3
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_ARCH_ELM_H
+#define __ASM_ARCH_ELM_H
+/*
+ * ELM Module Registers
+ */
+
+/* ELM registers bit fields */
+#define ELM_SYSCONFIG_SOFTRESET_MASK (0x2)
+#define ELM_SYSCONFIG_SOFTRESET (0x2)
+#define ELM_SYSSTATUS_RESETDONE_MASK (0x1)
+#define ELM_SYSSTATUS_RESETDONE (0x1)
+#define ELM_LOCATION_CONFIG_ECC_BCH_LEVEL_MASK (0x3)
+#define ELM_LOCATION_CONFIG_ECC_SIZE_MASK (0x7FF0000)
+#define ELM_LOCATION_CONFIG_ECC_SIZE_POS (16)
+#define ELM_SYNDROME_FRAGMENT_6_SYNDROME_VALID (0x00010000)
+#define ELM_LOCATION_STATUS_ECC_CORRECTABLE_MASK (0x100)
+#define ELM_LOCATION_STATUS_ECC_NB_ERRORS_MASK (0x1F)
+
+#ifndef __ASSEMBLY__
+
+enum bch_level {
+ BCH_4_BIT = 0,
+ BCH_8_BIT,
+ BCH_16_BIT
+};
+
+
+/* BCH syndrome registers */
+struct syndrome {
+ u32 syndrome_fragment_x[7]; /* 0x400, 0x404.... 0x418 */
+ u8 res1[36]; /* 0x41c */
+};
+
+/* BCH error status & location register */
+struct location {
+ u32 location_status; /* 0x800 */
+ u8 res1[124]; /* 0x804 */
+ u32 error_location_x[16]; /* 0x880.... */
+ u8 res2[64]; /* 0x8c0 */
+};
+
+/* BCH ELM register map - do not try to allocate memmory for this structure.
+ * We have used plenty of reserved variables to fill the slots in the ELM
+ * register memory map.
+ * Directly initialize the struct pointer to ELM base address.
+ */
+struct elm {
+ u32 rev; /* 0x000 */
+ u8 res1[12]; /* 0x004 */
+ u32 sysconfig; /* 0x010 */
+ u32 sysstatus; /* 0x014 */
+ u32 irqstatus; /* 0x018 */
+ u32 irqenable; /* 0x01c */
+ u32 location_config; /* 0x020 */
+ u8 res2[92]; /* 0x024 */
+ u32 page_ctrl; /* 0x080 */
+ u8 res3[892]; /* 0x084 */
+ struct syndrome syndrome_fragments[8]; /* 0x400 */
+ u8 res4[512]; /* 0x600 */
+ struct location error_location[8]; /* 0x800 */
+};
+
+int elm_check_error(u8 *syndrome, u32 nibbles, u32 *error_count,
+ u32 *error_locations);
+int elm_config(enum bch_level level);
+void elm_reset(void);
+void elm_init(void);
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_ARCH_ELM_H */
#define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400)
#define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE
+/* GPMC Base address */
+#define GPMC_BASE 0x50000000
+
/* CPSW Config space */
#define AM335X_CPSW_BASE 0x4A100000
#define AM335X_CPSW_MDIO_BASE 0x4A101000
--- /dev/null
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author
+ * Mansoor Ahamed <mansoor.ahamed@ti.com>
+ *
+ * Initial Code from:
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _MEM_H_
+#define _MEM_H_
+
+/*
+ * GPMC settings -
+ * Definitions is as per the following format
+ * #define <PART>_GPMC_CONFIG<x> <value>
+ * Where:
+ * PART is the part name e.g. STNOR - Intel Strata Flash
+ * x is GPMC config registers from 1 to 6 (there will be 6 macros)
+ * Value is corresponding value
+ *
+ * For every valid PRCM configuration there should be only one definition of
+ * the same. if values are independent of the board, this definition will be
+ * present in this file if values are dependent on the board, then this should
+ * go into corresponding mem-boardName.h file
+ *
+ * Currently valid part Names are (PART):
+ * M_NAND - Micron NAND
+ */
+#define GPMC_SIZE_256M 0x0
+#define GPMC_SIZE_128M 0x8
+#define GPMC_SIZE_64M 0xC
+#define GPMC_SIZE_32M 0xE
+#define GPMC_SIZE_16M 0xF
+
+#define M_NAND_GPMC_CONFIG1 0x00000800
+#define M_NAND_GPMC_CONFIG2 0x001e1e00
+#define M_NAND_GPMC_CONFIG3 0x001e1e00
+#define M_NAND_GPMC_CONFIG4 0x16051807
+#define M_NAND_GPMC_CONFIG5 0x00151e1e
+#define M_NAND_GPMC_CONFIG6 0x16000f80
+#define M_NAND_GPMC_CONFIG7 0x00000008
+
+/* max number of GPMC Chip Selects */
+#define GPMC_MAX_CS 8
+/* max number of GPMC regs */
+#define GPMC_MAX_REG 7
+
+#define PISMO1_NOR 1
+#define PISMO1_NAND 2
+#define PISMO2_CS0 3
+#define PISMO2_CS1 4
+#define PISMO1_ONENAND 5
+#define DBG_MPDB 6
+#define PISMO2_NAND_CS0 7
+#define PISMO2_NAND_CS1 8
+
+/* make it readable for the gpmc_init */
+#define PISMO1_NOR_BASE FLASH_BASE
+#define PISMO1_NAND_BASE CONFIG_SYS_NAND_BASE
+#define PISMO1_NAND_SIZE GPMC_SIZE_256M
+
+#endif /* endif _MEM_H_ */
--- /dev/null
+/*
+ * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
+ * Rohit Choraria <rohitkc@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_ARCH_OMAP_GPMC_H
+#define __ASM_ARCH_OMAP_GPMC_H
+
+#define GPMC_BUF_EMPTY 0
+#define GPMC_BUF_FULL 1
+
+#define ECCCLEAR (0x1 << 8)
+#define ECCRESULTREG1 (0x1 << 0)
+#define ECCSIZE512BYTE 0xFF
+#define ECCSIZE1 (ECCSIZE512BYTE << 22)
+#define ECCSIZE0 (ECCSIZE512BYTE << 12)
+#define ECCSIZE0SEL (0x000 << 0)
+
+/* Generic ECC Layouts */
+/* Large Page x8 NAND device Layout */
+#ifdef GPMC_NAND_ECC_LP_x8_LAYOUT
+#define GPMC_NAND_HW_ECC_LAYOUT {\
+ .eccbytes = 12,\
+ .eccpos = {1, 2, 3, 4, 5, 6, 7, 8,\
+ 9, 10, 11, 12},\
+ .oobfree = {\
+ {.offset = 13,\
+ .length = 51 } } \
+}
+#endif
+
+/* Large Page x16 NAND device Layout */
+#ifdef GPMC_NAND_ECC_LP_x16_LAYOUT
+#define GPMC_NAND_HW_ECC_LAYOUT {\
+ .eccbytes = 12,\
+ .eccpos = {2, 3, 4, 5, 6, 7, 8, 9,\
+ 10, 11, 12, 13},\
+ .oobfree = {\
+ {.offset = 14,\
+ .length = 50 } } \
+}
+#endif
+
+/* Small Page x8 NAND device Layout */
+#ifdef GPMC_NAND_ECC_SP_x8_LAYOUT
+#define GPMC_NAND_HW_ECC_LAYOUT {\
+ .eccbytes = 3,\
+ .eccpos = {1, 2, 3},\
+ .oobfree = {\
+ {.offset = 4,\
+ .length = 12 } } \
+}
+#endif
+
+/* Small Page x16 NAND device Layout */
+#ifdef GPMC_NAND_ECC_SP_x16_LAYOUT
+#define GPMC_NAND_HW_ECC_LAYOUT {\
+ .eccbytes = 3,\
+ .eccpos = {2, 3, 4},\
+ .oobfree = {\
+ {.offset = 5,\
+ .length = 11 } } \
+}
+#endif
+
+#define GPMC_NAND_HW_BCH4_ECC_LAYOUT {\
+ .eccbytes = 32,\
+ .eccpos = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,\
+ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,\
+ 28, 29, 30, 31, 32, 33},\
+ .oobfree = {\
+ {.offset = 34,\
+ .length = 30 } } \
+}
+
+#define GPMC_NAND_HW_BCH8_ECC_LAYOUT {\
+ .eccbytes = 56,\
+ .eccpos = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,\
+ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,\
+ 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,\
+ 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51,\
+ 52, 53, 54, 55, 56, 57},\
+ .oobfree = {\
+ {.offset = 58,\
+ .length = 6 } } \
+}
+
+#define GPMC_NAND_HW_BCH16_ECC_LAYOUT {\
+ .eccbytes = 104,\
+ .eccpos = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,\
+ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,\
+ 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,\
+ 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51,\
+ 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,\
+ 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75,\
+ 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87,\
+ 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99,\
+ 100, 101, 102, 103, 104, 105},\
+ .oobfree = {\
+ {.offset = 106,\
+ .length = 8 } } \
+}
+#endif /* __ASM_ARCH_OMAP_GPMC_H */
void setup_clocks_for_console(void);
void ddr_pll_config(unsigned int ddrpll_M);
+void sdelay(unsigned long);
+void gpmc_init(void);
+void omap_nand_switch_ecc(int);
#endif
#define ATMEL_PIO_PORTS 4
#define CPU_HAS_PIO3
#define PIO_SCDR_DIV (0x3fff << 0) /* Slow Clock Divider Mask */
+#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
+#define ATMEL_ID_UHP ATMEL_ID_UHPHS
/*
* at91sam9x5 specific prototypes
unsigned long get_i2c_clk(void);
unsigned long get_pwm_clk(void);
unsigned long get_uart_clk(int dev_index);
+unsigned long get_mmc_clk(int dev_index);
void set_mmc_clk(int dev_index, unsigned int div);
unsigned long get_lcd_clk(void);
void set_lcd_clk(void);
void set_mipi_clk(void);
+void set_i2s_clk_source(void);
+int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq);
+int set_epll_clk(unsigned long rate);
+int set_spi_clk(int periph_id, unsigned int rate);
#endif
unsigned int div_iem_l1;
};
+struct exynos4x12_clock {
+ unsigned char res1[0x4200];
+ unsigned int src_leftbus;
+ unsigned char res2[0x1fc];
+ unsigned int mux_stat_leftbus;
+ unsigned char res3[0xfc];
+ unsigned int div_leftbus;
+ unsigned char res4[0xfc];
+ unsigned int div_stat_leftbus;
+ unsigned char res5[0x1fc];
+ unsigned int gate_ip_leftbus;
+ unsigned char res6[0x12c];
+ unsigned int gate_ip_image;
+ unsigned char res7[0xcc];
+ unsigned int clkout_leftbus;
+ unsigned int clkout_leftbus_div_stat;
+ unsigned char res8[0x37f8];
+ unsigned int src_rightbus;
+ unsigned char res9[0x1fc];
+ unsigned int mux_stat_rightbus;
+ unsigned char res10[0xfc];
+ unsigned int div_rightbus;
+ unsigned char res11[0xfc];
+ unsigned int div_stat_rightbus;
+ unsigned char res12[0x1fc];
+ unsigned int gate_ip_rightbus;
+ unsigned char res13[0x15c];
+ unsigned int gate_ip_perir;
+ unsigned char res14[0x9c];
+ unsigned int clkout_rightbus;
+ unsigned int clkout_rightbus_div_stat;
+ unsigned char res15[0x3608];
+ unsigned int epll_lock;
+ unsigned char res16[0xc];
+ unsigned int vpll_lock;
+ unsigned char res17[0xec];
+ unsigned int epll_con0;
+ unsigned int epll_con1;
+ unsigned int epll_con2;
+ unsigned char res18[0x4];
+ unsigned int vpll_con0;
+ unsigned int vpll_con1;
+ unsigned int vpll_con2;
+ unsigned char res19[0xe4];
+ unsigned int src_top0;
+ unsigned int src_top1;
+ unsigned char res20[0x8];
+ unsigned int src_cam;
+ unsigned int src_tv;
+ unsigned int src_mfc;
+ unsigned int src_g3d;
+ unsigned char res21[0x4];
+ unsigned int src_lcd;
+ unsigned int src_isp;
+ unsigned int src_maudio;
+ unsigned int src_fsys;
+ unsigned char res22[0xc];
+ unsigned int src_peril0;
+ unsigned int src_peril1;
+ unsigned int src_cam1;
+ unsigned char res23[0xb4];
+ unsigned int src_mask_top;
+ unsigned char res24[0xc];
+ unsigned int src_mask_cam;
+ unsigned int src_mask_tv;
+ unsigned char res25[0xc];
+ unsigned int src_mask_lcd;
+ unsigned int src_mask_isp;
+ unsigned int src_mask_maudio;
+ unsigned int src_mask_fsys;
+ unsigned char res26[0xc];
+ unsigned int src_mask_peril0;
+ unsigned int src_mask_peril1;
+ unsigned char res27[0xb8];
+ unsigned int mux_stat_top0;
+ unsigned int mux_stat_top1;
+ unsigned char res28[0x10];
+ unsigned int mux_stat_mfc;
+ unsigned int mux_stat_g3d;
+ unsigned char res29[0x28];
+ unsigned int mux_stat_cam1;
+ unsigned char res30[0xb4];
+ unsigned int div_top;
+ unsigned char res31[0xc];
+ unsigned int div_cam;
+ unsigned int div_tv;
+ unsigned int div_mfc;
+ unsigned int div_g3d;
+ unsigned char res32[0x4];
+ unsigned int div_lcd;
+ unsigned int div_isp;
+ unsigned int div_maudio;
+ unsigned int div_fsys0;
+ unsigned int div_fsys1;
+ unsigned int div_fsys2;
+ unsigned int div_fsys3;
+ unsigned int div_peril0;
+ unsigned int div_peril1;
+ unsigned int div_peril2;
+ unsigned int div_peril3;
+ unsigned int div_peril4;
+ unsigned int div_peril5;
+ unsigned int div_cam1;
+ unsigned char res33[0x14];
+ unsigned int div2_ratio;
+ unsigned char res34[0x8c];
+ unsigned int div_stat_top;
+ unsigned char res35[0xc];
+ unsigned int div_stat_cam;
+ unsigned int div_stat_tv;
+ unsigned int div_stat_mfc;
+ unsigned int div_stat_g3d;
+ unsigned char res36[0x4];
+ unsigned int div_stat_lcd;
+ unsigned int div_stat_isp;
+ unsigned int div_stat_maudio;
+ unsigned int div_stat_fsys0;
+ unsigned int div_stat_fsys1;
+ unsigned int div_stat_fsys2;
+ unsigned int div_stat_fsys3;
+ unsigned int div_stat_peril0;
+ unsigned int div_stat_peril1;
+ unsigned int div_stat_peril2;
+ unsigned int div_stat_peril3;
+ unsigned int div_stat_peril4;
+ unsigned int div_stat_peril5;
+ unsigned int div_stat_cam1;
+ unsigned char res37[0x14];
+ unsigned int div2_stat;
+ unsigned char res38[0x29c];
+ unsigned int gate_ip_cam;
+ unsigned int gate_ip_tv;
+ unsigned int gate_ip_mfc;
+ unsigned int gate_ip_g3d;
+ unsigned char res39[0x4];
+ unsigned int gate_ip_lcd;
+ unsigned int gate_ip_isp;
+ unsigned char res40[0x4];
+ unsigned int gate_ip_fsys;
+ unsigned char res41[0x8];
+ unsigned int gate_ip_gps;
+ unsigned int gate_ip_peril;
+ unsigned char res42[0xc];
+ unsigned char res43[0x4];
+ unsigned char res44[0xc];
+ unsigned int gate_block;
+ unsigned char res45[0x8c];
+ unsigned int clkout_cmu_top;
+ unsigned int clkout_cmu_top_div_stat;
+ unsigned char res46[0x3600];
+ unsigned int mpll_lock;
+ unsigned char res47[0xfc];
+ unsigned int mpll_con0;
+ unsigned int mpll_con1;
+ unsigned char res48[0xf0];
+ unsigned int src_dmc;
+ unsigned char res49[0xfc];
+ unsigned int src_mask_dmc;
+ unsigned char res50[0xfc];
+ unsigned int mux_stat_dmc;
+ unsigned char res51[0xfc];
+ unsigned int div_dmc0;
+ unsigned int div_dmc1;
+ unsigned char res52[0xf8];
+ unsigned int div_stat_dmc0;
+ unsigned int div_stat_dmc1;
+ unsigned char res53[0xf8];
+ unsigned int gate_bus_dmc0;
+ unsigned int gate_bus_dmc1;
+ unsigned char res54[0x1f8];
+ unsigned int gate_ip_dmc0;
+ unsigned int gate_ip_dmc1;
+ unsigned char res55[0xf8];
+ unsigned int clkout_cmu_dmc;
+ unsigned int clkout_cmu_dmc_div_stat;
+ unsigned char res56[0x5f8];
+ unsigned int dcgidx_map0;
+ unsigned int dcgidx_map1;
+ unsigned int dcgidx_map2;
+ unsigned char res57[0x14];
+ unsigned int dcgperf_map0;
+ unsigned int dcgperf_map1;
+ unsigned char res58[0x18];
+ unsigned int dvcidx_map;
+ unsigned char res59[0x1c];
+ unsigned int freq_cpu;
+ unsigned int freq_dpm;
+ unsigned char res60[0x18];
+ unsigned int dvsemclk_en;
+ unsigned int maxperf;
+ unsigned char res61[0x8];
+ unsigned int dmc_freq_ctrl;
+ unsigned int dmc_pause_ctrl;
+ unsigned int dddrphy_lock_ctrl;
+ unsigned int c2c_state;
+ unsigned char res62[0x2f60];
+ unsigned int apll_lock;
+ unsigned char res63[0x8];
+ unsigned char res64[0xf4];
+ unsigned int apll_con0;
+ unsigned int apll_con1;
+ unsigned char res65[0xf8];
+ unsigned int src_cpu;
+ unsigned char res66[0x1fc];
+ unsigned int mux_stat_cpu;
+ unsigned char res67[0xfc];
+ unsigned int div_cpu0;
+ unsigned int div_cpu1;
+ unsigned char res68[0xf8];
+ unsigned int div_stat_cpu0;
+ unsigned int div_stat_cpu1;
+ unsigned char res69[0x2f8];
+ unsigned int clk_gate_ip_cpu;
+ unsigned char res70[0xfc];
+ unsigned int clkout_cmu_cpu;
+ unsigned int clkout_cmu_cpu_div_stat;
+ unsigned char res71[0x5f8];
+ unsigned int armclk_stopctrl;
+ unsigned int atclk_stopctrl;
+ unsigned char res72[0x10];
+ unsigned char res73[0x8];
+ unsigned int pwr_ctrl;
+ unsigned int pwr_ctrl2;
+ unsigned char res74[0xd8];
+ unsigned int apll_con0_l8;
+ unsigned int apll_con0_l7;
+ unsigned int apll_con0_l6;
+ unsigned int apll_con0_l5;
+ unsigned int apll_con0_l4;
+ unsigned int apll_con0_l3;
+ unsigned int apll_con0_l2;
+ unsigned int apll_con0_l1;
+ unsigned int iem_control;
+ unsigned char res75[0xdc];
+ unsigned int apll_con1_l8;
+ unsigned int apll_con1_l7;
+ unsigned int apll_con1_l6;
+ unsigned int apll_con1_l5;
+ unsigned int apll_con1_l4;
+ unsigned int apll_con1_l3;
+ unsigned int apll_con1_l2;
+ unsigned int apll_con1_l1;
+ unsigned char res76[0xe0];
+ unsigned int div_iem_l8;
+ unsigned int div_iem_l7;
+ unsigned int div_iem_l6;
+ unsigned int div_iem_l5;
+ unsigned int div_iem_l4;
+ unsigned int div_iem_l3;
+ unsigned int div_iem_l2;
+ unsigned int div_iem_l1;
+ unsigned char res77[0xe0];
+ unsigned int l2_status;
+ unsigned char res78[0xc];
+ unsigned int cpu_status;
+ unsigned char res79[0xc];
+ unsigned int ptm_status;
+ unsigned char res80[0x2edc];
+ unsigned int div_isp0;
+ unsigned int div_isp1;
+ unsigned char res81[0xf8];
+ unsigned int div_stat_isp0;
+ unsigned int div_stat_isp1;
+ unsigned char res82[0x3f8];
+ unsigned int gate_ip_isp0;
+ unsigned int gate_ip_isp1;
+ unsigned char res83[0x1f8];
+ unsigned int clkout_cmu_isp;
+ unsigned int clkout_cmu_ispd_div_stat;
+ unsigned char res84[0xf8];
+ unsigned int cmu_isp_spar0;
+ unsigned int cmu_isp_spar1;
+ unsigned int cmu_isp_spar2;
+ unsigned int cmu_isp_spar3;
+};
+
struct exynos5_clock {
unsigned int apll_lock;
unsigned char res1[0xfc];
unsigned int pll_div2_sel;
unsigned char res123[0xf5d8];
};
+
+/* structure for epll configuration used in audio clock configuration */
+struct set_epll_con_val {
+ unsigned int freq_out; /* frequency out */
+ unsigned int en_lock_det; /* enable lock detect */
+ unsigned int m_div; /* m divider value */
+ unsigned int p_div; /* p divider value */
+ unsigned int s_div; /* s divider value */
+ unsigned int k_dsm; /* k value of delta signal modulator */
+};
#endif
#define MPLL_FOUT_SEL_SHIFT 4
+#define EXYNOS5_EPLLCON0_LOCKED_SHIFT 29 /* EPLL Locked bit position*/
+#define TIMEOUT_EPLL_LOCK 1000
+
+#define AUDIO_0_RATIO_MASK 0x0f
+#define AUDIO_1_RATIO_MASK 0x0f
+
+#define AUDIO1_SEL_MASK 0xf
+#define CLK_SRC_SCLK_EPLL 0x7
+
+/* CON0 bit-fields */
+#define EPLL_CON0_MDIV_MASK 0x1ff
+#define EPLL_CON0_PDIV_MASK 0x3f
+#define EPLL_CON0_SDIV_MASK 0x7
+#define EPLL_CON0_MDIV_SHIFT 16
+#define EPLL_CON0_PDIV_SHIFT 8
+#define EPLL_CON0_SDIV_SHIFT 0
+#define EPLL_CON0_LOCK_DET_EN_SHIFT 28
+#define EPLL_CON0_LOCK_DET_EN_MASK 1
+
#define MPLL_FOUT_SEL_MASK 0x1
#define BPLL_FOUT_SEL_SHIFT 0
#define BPLL_FOUT_SEL_MASK 0x1
#define EXYNOS_CPU_NAME "Exynos"
#define EXYNOS4_ADDR_BASE 0x10000000
-/* EXYNOS4 */
+/* EXYNOS4 Common*/
#define EXYNOS4_I2C_SPACING 0x10000
#define EXYNOS4_GPIO_PART3_BASE 0x03860000
#define EXYNOS4_UART_BASE 0x13800000
#define EXYNOS4_I2C_BASE 0x13860000
#define EXYNOS4_ADC_BASE 0x13910000
+#define EXYNOS4_SPI_BASE 0x13920000
#define EXYNOS4_PWMTIMER_BASE 0x139D0000
#define EXYNOS4_MODEM_BASE 0x13A00000
#define EXYNOS4_USBPHY_CONTROL 0x10020704
+#define EXYNOS4_I2S_BASE 0xE2100000
#define EXYNOS4_GPIO_PART4_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4_DP_BASE DEVICE_NOT_AVAILABLE
-
-/* EXYNOS5 */
+#define EXYNOS4_SPI_ISP_BASE DEVICE_NOT_AVAILABLE
+
+/* EXYNOS4X12 */
+#define EXYNOS4X12_GPIO_PART3_BASE 0x03860000
+#define EXYNOS4X12_PRO_ID 0x10000000
+#define EXYNOS4X12_SYSREG_BASE 0x10010000
+#define EXYNOS4X12_POWER_BASE 0x10020000
+#define EXYNOS4X12_SWRESET 0x10020400
+#define EXYNOS4X12_USBPHY_CONTROL 0x10020704
+#define EXYNOS4X12_CLOCK_BASE 0x10030000
+#define EXYNOS4X12_SYSTIMER_BASE 0x10050000
+#define EXYNOS4X12_WATCHDOG_BASE 0x10060000
+#define EXYNOS4X12_DMC0_BASE 0x10600000
+#define EXYNOS4X12_DMC1_BASE 0x10610000
+#define EXYNOS4X12_GPIO_PART4_BASE 0x106E0000
+#define EXYNOS4X12_GPIO_PART2_BASE 0x11000000
+#define EXYNOS4X12_GPIO_PART1_BASE 0x11400000
+#define EXYNOS4X12_FIMD_BASE 0x11C00000
+#define EXYNOS4X12_MIPI_DSIM_BASE 0x11C80000
+#define EXYNOS4X12_USBOTG_BASE 0x12480000
+#define EXYNOS4X12_MMC_BASE 0x12510000
+#define EXYNOS4X12_SROMC_BASE 0x12570000
+#define EXYNOS4X12_USB_HOST_EHCI_BASE 0x12580000
+#define EXYNOS4X12_USBPHY_BASE 0x125B0000
+#define EXYNOS4X12_UART_BASE 0x13800000
+#define EXYNOS4X12_I2C_BASE 0x13860000
+#define EXYNOS4X12_PWMTIMER_BASE 0x139D0000
+
+#define EXYNOS4X12_ADC_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_DP_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_MODEM_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_I2S_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_SPI_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_SPI_ISP_BASE DEVICE_NOT_AVAILABLE
+
+/* EXYNOS5 Common*/
#define EXYNOS5_I2C_SPACING 0x10000
#define EXYNOS5_GPIO_PART4_BASE 0x03860000
#define EXYNOS5_SROMC_BASE 0x12250000
#define EXYNOS5_UART_BASE 0x12C00000
#define EXYNOS5_I2C_BASE 0x12C60000
+#define EXYNOS5_SPI_BASE 0x12D20000
+#define EXYNOS5_I2S_BASE 0x12D60000
#define EXYNOS5_PWMTIMER_BASE 0x12DD0000
+#define EXYNOS5_SPI_ISP_BASE 0x131A0000
#define EXYNOS5_GPIO_PART2_BASE 0x13400000
#define EXYNOS5_FIMD_BASE 0x14400000
#define EXYNOS5_DP_BASE 0x145B0000
IS_SAMSUNG_TYPE(exynos4, 0x4)
IS_SAMSUNG_TYPE(exynos5, 0x5)
+#define IS_EXYNOS_TYPE(type, id) \
+static inline int proid_is_##type(void) \
+{ \
+ return s5p_cpu_id == id; \
+}
+
+IS_EXYNOS_TYPE(exynos4210, 0x4210)
+IS_EXYNOS_TYPE(exynos4412, 0x4412)
+IS_EXYNOS_TYPE(exynos5250, 0x5250)
+
#define SAMSUNG_BASE(device, base) \
static inline unsigned int samsung_get_base_##device(void) \
{ \
- if (cpu_is_exynos4()) \
+ if (cpu_is_exynos4()) { \
+ if (proid_is_exynos4412()) \
+ return EXYNOS4X12_##base; \
return EXYNOS4_##base; \
- else if (cpu_is_exynos5()) \
+ } else if (cpu_is_exynos5()) { \
return EXYNOS5_##base; \
- else \
- return 0; \
+ } \
+ return 0; \
}
SAMSUNG_BASE(adc, ADC_BASE)
SAMSUNG_BASE(sysreg, SYSREG_BASE)
SAMSUNG_BASE(fimd, FIMD_BASE)
SAMSUNG_BASE(i2c, I2C_BASE)
+SAMSUNG_BASE(i2s, I2S_BASE)
SAMSUNG_BASE(mipi_dsim, MIPI_DSIM_BASE)
SAMSUNG_BASE(gpio_part1, GPIO_PART1_BASE)
SAMSUNG_BASE(gpio_part2, GPIO_PART2_BASE)
SAMSUNG_BASE(usb_otg, USBOTG_BASE)
SAMSUNG_BASE(watchdog, WATCHDOG_BASE)
SAMSUNG_BASE(power, POWER_BASE)
+SAMSUNG_BASE(spi, SPI_BASE)
+SAMSUNG_BASE(spi_isp, SPI_ISP_BASE)
#endif
#endif /* _EXYNOS4_CPU_H */
}
#endif
+void exynos_set_dp_platform_data(struct exynos_dp_platform_data *pd);
+
#endif /* _DP_INFO_H */
struct s5p_gpio_bank z;
};
+struct exynos4x12_gpio_part1 {
+ struct s5p_gpio_bank a0;
+ struct s5p_gpio_bank a1;
+ struct s5p_gpio_bank b;
+ struct s5p_gpio_bank c0;
+ struct s5p_gpio_bank c1;
+ struct s5p_gpio_bank d0;
+ struct s5p_gpio_bank d1;
+ struct s5p_gpio_bank res1[0x5];
+ struct s5p_gpio_bank f0;
+ struct s5p_gpio_bank f1;
+ struct s5p_gpio_bank f2;
+ struct s5p_gpio_bank f3;
+ struct s5p_gpio_bank res2[0x2];
+ struct s5p_gpio_bank j0;
+ struct s5p_gpio_bank j1;
+};
+
+struct exynos4x12_gpio_part2 {
+ struct s5p_gpio_bank res1[0x2];
+ struct s5p_gpio_bank k0;
+ struct s5p_gpio_bank k1;
+ struct s5p_gpio_bank k2;
+ struct s5p_gpio_bank k3;
+ struct s5p_gpio_bank l0;
+ struct s5p_gpio_bank l1;
+ struct s5p_gpio_bank l2;
+ struct s5p_gpio_bank y0;
+ struct s5p_gpio_bank y1;
+ struct s5p_gpio_bank y2;
+ struct s5p_gpio_bank y3;
+ struct s5p_gpio_bank y4;
+ struct s5p_gpio_bank y5;
+ struct s5p_gpio_bank y6;
+ struct s5p_gpio_bank res2[0x3];
+ struct s5p_gpio_bank m0;
+ struct s5p_gpio_bank m1;
+ struct s5p_gpio_bank m2;
+ struct s5p_gpio_bank m3;
+ struct s5p_gpio_bank m4;
+ struct s5p_gpio_bank res3[0x48];
+ struct s5p_gpio_bank x0;
+ struct s5p_gpio_bank x1;
+ struct s5p_gpio_bank x2;
+ struct s5p_gpio_bank x3;
+};
+
+struct exynos4x12_gpio_part3 {
+ struct s5p_gpio_bank z;
+};
+
+struct exynos4x12_gpio_part4 {
+ struct s5p_gpio_bank v0;
+ struct s5p_gpio_bank v1;
+ struct s5p_gpio_bank res1[0x1];
+ struct s5p_gpio_bank v2;
+ struct s5p_gpio_bank v3;
+ struct s5p_gpio_bank res2[0x1];
+ struct s5p_gpio_bank v4;
+};
+
struct exynos5_gpio_part1 {
struct s5p_gpio_bank a0;
struct s5p_gpio_bank a1;
- EXYNOS4_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
* GPIO_PER_BANK) + pin) + EXYNOS4_GPIO_PART1_MAX)
+#define exynos4x12_gpio_part1_get_nr(bank, pin) \
+ ((((((unsigned int) &(((struct exynos4x12_gpio_part1 *) \
+ EXYNOS4X12_GPIO_PART1_BASE)->bank)) \
+ - EXYNOS4X12_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \
+ * GPIO_PER_BANK) + pin)
+
+#define EXYNOS4X12_GPIO_PART1_MAX ((sizeof(struct exynos4x12_gpio_part1) \
+ / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
+
+#define exynos4x12_gpio_part2_get_nr(bank, pin) \
+ (((((((unsigned int) &(((struct exynos4x12_gpio_part2 *) \
+ EXYNOS4X12_GPIO_PART2_BASE)->bank)) \
+ - EXYNOS4X12_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
+ * GPIO_PER_BANK) + pin) + EXYNOS4X12_GPIO_PART1_MAX)
+
+#define EXYNOS4X12_GPIO_PART2_MAX ((sizeof(struct exynos4x12_gpio_part2) \
+ / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
+
+#define exynos4x12_gpio_part3_get_nr(bank, pin) \
+ (((((((unsigned int) &(((struct exynos4x12_gpio_part3 *) \
+ EXYNOS4X12_GPIO_PART3_BASE)->bank)) \
+ - EXYNOS4X12_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \
+ * GPIO_PER_BANK) + pin) + EXYNOS4X12_GPIO_PART2_MAX)
+
#define exynos5_gpio_part1_get_nr(bank, pin) \
((((((unsigned int) &(((struct exynos5_gpio_part1 *) \
EXYNOS5_GPIO_PART1_BASE)->bank)) \
return 0;
}
+static inline unsigned int s5p_gpio_part_max(int nr)
+{
+ if (cpu_is_exynos5()) {
+ if (nr < EXYNOS5_GPIO_PART1_MAX)
+ return 0;
+ else if (nr < EXYNOS5_GPIO_PART2_MAX)
+ return EXYNOS5_GPIO_PART1_MAX;
+ else
+ return EXYNOS5_GPIO_PART2_MAX;
+
+ } else if (cpu_is_exynos4()) {
+ if (nr < EXYNOS4_GPIO_PART1_MAX)
+ return 0;
+ else
+ return EXYNOS4_GPIO_PART1_MAX;
+ }
+
+ return 0;
+}
#endif
/* Pin configurations */
--- /dev/null
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ * R. Chandrasekar <rcsekar@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __I2S_REGS_H__
+#define __I2S_REGS_H__
+
+#define CON_TXFIFO_FULL (1 << 8)
+#define CON_TXCH_PAUSE (1 << 4)
+#define CON_ACTIVE (1 << 0)
+
+#define MOD_BLCP_SHIFT 24
+#define MOD_BLCP_16BIT (0 << MOD_BLCP_SHIFT)
+#define MOD_BLCP_8BIT (1 << MOD_BLCP_SHIFT)
+#define MOD_BLCP_24BIT (2 << MOD_BLCP_SHIFT)
+#define MOD_BLCP_MASK (3 << MOD_BLCP_SHIFT)
+
+#define MOD_BLC_16BIT (0 << 13)
+#define MOD_BLC_8BIT (1 << 13)
+#define MOD_BLC_24BIT (2 << 13)
+#define MOD_BLC_MASK (3 << 13)
+
+#define MOD_SLAVE (1 << 11)
+#define MOD_MASK (3 << 8)
+#define MOD_LR_LLOW (0 << 7)
+#define MOD_LR_RLOW (1 << 7)
+#define MOD_SDF_IIS (0 << 5)
+#define MOD_SDF_MSB (1 << 5)
+#define MOD_SDF_LSB (2 << 5)
+#define MOD_SDF_MASK (3 << 5)
+#define MOD_RCLK_256FS (0 << 3)
+#define MOD_RCLK_512FS (1 << 3)
+#define MOD_RCLK_384FS (2 << 3)
+#define MOD_RCLK_768FS (3 << 3)
+#define MOD_RCLK_MASK (3 << 3)
+#define MOD_BCLK_32FS (0 << 1)
+#define MOD_BCLK_48FS (1 << 1)
+#define MOD_BCLK_16FS (2 << 1)
+#define MOD_BCLK_24FS (3 << 1)
+#define MOD_BCLK_MASK (3 << 1)
+
+#define MOD_CDCLKCON (1 << 12)
+
+#define FIC_TXFLUSH (1 << 15)
+#define FIC_RXFLUSH (1 << 7)
+
+#endif /* __I2S_REGS_H__ */
void (*mipi_display_on)(struct mipi_dsim_device *dsim_dev);
};
+#ifdef CONFIG_EXYNOS_MIPI_DSIM
int exynos_mipi_dsi_init(void);
+#else
+static inline int exynos_mipi_dsi_init(void)
+{
+ return 0;
+}
+#endif
/*
* register mipi_dsim_lcd_driver object defined by lcd panel driver
#define __ASM_ARM_ARCH_PERIPH_H
/*
- * Peripherals requiring clock/pinmux configuration. List will
+ * Peripherals required for pinmux configuration. List will
* grow with support for more devices getting added.
+ * Numbering based on interrupt table.
*
*/
enum periph_id {
- PERIPH_ID_I2C0,
+ PERIPH_ID_UART0 = 51,
+ PERIPH_ID_UART1,
+ PERIPH_ID_UART2,
+ PERIPH_ID_UART3,
+ PERIPH_ID_I2C0 = 56,
PERIPH_ID_I2C1,
PERIPH_ID_I2C2,
PERIPH_ID_I2C3,
PERIPH_ID_I2C5,
PERIPH_ID_I2C6,
PERIPH_ID_I2C7,
- PERIPH_ID_SDMMC0,
+ PERIPH_ID_SPI0 = 68,
+ PERIPH_ID_SPI1,
+ PERIPH_ID_SPI2,
+ PERIPH_ID_SDMMC0 = 75,
PERIPH_ID_SDMMC1,
PERIPH_ID_SDMMC2,
PERIPH_ID_SDMMC3,
- PERIPH_ID_SROMC,
- PERIPH_ID_UART0,
- PERIPH_ID_UART1,
- PERIPH_ID_UART2,
- PERIPH_ID_UART3,
+ PERIPH_ID_I2S1 = 99,
+
+ /* Since following peripherals do
+ * not have shared peripheral interrupts (SPIs)
+ * they are numbered arbitiraly after the maximum
+ * SPIs Exynos has (128)
+ */
+ PERIPH_ID_SROMC = 128,
+ PERIPH_ID_SPI3,
+ PERIPH_ID_SPI4,
+ PERIPH_ID_SDMMC4,
PERIPH_ID_COUNT,
PERIPH_ID_NONE = -1,
*/
int exynos_pinmux_config(int peripheral, int flags);
+/**
+ * Decode the peripheral id using the interrpt numbers.
+ *
+ * @param blob Device tree blob
+ * @param node FDT I2C node to find
+ * @return peripheral id if ok, PERIPH_ID_NONE on error
+ */
+int pinmux_decode_periph_id(const void *blob, int node);
#endif
--- /dev/null
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ * Rajeshwari Shinde <rajeshwari.s@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#ifndef __SOUND_ARCH_H__
+#define __SOUND_ARCH_H__
+
+/* I2S values */
+#define I2S_PLL_CLK 192000000
+#define I2S_SAMPLING_RATE 48000
+#define I2S_BITS_PER_SAMPLE 16
+#define I2S_CHANNELS 2
+#define I2S_RFS 256
+#define I2S_BFS 32
+
+/* I2C values */
+#define AUDIO_I2C_BUS 1
+#define AUDIO_I2C_REG 0x1a
+
+/* Audio Codec */
+#define AUDIO_CODEC "wm8994"
+
+#define AUDIO_COMPAT 1
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2012 SAMSUNG Electronics
+ * Padmavathi Venna <padma.v@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_EXYNOS_COMMON_SPI_H_
+#define __ASM_ARCH_EXYNOS_COMMON_SPI_H_
+
+#ifndef __ASSEMBLY__
+
+/* SPI peripheral register map; padded to 64KB */
+struct exynos_spi {
+ unsigned int ch_cfg; /* 0x00 */
+ unsigned char reserved0[4];
+ unsigned int mode_cfg; /* 0x08 */
+ unsigned int cs_reg; /* 0x0c */
+ unsigned char reserved1[4];
+ unsigned int spi_sts; /* 0x14 */
+ unsigned int tx_data; /* 0x18 */
+ unsigned int rx_data; /* 0x1c */
+ unsigned int pkt_cnt; /* 0x20 */
+ unsigned char reserved2[4];
+ unsigned char reserved3[4];
+ unsigned int fb_clk; /* 0x2c */
+ unsigned char padding[0xffd0];
+};
+
+#define EXYNOS_SPI_MAX_FREQ 50000000
+
+#define SPI_TIMEOUT_MS 10
+
+/* SPI_CHCFG */
+#define SPI_CH_HS_EN (1 << 6)
+#define SPI_CH_RST (1 << 5)
+#define SPI_SLAVE_MODE (1 << 4)
+#define SPI_CH_CPOL_L (1 << 3)
+#define SPI_CH_CPHA_B (1 << 2)
+#define SPI_RX_CH_ON (1 << 1)
+#define SPI_TX_CH_ON (1 << 0)
+
+/* SPI_MODECFG */
+#define SPI_MODE_CH_WIDTH_WORD (0x2 << 29)
+#define SPI_MODE_BUS_WIDTH_WORD (0x2 << 17)
+
+/* SPI_CSREG */
+#define SPI_SLAVE_SIG_INACT (1 << 0)
+
+/* SPI_STS */
+#define SPI_ST_TX_DONE (1 << 25)
+#define SPI_FIFO_LVL_MASK 0x1ff
+#define SPI_TX_LVL_OFFSET 6
+#define SPI_RX_LVL_OFFSET 15
+
+/* Feedback Delay */
+#define SPI_CLK_BYPASS (0 << 0)
+#define SPI_FB_DELAY_90 (1 << 0)
+#define SPI_FB_DELAY_180 (2 << 0)
+#define SPI_FB_DELAY_270 (3 << 0)
+
+/* Packet Count */
+#define SPI_PACKET_CNT_EN (1 << 16)
+
+#endif /* __ASSEMBLY__ */
+#endif
/* Configure the Band Width and Bank Control Regs for required SROMC Bank */
void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf);
+enum {
+ FDT_SROM_PMC,
+ FDT_SROM_TACP,
+ FDT_SROM_TAH,
+ FDT_SROM_TCOH,
+ FDT_SROM_TACC,
+ FDT_SROM_TCOS,
+ FDT_SROM_TACS,
+
+ FDT_SROM_TIMING_COUNT,
+};
+
+struct fdt_sromc {
+ u8 bank; /* srom bank number */
+ u8 width; /* bus width in bytes */
+ unsigned int timing[FDT_SROM_TIMING_COUNT]; /* timing parameters */
+};
+
#endif /* __ASM_ARCH_SROMC_H_ */
| (attr << 8) | (kw_winctrl_calcsize(size) << 16))
#define KWGBE_PORT_SERIAL_CONTROL1_REG(_x) \
- ((_x ? KW_EGIGA0_BASE : KW_EGIGA1_BASE) + 0x44c)
+ ((_x ? KW_EGIGA1_BASE : KW_EGIGA0_BASE) + 0x44c)
#define KW_REG_PCIE_DEVID (KW_REG_PCIE_BASE + 0x00)
#define KW_REG_PCIE_REVID (KW_REG_PCIE_BASE + 0x08)
#define MPP_MAX 49
-void kirkwood_mpp_conf(u32 *mpp_list, u32 *mpp_save);
+void kirkwood_mpp_conf(const u32 *mpp_list, u32 *mpp_save);
#endif
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/types.h>
-#ifdef CONFIG_FEC_MXC
-extern void mx25_fec_init_pins(void);
-#endif
-
/* Clock Control Module (CCM) registers */
struct ccm_regs {
u32 mpctl; /* Core PLL Control */
#define IMX_RTIC_BASE (0x53FEC000)
#define IMX_IIM_BASE (0x53FF0000)
#define IMX_USB_BASE (0x53FF4000)
+#define IMX_USB_PORT_OFFSET 0x200
#define IMX_CSI_BASE (0x53FF8000)
#define IMX_DRYICE_BASE (0x53FFC000)
#define _SYS_PROTO_H_
void mx25_uart1_init_pins(void);
+#if defined CONFIG_FEC_MXC
+extern void mx25_fec_init_pins(void);
+#endif
#endif
void mx31_uart1_hw_init(void);
void mx31_uart2_hw_init(void);
void mx31_spi2_hw_init(void);
-void mxc_hw_watchdog_enable(void);
-void mxc_hw_watchdog_reset(void);
#endif /* __ASM_ARCH_CLOCK_H */
u32 test;
};
-/* Watchdog Timer (WDOG) registers */
-#define WDOG_ENABLE (1 << 2)
-#define WDOG_WT_SHIFT 8
-#define WDOG_WDZST (1 << 0)
-
-struct wdog_regs {
- u16 wcr; /* Control */
- u16 wsr; /* Service */
- u16 wrsr; /* Reset Status */
-};
-
/* IIM Control Registers */
struct iim_regs {
u32 iim_stat;
#define ARM_PPMRR 0x40000015
-#define WDOG_BASE 0x53FDC000
+#define WDOG1_BASE_ADDR 0x53FDC000
/*
* GPIO
#define MX31_AIPS1_BASE_ADDR 0x43f00000
#define IMX_USB_BASE (MX31_AIPS1_BASE_ADDR + 0x88000)
-
-/* USB portsc */
-/* values for portsc field */
-#define MXC_EHCI_PHY_LOW_POWER_SUSPEND (1 << 23)
-#define MXC_EHCI_FORCE_FS (1 << 24)
-#define MXC_EHCI_UTMI_8BIT (0 << 28)
-#define MXC_EHCI_UTMI_16BIT (1 << 28)
-#define MXC_EHCI_SERIAL (1 << 29)
-#define MXC_EHCI_MODE_UTMI (0 << 30)
-#define MXC_EHCI_MODE_PHILIPS (1 << 30)
-#define MXC_EHCI_MODE_ULPI (2 << 30)
-#define MXC_EHCI_MODE_SERIAL (3 << 30)
-
-/* values for flags field */
-#define MXC_EHCI_INTERFACE_DIFF_UNI (0 << 0)
-#define MXC_EHCI_INTERFACE_DIFF_BI (1 << 0)
-#define MXC_EHCI_INTERFACE_SINGLE_UNI (2 << 0)
-#define MXC_EHCI_INTERFACE_SINGLE_BI (3 << 0)
-#define MXC_EHCI_INTERFACE_MASK (0xf)
-
-#define MXC_EHCI_POWER_PINS_ENABLED (1 << 5)
-#define MXC_EHCI_TTL_ENABLED (1 << 6)
-
-#define MXC_EHCI_INTERNAL_PHY (1 << 7)
-#define MXC_EHCI_IPPUE_DOWN (1 << 8)
-#define MXC_EHCI_IPPUE_UP (1 << 9)
+#define IMX_USB_PORT_OFFSET 0x200
/*
* CSPI register definitions
#define IRAM_BASE_ADDR 0x10000000 /* internal ram */
#define IRAM_SIZE 0x00020000 /* 128 KB */
+#define LOW_LEVEL_SRAM_STACK 0x1001E000
+
/*
* AIPS 1
*/
#define GPIO2_BASE_ADDR 0x53FD0000
#define SDMA_BASE_ADDR 0x53FD4000
#define RTC_BASE_ADDR 0x53FD8000
-#define WDOG_BASE_ADDR 0x53FDC000
+#define WDOG1_BASE_ADDR 0x53FDC000
#define PWM_BASE_ADDR 0x53FE0000
#define RTIC_BASE_ADDR 0x53FEC000
#define IIM_BASE_ADDR 0x53FF0000
+#define IMX_USB_BASE 0x53FF4000
+#define IMX_USB_PORT_OFFSET 0x400
#define IMX_CCM_BASE CCM_BASE_ADDR
u32 test;
};
-/* Watchdog Timer (WDOG) registers */
-struct wdog_regs {
- u16 wcr; /* Control */
- u16 wsr; /* Service */
- u16 wrsr; /* Reset Status */
- u16 wicr; /* Interrupt Control */
- u16 wmcr; /* Misc Control */
-};
-
struct esdc_regs {
u32 esdctl0;
u32 esdcfg0;
--- /dev/null
+/*
+ * (C) Copyright 2008
+ * Texas Instruments, <www.ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation's version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef MMC_HOST_DEF_H
+#define MMC_HOST_DEF_H
+
+/* Driver definitions */
+#define MMCSD_SECTOR_SIZE 512
+
+#endif /* MMC_HOST_DEF_H */
--- /dev/null
+/*
+ * (C) Copyright 2012
+ * Texas Instruments, <www.ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _ASM_ARCH_SPL_H_
+#define _ASM_SPL_H_
+
+#define BOOT_DEVICE_NONE 0
+#define BOOT_DEVICE_XIP 1
+#define BOOT_DEVICE_XIPWAIT 2
+#define BOOT_DEVICE_NAND 3
+#define BOOT_DEVICE_ONE_NAND 4
+#define BOOT_DEVICE_MMC1 5
+#define BOOT_DEVICE_MMC2 6
+#define BOOT_DEVICE_MMC2_2 7
+#define BOOT_DEVICE_NOR 8
+#define BOOT_DEVICE_I2C 9
+#define BOOT_DEVICE_SPI 10
+
+#endif
#define _SYS_PROTO_H_
u32 get_cpu_rev(void);
+void mx3_setup_sdram_bank(u32 start_address, u32 ddr2_config,
+ u32 row, u32 col, u32 dsize, u32 refresh);
#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev)
#endif
*/
#define WBED 1
-/*
- * WEIM WCR
- */
-#define BCM 1
-#define GBCD(x) (((x) & 0x3) << 1)
-#define INTEN (1 << 4)
-#define INTPOL (1 << 5)
-#define WDOG_EN (1 << 8)
-#define WDOG_LIMIT(x) (((x) & 0x3) << 9)
-
#define CS0_128 0
#define CS0_64M_CS1_64M 1
#define CS0_64M_CS1_32M_CS2_32M 2
MX53_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT,
MX53_CSPI_IPP_IND_MISO_SELECT_INPUT,
MX53_CSPI_IPP_IND_MOSI_SELECT_INPUT,
+ MX53_CSPI_IPP_IND_SS_B_0_SELECT_INPUT,
MX53_CSPI_IPP_IND_SS_B_1_SELECT_INPUT,
MX53_CSPI_IPP_IND_SS_B_2_SELECT_INPUT,
MX53_CSPI_IPP_IND_SS_B_3_SELECT_INPUT,
- MX53_CSPI_IPP_IND_SS_B_4_SELECT_INPUT,
MX53_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT,
MX53_ECSPI1_IPP_IND_MISO_SELECT_INPUT,
MX53_ECSPI1_IPP_IND_MOSI_SELECT_INPUT,
+ MX53_ECSPI1_IPP_IND_SS_B_0_SELECT_INPUT,
MX53_ECSPI1_IPP_IND_SS_B_1_SELECT_INPUT,
MX53_ECSPI1_IPP_IND_SS_B_2_SELECT_INPUT,
MX53_ECSPI1_IPP_IND_SS_B_3_SELECT_INPUT,
- MX53_ECSPI1_IPP_IND_SS_B_4_SELECT_INPUT,
MX53_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT,
MX53_ECSPI2_IPP_IND_MISO_SELECT_INPUT,
MX53_ECSPI2_IPP_IND_MOSI_SELECT_INPUT,
+ MX53_ECSPI2_IPP_IND_SS_B_0_SELECT_INPUT,
MX53_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT,
- MX53_ECSPI2_IPP_IND_SS_B_2_SELECT_INPUT,
MX53_ESAI1_IPP_IND_FSR_SELECT_INPUT,
MX53_ESAI1_IPP_IND_FST_SELECT_INPUT,
MX53_ESAI1_IPP_IND_HCKR_SELECT_INPUT,
#ifndef _SYS_PROTO_H_
#define _SYS_PROTO_H_
-u32 get_cpu_rev(void);
+#define MXC_CPU_MX51 0x51
+#define MXC_CPU_MX53 0x53
+#define MXC_CPU_MX6SL 0x60
+#define MXC_CPU_MX6DL 0x61
+#define MXC_CPU_MX6SOLO 0x62
+#define MXC_CPU_MX6Q 0x63
+
#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev)
+u32 get_cpu_rev(void);
+unsigned imx_ddr_size(void);
void sdelay(unsigned long);
void set_chipselect_size(int const);
u32 usb2_misc_clr; /* 0x258 */
u32 usb2_misc_tog; /* 0x25c */
u32 digprog; /* 0x260 */
+ u32 reserved1[7];
+ u32 digprog_sololite; /* 0x280 */
};
#define ANATOP_PFD_480_PFD0_FRAC_SHIFT 0
--- /dev/null
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+
+#ifndef __ASM_ARCH_MX6_MX6DL_PINS_H__
+#define __ASM_ARCH_MX6_MX6DL_PINS_H__
+
+#include <asm/imx-common/iomux-v3.h>
+
+/* Use to set PAD control */
+#define PAD_CTL_HYS (1 << 16)
+#define PAD_CTL_PUS_100K_DOWN (0 << 14)
+#define PAD_CTL_PUS_47K_UP (1 << 14)
+#define PAD_CTL_PUS_100K_UP (2 << 14)
+#define PAD_CTL_PUS_22K_UP (3 << 14)
+
+#define PAD_CTL_PUE (1 << 13)
+#define PAD_CTL_PKE (1 << 12)
+#define PAD_CTL_ODE (1 << 11)
+#define PAD_CTL_SPEED_LOW (1 << 6)
+#define PAD_CTL_SPEED_MED (2 << 6)
+#define PAD_CTL_SPEED_HIGH (3 << 6)
+#define PAD_CTL_DSE_DISABLE (0 << 3)
+#define PAD_CTL_DSE_240ohm (1 << 3)
+#define PAD_CTL_DSE_120ohm (2 << 3)
+#define PAD_CTL_DSE_80ohm (3 << 3)
+#define PAD_CTL_DSE_60ohm (4 << 3)
+#define PAD_CTL_DSE_48ohm (5 << 3)
+#define PAD_CTL_DSE_40ohm (6 << 3)
+#define PAD_CTL_DSE_34ohm (7 << 3)
+#define PAD_CTL_SRE_FAST (1 << 0)
+#define PAD_CTL_SRE_SLOW (0 << 0)
+
+#define IOMUX_CONFIG_SION 0x10
+#define NO_MUX_I 0
+#define NO_PAD_I 0
+enum {
+ MX6DL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK = IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6DL_PAD_DI0_PIN15__IPU1_DI0_PIN15 = IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6DL_PAD_DI0_PIN2__IPU1_DI0_PIN2 = IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6DL_PAD_DI0_PIN3__IPU1_DI0_PIN3 = IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6DL_PAD_DI0_PIN4__GPIO_4_20 = IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6DL_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 = IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6DL_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 = IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6DL_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 = IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6DL_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 = IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6DL_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 = IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6DL_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 = IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6DL_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 = IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6DL_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 = IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6DL_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 = IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6DL_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 = IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6DL_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 = IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6DL_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 = IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6DL_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 = IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6DL_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 = IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6DL_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 = IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6DL_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 = IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6DL_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 = IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6DL_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 = IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6DL_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 = IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6DL_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 = IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6DL_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 = IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6DL_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 = IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6DL_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 = IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6DL_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 = IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+ MX6DL_PAD_EIM_D16__ECSPI1_SCLK = IOMUX_PAD(0x0514, 0x0144, 1, 0x07D8, 2, 0),
+ MX6DL_PAD_EIM_D17__ECSPI1_MISO = IOMUX_PAD(0x0518, 0x0148, 1, 0x07DC, 2, 0),
+ MX6DL_PAD_EIM_D18__ECSPI1_MOSI = IOMUX_PAD(0x051C, 0x014C, 1, 0x07E0, 2, 0),
+ MX6DL_PAD_EIM_D19__GPIO_3_19 = IOMUX_PAD(0x0520, 0x0150, 5, 0x0000, 0, 0),
+ MX6DL_PAD_EIM_D21__GPIO_3_21 = IOMUX_PAD(0x0528, 0x0158, 5, 0x0000, 0, 0),
+ MX6DL_PAD_EIM_D21__I2C1_SCL = IOMUX_PAD(0x0528, 0x0158, 6 | IOMUX_CONFIG_SION, 0x0868, 1, 0),
+ MX6DL_PAD_EIM_D23__GPIO_3_23 = IOMUX_PAD(0x0530, 0x0160, 5, 0x0000, 0, 0),
+ MX6DL_PAD_EIM_D26__UART2_TXD = IOMUX_PAD(0x053C, 0x016C, 4, 0x0000, 0, 0),
+ MX6DL_PAD_EIM_D27__UART2_RXD = IOMUX_PAD(0x0540, 0x0170, 4, 0x0904, 1, 0),
+ MX6DL_PAD_EIM_D28__I2C1_SDA = IOMUX_PAD(0x0544, 0x0174, 1 | IOMUX_CONFIG_SION, 0x086C, 1, 0),
+ MX6DL_PAD_EIM_D28__GPIO_3_28 = IOMUX_PAD(0x0544, 0x0174, 5, 0x0000, 0, 0),
+ MX6DL_PAD_ENET_MDC__ENET_MDC = IOMUX_PAD(0x05B8, 0x01E8, 1, 0x0000, 0, 0),
+ MX6DL_PAD_ENET_MDIO__ENET_MDIO = IOMUX_PAD(0x05BC, 0x01EC, 1, 0x0810, 0, 0),
+ MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK = IOMUX_PAD(0x05C0, 0x01F0, 1, 0x0000, 0, 0),
+ MX6DL_PAD_ENET_RXD0__GPIO_1_27 = IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0),
+ MX6DL_PAD_GPIO_16__GPIO_7_11 = IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0),
+ MX6DL_PAD_GPIO_16__I2C3_SDA = IOMUX_PAD(0x05E4, 0x0214, 6 | IOMUX_CONFIG_SION, 0x087C, 1, 0),
+ MX6DL_PAD_GPIO_17__GPIO_7_12 = IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0),
+ MX6DL_PAD_GPIO_18__GPIO_7_13 = IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0),
+ MX6DL_PAD_GPIO_19__GPIO_4_5 = IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0),
+ MX6DL_PAD_GPIO_5__GPIO_1_5 = IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0),
+ MX6DL_PAD_GPIO_5__I2C3_SCL = IOMUX_PAD(0x0600, 0x0230, 6 | IOMUX_CONFIG_SION, 0x0878, 2, 0),
+ MX6DL_PAD_KEY_COL3__I2C2_SCL = IOMUX_PAD(0x0638, 0x0250, 4 | IOMUX_CONFIG_SION, 0x0870, 1, 0),
+ MX6DL_PAD_KEY_COL3__GPIO_4_12 = IOMUX_PAD(0x0638, 0x0250, 5, 0x0000, 0, 0),
+ MX6DL_PAD_KEY_ROW3__I2C2_SDA = IOMUX_PAD(0x064C, 0x0264, 4 | IOMUX_CONFIG_SION, 0x0874, 1, 0),
+ MX6DL_PAD_KEY_ROW3__GPIO_4_13 = IOMUX_PAD(0x064C, 0x0264, 5, 0x0000, 0, 0),
+ MX6DL_PAD_NANDF_D1__GPIO_2_1 = IOMUX_PAD(0x0670, 0x0288, 5, 0x0000, 0, 0),
+ MX6DL_PAD_NANDF_D2__GPIO_2_2 = IOMUX_PAD(0x0674, 0x028C, 5, 0x0000, 0, 0),
+ MX6DL_PAD_NANDF_D3__GPIO_2_3 = IOMUX_PAD(0x0678, 0x0290, 5, 0x0000, 0, 0),
+ MX6DL_PAD_NANDF_D4__GPIO_2_4 = IOMUX_PAD(0x067C, 0x0294, 5, 0x0000, 0, 0),
+ MX6DL_PAD_NANDF_D6__GPIO_2_6 = IOMUX_PAD(0x0684, 0x029C, 5, 0x0000, 0, 0),
+ MX6DL_PAD_RGMII_RD0__ENET_RGMII_RD0 = IOMUX_PAD(0x0694, 0x02AC, 1, 0x0818, 1, 0),
+ MX6DL_PAD_RGMII_RD0__GPIO_6_25 = IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0),
+ MX6DL_PAD_RGMII_RD1__ENET_RGMII_RD1 = IOMUX_PAD(0x0698, 0x02B0, 1, 0x081C, 1, 0),
+ MX6DL_PAD_RGMII_RD1__GPIO_6_27 = IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0),
+ MX6DL_PAD_RGMII_RD2__ENET_RGMII_RD2 = IOMUX_PAD(0x069C, 0x02B4, 1, 0x0820, 1, 0),
+ MX6DL_PAD_RGMII_RD2__GPIO_6_28 = IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0),
+ MX6DL_PAD_RGMII_RD3__ENET_RGMII_RD3 = IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0824, 1, 0),
+ MX6DL_PAD_RGMII_RD3__GPIO_6_29 = IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0),
+ MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL = IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0828, 1, 0),
+ MX6DL_PAD_RGMII_RX_CTL__GPIO_6_24 = IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0),
+ MX6DL_PAD_RGMII_RXC__ENET_RGMII_RXC = IOMUX_PAD(0x06A8, 0x02C0, 1, 0x0814, 1, 0),
+ MX6DL_PAD_RGMII_RXC__GPIO_6_30 = IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0),
+ MX6DL_PAD_RGMII_TD0__ENET_RGMII_TD0 = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0),
+ MX6DL_PAD_RGMII_TD1__ENET_RGMII_TD1 = IOMUX_PAD(0x06B0, 0x02C8, 1, 0x0000, 0, 0),
+ MX6DL_PAD_RGMII_TD2__ENET_RGMII_TD2 = IOMUX_PAD(0x06B4, 0x02CC, 1, 0x0000, 0, 0),
+ MX6DL_PAD_RGMII_TD3__ENET_RGMII_TD3 = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0),
+ MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL = IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0),
+ MX6DL_PAD_RGMII_TXC__ENET_RGMII_TXC = IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0),
+ MX6DL_PAD_SD1_CMD__GPIO_1_18 = IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0),
+ MX6DL_PAD_SD1_DAT3__GPIO_1_21 = IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0),
+ MX6DL_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x06F4, 0x030C, 0, 0x0934, 1, 0),
+ MX6DL_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x06F8, 0x0310, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+ MX6DL_PAD_SD3_DAT0__USDHC3_DAT0 = IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0),
+ MX6DL_PAD_SD3_DAT1__USDHC3_DAT1 = IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0),
+ MX6DL_PAD_SD3_DAT2__USDHC3_DAT2 = IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, 0),
+ MX6DL_PAD_SD3_DAT3__USDHC3_DAT3 = IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, 0),
+ MX6DL_PAD_SD3_DAT5__GPIO_7_0 = IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0),
+ MX6DL_PAD_SD3_DAT6__UART1_RXD = IOMUX_PAD(0x0714, 0x032C, 1, 0x08FC, 2, 0),
+ MX6DL_PAD_SD3_DAT7__UART1_TXD = IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, 0),
+ MX6DL_PAD_SD4_CLK__USDHC4_CLK = IOMUX_PAD(0x0720, 0x0338, 0, 0x0938, 1, 0),
+ MX6DL_PAD_SD4_CMD__USDHC4_CMD = IOMUX_PAD(0x0724, 0x033C, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+ MX6DL_PAD_SD4_DAT0__USDHC4_DAT0 = IOMUX_PAD(0x0728, 0x0340, 1, 0x0000, 0, 0),
+ MX6DL_PAD_SD4_DAT1__USDHC4_DAT1 = IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, 0),
+ MX6DL_PAD_SD4_DAT2__USDHC4_DAT2 = IOMUX_PAD(0x0730, 0x0348, 1, 0x0000, 0, 0),
+ MX6DL_PAD_SD4_DAT3__USDHC4_DAT3 = IOMUX_PAD(0x0734, 0x034C, 1, 0x0000, 0, 0),
+};
+#endif /* __ASM_ARCH_MX6_MX6DL_PINS_H__ */
#ifndef _SYS_PROTO_H_
#define _SYS_PROTO_H_
-#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev)
+#define MXC_CPU_MX51 0x51
+#define MXC_CPU_MX53 0x53
+#define MXC_CPU_MX6SL 0x60
+#define MXC_CPU_MX6DL 0x61
+#define MXC_CPU_MX6SOLO 0x62
+#define MXC_CPU_MX6Q 0x63
+#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev)
u32 get_cpu_rev(void);
+const char *get_imx_type(u32 imxtype);
+unsigned imx_ddr_size(void);
void set_vddsoc(u32 mv);
#include <asm/arch/regs-apbh.h>
#include <asm/arch/regs-base.h>
#include <asm/arch/regs-bch.h>
-#include <asm/arch/regs-clkctrl-mx28.h>
#include <asm/arch/regs-digctl.h>
#include <asm/arch/regs-gpmi.h>
#include <asm/arch/regs-i2c.h>
#include <asm/arch/regs-lradc.h>
#include <asm/arch/regs-ocotp.h>
#include <asm/arch/regs-pinctrl.h>
-#include <asm/arch/regs-power.h>
#include <asm/arch/regs-rtc.h>
#include <asm/arch/regs-ssp.h>
#include <asm/arch/regs-timrot.h>
+#ifdef CONFIG_MX28
+#include <asm/arch/regs-clkctrl-mx28.h>
+#include <asm/arch/regs-power-mx28.h>
+#endif
+
#endif /* __IMX_REGS_H__ */
#ifndef __ASSEMBLY__
struct mxs_clkctrl_regs {
mxs_reg_32(hw_clkctrl_pll0ctrl0) /* 0x00 */
- mxs_reg_32(hw_clkctrl_pll0ctrl1) /* 0x10 */
+ uint32_t hw_clkctrl_pll0ctrl1; /* 0x10 */
+ uint32_t reserved_pll0ctrl1[3]; /* 0x14-0x1c */
mxs_reg_32(hw_clkctrl_pll1ctrl0) /* 0x20 */
- mxs_reg_32(hw_clkctrl_pll1ctrl1) /* 0x30 */
+ uint32_t hw_clkctrl_pll1ctrl1; /* 0x30 */
+ uint32_t reserved_pll1ctrl1[3]; /* 0x34-0x3c */
mxs_reg_32(hw_clkctrl_pll2ctrl0) /* 0x40 */
mxs_reg_32(hw_clkctrl_cpu) /* 0x50 */
mxs_reg_32(hw_clkctrl_hbus) /* 0x60 */
--- /dev/null
+/*
+ * Freescale i.MX28 Power Controller Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __MX28_REGS_POWER_H__
+#define __MX28_REGS_POWER_H__
+
+#include <asm/arch/regs-common.h>
+
+#ifndef __ASSEMBLY__
+struct mxs_power_regs {
+ mxs_reg_32(hw_power_ctrl)
+ mxs_reg_32(hw_power_5vctrl)
+ mxs_reg_32(hw_power_minpwr)
+ mxs_reg_32(hw_power_charge)
+ uint32_t hw_power_vdddctrl;
+ uint32_t reserved_vddd[3];
+ uint32_t hw_power_vddactrl;
+ uint32_t reserved_vdda[3];
+ uint32_t hw_power_vddioctrl;
+ uint32_t reserved_vddio[3];
+ uint32_t hw_power_vddmemctrl;
+ uint32_t reserved_vddmem[3];
+ uint32_t hw_power_dcdc4p2;
+ uint32_t reserved_dcdc4p2[3];
+ uint32_t hw_power_misc;
+ uint32_t reserved_misc[3];
+ uint32_t hw_power_dclimits;
+ uint32_t reserved_dclimits[3];
+ mxs_reg_32(hw_power_loopctrl)
+ uint32_t hw_power_sts;
+ uint32_t reserved_sts[3];
+ mxs_reg_32(hw_power_speed)
+ uint32_t hw_power_battmonitor;
+ uint32_t reserved_battmonitor[3];
+
+ uint32_t reserved[4];
+
+ mxs_reg_32(hw_power_reset)
+ mxs_reg_32(hw_power_debug)
+ mxs_reg_32(hw_power_thermal)
+ mxs_reg_32(hw_power_usb1ctrl)
+ mxs_reg_32(hw_power_special)
+ mxs_reg_32(hw_power_version)
+ mxs_reg_32(hw_power_anaclkctrl)
+ mxs_reg_32(hw_power_refctrl)
+};
+#endif
+
+#define POWER_CTRL_PSWITCH_MID_TRAN (1 << 27)
+#define POWER_CTRL_DCDC4P2_BO_IRQ (1 << 24)
+#define POWER_CTRL_ENIRQ_DCDC4P2_BO (1 << 23)
+#define POWER_CTRL_VDD5V_DROOP_IRQ (1 << 22)
+#define POWER_CTRL_ENIRQ_VDD5V_DROOP (1 << 21)
+#define POWER_CTRL_PSWITCH_IRQ (1 << 20)
+#define POWER_CTRL_PSWITCH_IRQ_SRC (1 << 19)
+#define POWER_CTRL_POLARITY_PSWITCH (1 << 18)
+#define POWER_CTRL_ENIRQ_PSWITCH (1 << 17)
+#define POWER_CTRL_POLARITY_DC_OK (1 << 16)
+#define POWER_CTRL_DC_OK_IRQ (1 << 15)
+#define POWER_CTRL_ENIRQ_DC_OK (1 << 14)
+#define POWER_CTRL_BATT_BO_IRQ (1 << 13)
+#define POWER_CTRL_ENIRQ_BATT_BO (1 << 12)
+#define POWER_CTRL_VDDIO_BO_IRQ (1 << 11)
+#define POWER_CTRL_ENIRQ_VDDIO_BO (1 << 10)
+#define POWER_CTRL_VDDA_BO_IRQ (1 << 9)
+#define POWER_CTRL_ENIRQ_VDDA_BO (1 << 8)
+#define POWER_CTRL_VDDD_BO_IRQ (1 << 7)
+#define POWER_CTRL_ENIRQ_VDDD_BO (1 << 6)
+#define POWER_CTRL_POLARITY_VBUSVALID (1 << 5)
+#define POWER_CTRL_VBUS_VALID_IRQ (1 << 4)
+#define POWER_CTRL_ENIRQ_VBUS_VALID (1 << 3)
+#define POWER_CTRL_POLARITY_VDD5V_GT_VDDIO (1 << 2)
+#define POWER_CTRL_VDD5V_GT_VDDIO_IRQ (1 << 1)
+#define POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO (1 << 0)
+
+#define POWER_5VCTRL_VBUSDROOP_TRSH_MASK (0x3 << 30)
+#define POWER_5VCTRL_VBUSDROOP_TRSH_OFFSET 30
+#define POWER_5VCTRL_VBUSDROOP_TRSH_4V3 (0x0 << 30)
+#define POWER_5VCTRL_VBUSDROOP_TRSH_4V4 (0x1 << 30)
+#define POWER_5VCTRL_VBUSDROOP_TRSH_4V5 (0x2 << 30)
+#define POWER_5VCTRL_VBUSDROOP_TRSH_4V7 (0x3 << 30)
+#define POWER_5VCTRL_HEADROOM_ADJ_MASK (0x7 << 24)
+#define POWER_5VCTRL_HEADROOM_ADJ_OFFSET 24
+#define POWER_5VCTRL_PWD_CHARGE_4P2_MASK (0x3 << 20)
+#define POWER_5VCTRL_PWD_CHARGE_4P2_OFFSET 20
+#define POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK (0x3f << 12)
+#define POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET 12
+#define POWER_5VCTRL_VBUSVALID_TRSH_MASK (0x7 << 8)
+#define POWER_5VCTRL_VBUSVALID_TRSH_OFFSET 8
+#define POWER_5VCTRL_VBUSVALID_TRSH_2V9 (0x0 << 8)
+#define POWER_5VCTRL_VBUSVALID_TRSH_4V0 (0x1 << 8)
+#define POWER_5VCTRL_VBUSVALID_TRSH_4V1 (0x2 << 8)
+#define POWER_5VCTRL_VBUSVALID_TRSH_4V2 (0x3 << 8)
+#define POWER_5VCTRL_VBUSVALID_TRSH_4V3 (0x4 << 8)
+#define POWER_5VCTRL_VBUSVALID_TRSH_4V4 (0x5 << 8)
+#define POWER_5VCTRL_VBUSVALID_TRSH_4V5 (0x6 << 8)
+#define POWER_5VCTRL_VBUSVALID_TRSH_4V6 (0x7 << 8)
+#define POWER_5VCTRL_PWDN_5VBRNOUT (1 << 7)
+#define POWER_5VCTRL_ENABLE_LINREG_ILIMIT (1 << 6)
+#define POWER_5VCTRL_DCDC_XFER (1 << 5)
+#define POWER_5VCTRL_VBUSVALID_5VDETECT (1 << 4)
+#define POWER_5VCTRL_VBUSVALID_TO_B (1 << 3)
+#define POWER_5VCTRL_ILIMIT_EQ_ZERO (1 << 2)
+#define POWER_5VCTRL_PWRUP_VBUS_CMPS (1 << 1)
+#define POWER_5VCTRL_ENABLE_DCDC (1 << 0)
+
+#define POWER_MINPWR_LOWPWR_4P2 (1 << 14)
+#define POWER_MINPWR_PWD_BO (1 << 12)
+#define POWER_MINPWR_USE_VDDXTAL_VBG (1 << 11)
+#define POWER_MINPWR_PWD_ANA_CMPS (1 << 10)
+#define POWER_MINPWR_ENABLE_OSC (1 << 9)
+#define POWER_MINPWR_SELECT_OSC (1 << 8)
+#define POWER_MINPWR_VBG_OFF (1 << 7)
+#define POWER_MINPWR_DOUBLE_FETS (1 << 6)
+#define POWER_MINPWR_HALFFETS (1 << 5)
+#define POWER_MINPWR_LESSANA_I (1 << 4)
+#define POWER_MINPWR_PWD_XTAL24 (1 << 3)
+#define POWER_MINPWR_DC_STOPCLK (1 << 2)
+#define POWER_MINPWR_EN_DC_PFM (1 << 1)
+#define POWER_MINPWR_DC_HALFCLK (1 << 0)
+
+#define POWER_CHARGE_ADJ_VOLT_MASK (0x7 << 24)
+#define POWER_CHARGE_ADJ_VOLT_OFFSET 24
+#define POWER_CHARGE_ADJ_VOLT_M025P (0x1 << 24)
+#define POWER_CHARGE_ADJ_VOLT_P050P (0x2 << 24)
+#define POWER_CHARGE_ADJ_VOLT_M075P (0x3 << 24)
+#define POWER_CHARGE_ADJ_VOLT_P025P (0x4 << 24)
+#define POWER_CHARGE_ADJ_VOLT_M050P (0x5 << 24)
+#define POWER_CHARGE_ADJ_VOLT_P075P (0x6 << 24)
+#define POWER_CHARGE_ADJ_VOLT_M100P (0x7 << 24)
+#define POWER_CHARGE_ENABLE_LOAD (1 << 22)
+#define POWER_CHARGE_ENABLE_FAULT_DETECT (1 << 20)
+#define POWER_CHARGE_CHRG_STS_OFF (1 << 19)
+#define POWER_CHARGE_LIION_4P1 (1 << 18)
+#define POWER_CHARGE_PWD_BATTCHRG (1 << 16)
+#define POWER_CHARGE_ENABLE_CHARGER_USB1 (1 << 13)
+#define POWER_CHARGE_ENABLE_CHARGER_USB0 (1 << 12)
+#define POWER_CHARGE_STOP_ILIMIT_MASK (0xf << 8)
+#define POWER_CHARGE_STOP_ILIMIT_OFFSET 8
+#define POWER_CHARGE_STOP_ILIMIT_10MA (0x1 << 8)
+#define POWER_CHARGE_STOP_ILIMIT_20MA (0x2 << 8)
+#define POWER_CHARGE_STOP_ILIMIT_50MA (0x4 << 8)
+#define POWER_CHARGE_STOP_ILIMIT_100MA (0x8 << 8)
+#define POWER_CHARGE_BATTCHRG_I_MASK 0x3f
+#define POWER_CHARGE_BATTCHRG_I_OFFSET 0
+#define POWER_CHARGE_BATTCHRG_I_10MA 0x01
+#define POWER_CHARGE_BATTCHRG_I_20MA 0x02
+#define POWER_CHARGE_BATTCHRG_I_50MA 0x04
+#define POWER_CHARGE_BATTCHRG_I_100MA 0x08
+#define POWER_CHARGE_BATTCHRG_I_200MA 0x10
+#define POWER_CHARGE_BATTCHRG_I_400MA 0x20
+
+#define POWER_VDDDCTRL_ADJTN_MASK (0xf << 28)
+#define POWER_VDDDCTRL_ADJTN_OFFSET 28
+#define POWER_VDDDCTRL_PWDN_BRNOUT (1 << 23)
+#define POWER_VDDDCTRL_DISABLE_STEPPING (1 << 22)
+#define POWER_VDDDCTRL_ENABLE_LINREG (1 << 21)
+#define POWER_VDDDCTRL_DISABLE_FET (1 << 20)
+#define POWER_VDDDCTRL_LINREG_OFFSET_MASK (0x3 << 16)
+#define POWER_VDDDCTRL_LINREG_OFFSET_OFFSET 16
+#define POWER_VDDDCTRL_LINREG_OFFSET_0STEPS (0x0 << 16)
+#define POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 16)
+#define POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 16)
+#define POWER_VDDDCTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 16)
+#define POWER_VDDDCTRL_BO_OFFSET_MASK (0x7 << 8)
+#define POWER_VDDDCTRL_BO_OFFSET_OFFSET 8
+#define POWER_VDDDCTRL_TRG_MASK 0x1f
+#define POWER_VDDDCTRL_TRG_OFFSET 0
+
+#define POWER_VDDACTRL_PWDN_BRNOUT (1 << 19)
+#define POWER_VDDACTRL_DISABLE_STEPPING (1 << 18)
+#define POWER_VDDACTRL_ENABLE_LINREG (1 << 17)
+#define POWER_VDDACTRL_DISABLE_FET (1 << 16)
+#define POWER_VDDACTRL_LINREG_OFFSET_MASK (0x3 << 12)
+#define POWER_VDDACTRL_LINREG_OFFSET_OFFSET 12
+#define POWER_VDDACTRL_LINREG_OFFSET_0STEPS (0x0 << 12)
+#define POWER_VDDACTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 12)
+#define POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 12)
+#define POWER_VDDACTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 12)
+#define POWER_VDDACTRL_BO_OFFSET_MASK (0x7 << 8)
+#define POWER_VDDACTRL_BO_OFFSET_OFFSET 8
+#define POWER_VDDACTRL_TRG_MASK 0x1f
+#define POWER_VDDACTRL_TRG_OFFSET 0
+
+#define POWER_VDDIOCTRL_ADJTN_MASK (0xf << 20)
+#define POWER_VDDIOCTRL_ADJTN_OFFSET 20
+#define POWER_VDDIOCTRL_PWDN_BRNOUT (1 << 18)
+#define POWER_VDDIOCTRL_DISABLE_STEPPING (1 << 17)
+#define POWER_VDDIOCTRL_DISABLE_FET (1 << 16)
+#define POWER_VDDIOCTRL_LINREG_OFFSET_MASK (0x3 << 12)
+#define POWER_VDDIOCTRL_LINREG_OFFSET_OFFSET 12
+#define POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS (0x0 << 12)
+#define POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 12)
+#define POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 12)
+#define POWER_VDDIOCTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 12)
+#define POWER_VDDIOCTRL_BO_OFFSET_MASK (0x7 << 8)
+#define POWER_VDDIOCTRL_BO_OFFSET_OFFSET 8
+#define POWER_VDDIOCTRL_TRG_MASK 0x1f
+#define POWER_VDDIOCTRL_TRG_OFFSET 0
+
+#define POWER_VDDMEMCTRL_PULLDOWN_ACTIVE (1 << 10)
+#define POWER_VDDMEMCTRL_ENABLE_ILIMIT (1 << 9)
+#define POWER_VDDMEMCTRL_ENABLE_LINREG (1 << 8)
+#define POWER_VDDMEMCTRL_BO_OFFSET_MASK (0x7 << 5)
+#define POWER_VDDMEMCTRL_BO_OFFSET_OFFSET 5
+#define POWER_VDDMEMCTRL_TRG_MASK 0x1f
+#define POWER_VDDMEMCTRL_TRG_OFFSET 0
+
+#define POWER_DCDC4P2_DROPOUT_CTRL_MASK (0xf << 28)
+#define POWER_DCDC4P2_DROPOUT_CTRL_OFFSET 28
+#define POWER_DCDC4P2_DROPOUT_CTRL_200MV (0x3 << 30)
+#define POWER_DCDC4P2_DROPOUT_CTRL_100MV (0x2 << 30)
+#define POWER_DCDC4P2_DROPOUT_CTRL_50MV (0x1 << 30)
+#define POWER_DCDC4P2_DROPOUT_CTRL_25MV (0x0 << 30)
+#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2 (0x0 << 28)
+#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2_LT_BATT (0x1 << 28)
+#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL (0x2 << 28)
+#define POWER_DCDC4P2_ISTEAL_THRESH_MASK (0x3 << 24)
+#define POWER_DCDC4P2_ISTEAL_THRESH_OFFSET 24
+#define POWER_DCDC4P2_ENABLE_4P2 (1 << 23)
+#define POWER_DCDC4P2_ENABLE_DCDC (1 << 22)
+#define POWER_DCDC4P2_HYST_DIR (1 << 21)
+#define POWER_DCDC4P2_HYST_THRESH (1 << 20)
+#define POWER_DCDC4P2_TRG_MASK (0x7 << 16)
+#define POWER_DCDC4P2_TRG_OFFSET 16
+#define POWER_DCDC4P2_TRG_4V2 (0x0 << 16)
+#define POWER_DCDC4P2_TRG_4V1 (0x1 << 16)
+#define POWER_DCDC4P2_TRG_4V0 (0x2 << 16)
+#define POWER_DCDC4P2_TRG_3V9 (0x3 << 16)
+#define POWER_DCDC4P2_TRG_BATT (0x4 << 16)
+#define POWER_DCDC4P2_BO_MASK (0x1f << 8)
+#define POWER_DCDC4P2_BO_OFFSET 8
+#define POWER_DCDC4P2_CMPTRIP_MASK 0x1f
+#define POWER_DCDC4P2_CMPTRIP_OFFSET 0
+
+#define POWER_MISC_FREQSEL_MASK (0x7 << 4)
+#define POWER_MISC_FREQSEL_OFFSET 4
+#define POWER_MISC_FREQSEL_20MHZ (0x1 << 4)
+#define POWER_MISC_FREQSEL_24MHZ (0x2 << 4)
+#define POWER_MISC_FREQSEL_19MHZ (0x3 << 4)
+#define POWER_MISC_FREQSEL_14MHZ (0x4 << 4)
+#define POWER_MISC_FREQSEL_18MHZ (0x5 << 4)
+#define POWER_MISC_FREQSEL_21MHZ (0x6 << 4)
+#define POWER_MISC_FREQSEL_17MHZ (0x7 << 4)
+#define POWER_MISC_DISABLE_FET_BO_LOGIC (1 << 3)
+#define POWER_MISC_DELAY_TIMING (1 << 2)
+#define POWER_MISC_TEST (1 << 1)
+#define POWER_MISC_SEL_PLLCLK (1 << 0)
+
+#define POWER_DCLIMITS_POSLIMIT_BUCK_MASK (0x7f << 8)
+#define POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET 8
+#define POWER_DCLIMITS_NEGLIMIT_MASK 0x7f
+#define POWER_DCLIMITS_NEGLIMIT_OFFSET 0
+
+#define POWER_LOOPCTRL_TOGGLE_DIF (1 << 20)
+#define POWER_LOOPCTRL_HYST_SIGN (1 << 19)
+#define POWER_LOOPCTRL_EN_CM_HYST (1 << 18)
+#define POWER_LOOPCTRL_EN_DF_HYST (1 << 17)
+#define POWER_LOOPCTRL_CM_HYST_THRESH (1 << 16)
+#define POWER_LOOPCTRL_DF_HYST_THRESH (1 << 15)
+#define POWER_LOOPCTRL_RCSCALE_THRESH (1 << 14)
+#define POWER_LOOPCTRL_EN_RCSCALE_MASK (0x3 << 12)
+#define POWER_LOOPCTRL_EN_RCSCALE_OFFSET 12
+#define POWER_LOOPCTRL_EN_RCSCALE_DIS (0x0 << 12)
+#define POWER_LOOPCTRL_EN_RCSCALE_2X (0x1 << 12)
+#define POWER_LOOPCTRL_EN_RCSCALE_4X (0x2 << 12)
+#define POWER_LOOPCTRL_EN_RCSCALE_8X (0x3 << 12)
+#define POWER_LOOPCTRL_DC_FF_MASK (0x7 << 8)
+#define POWER_LOOPCTRL_DC_FF_OFFSET 8
+#define POWER_LOOPCTRL_DC_R_MASK (0xf << 4)
+#define POWER_LOOPCTRL_DC_R_OFFSET 4
+#define POWER_LOOPCTRL_DC_C_MASK 0x3
+#define POWER_LOOPCTRL_DC_C_OFFSET 0
+#define POWER_LOOPCTRL_DC_C_MAX 0x0
+#define POWER_LOOPCTRL_DC_C_2X 0x1
+#define POWER_LOOPCTRL_DC_C_4X 0x2
+#define POWER_LOOPCTRL_DC_C_MIN 0x3
+
+#define POWER_STS_PWRUP_SOURCE_MASK (0x3f << 24)
+#define POWER_STS_PWRUP_SOURCE_OFFSET 24
+#define POWER_STS_PWRUP_SOURCE_5V (0x20 << 24)
+#define POWER_STS_PWRUP_SOURCE_RTC (0x10 << 24)
+#define POWER_STS_PWRUP_SOURCE_PSWITCH_HIGH (0x02 << 24)
+#define POWER_STS_PWRUP_SOURCE_PSWITCH_MID (0x01 << 24)
+#define POWER_STS_PSWITCH_MASK (0x3 << 20)
+#define POWER_STS_PSWITCH_OFFSET 20
+#define POWER_STS_THERMAL_WARNING (1 << 19)
+#define POWER_STS_VDDMEM_BO (1 << 18)
+#define POWER_STS_AVALID0_STATUS (1 << 17)
+#define POWER_STS_BVALID0_STATUS (1 << 16)
+#define POWER_STS_VBUSVALID0_STATUS (1 << 15)
+#define POWER_STS_SESSEND0_STATUS (1 << 14)
+#define POWER_STS_BATT_BO (1 << 13)
+#define POWER_STS_VDD5V_FAULT (1 << 12)
+#define POWER_STS_CHRGSTS (1 << 11)
+#define POWER_STS_DCDC_4P2_BO (1 << 10)
+#define POWER_STS_DC_OK (1 << 9)
+#define POWER_STS_VDDIO_BO (1 << 8)
+#define POWER_STS_VDDA_BO (1 << 7)
+#define POWER_STS_VDDD_BO (1 << 6)
+#define POWER_STS_VDD5V_GT_VDDIO (1 << 5)
+#define POWER_STS_VDD5V_DROOP (1 << 4)
+#define POWER_STS_AVALID0 (1 << 3)
+#define POWER_STS_BVALID0 (1 << 2)
+#define POWER_STS_VBUSVALID0 (1 << 1)
+#define POWER_STS_SESSEND0 (1 << 0)
+
+#define POWER_SPEED_STATUS_MASK (0xffff << 8)
+#define POWER_SPEED_STATUS_OFFSET 8
+#define POWER_SPEED_STATUS_SEL_MASK (0x3 << 6)
+#define POWER_SPEED_STATUS_SEL_OFFSET 6
+#define POWER_SPEED_STATUS_SEL_DCDC_STAT (0x0 << 6)
+#define POWER_SPEED_STATUS_SEL_CORE_STAT (0x1 << 6)
+#define POWER_SPEED_STATUS_SEL_ARM_STAT (0x2 << 6)
+#define POWER_SPEED_CTRL_MASK 0x3
+#define POWER_SPEED_CTRL_OFFSET 0
+#define POWER_SPEED_CTRL_SS_OFF 0x0
+#define POWER_SPEED_CTRL_SS_ON 0x1
+#define POWER_SPEED_CTRL_SS_ENABLE 0x3
+
+#define POWER_BATTMONITOR_BATT_VAL_MASK (0x3ff << 16)
+#define POWER_BATTMONITOR_BATT_VAL_OFFSET 16
+#define POWER_BATTMONITOR_PWDN_BATTBRNOUT_5VDETECT_EN (1 << 11)
+#define POWER_BATTMONITOR_EN_BATADJ (1 << 10)
+#define POWER_BATTMONITOR_PWDN_BATTBRNOUT (1 << 9)
+#define POWER_BATTMONITOR_BRWNOUT_PWD (1 << 8)
+#define POWER_BATTMONITOR_BRWNOUT_LVL_MASK 0x1f
+#define POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET 0
+
+#define POWER_RESET_UNLOCK_MASK (0xffff << 16)
+#define POWER_RESET_UNLOCK_OFFSET 16
+#define POWER_RESET_UNLOCK_KEY (0x3e77 << 16)
+#define POWER_RESET_FASTFALL_PSWITCH_OFF (1 << 2)
+#define POWER_RESET_PWD_OFF (1 << 1)
+#define POWER_RESET_PWD (1 << 0)
+
+#define POWER_DEBUG_VBUSVALIDPIOLOCK (1 << 3)
+#define POWER_DEBUG_AVALIDPIOLOCK (1 << 2)
+#define POWER_DEBUG_BVALIDPIOLOCK (1 << 1)
+#define POWER_DEBUG_SESSENDPIOLOCK (1 << 0)
+
+#define POWER_THERMAL_TEST (1 << 8)
+#define POWER_THERMAL_PWD (1 << 7)
+#define POWER_THERMAL_LOW_POWER (1 << 6)
+#define POWER_THERMAL_OFFSET_ADJ_MASK (0x3 << 4)
+#define POWER_THERMAL_OFFSET_ADJ_OFFSET 4
+#define POWER_THERMAL_OFFSET_ADJ_ENABLE (1 << 3)
+#define POWER_THERMAL_TEMP_THRESHOLD_MASK 0x7
+#define POWER_THERMAL_TEMP_THRESHOLD_OFFSET 0
+
+#define POWER_USB1CTRL_AVALID1 (1 << 3)
+#define POWER_USB1CTRL_BVALID1 (1 << 2)
+#define POWER_USB1CTRL_VBUSVALID1 (1 << 1)
+#define POWER_USB1CTRL_SESSEND1 (1 << 0)
+
+#define POWER_SPECIAL_TEST_MASK 0xffffffff
+#define POWER_SPECIAL_TEST_OFFSET 0
+
+#define POWER_VERSION_MAJOR_MASK (0xff << 24)
+#define POWER_VERSION_MAJOR_OFFSET 24
+#define POWER_VERSION_MINOR_MASK (0xff << 16)
+#define POWER_VERSION_MINOR_OFFSET 16
+#define POWER_VERSION_STEP_MASK 0xffff
+#define POWER_VERSION_STEP_OFFSET 0
+
+#define POWER_ANACLKCTRL_CLKGATE_0 (1 << 31)
+#define POWER_ANACLKCTRL_OUTDIV_MASK (0x7 << 28)
+#define POWER_ANACLKCTRL_OUTDIV_OFFSET 28
+#define POWER_ANACLKCTRL_INVERT_OUTCLK (1 << 27)
+#define POWER_ANACLKCTRL_CLKGATE_I (1 << 26)
+#define POWER_ANACLKCTRL_DITHER_OFF (1 << 10)
+#define POWER_ANACLKCTRL_SLOW_DITHER (1 << 9)
+#define POWER_ANACLKCTRL_INVERT_INCLK (1 << 8)
+#define POWER_ANACLKCTRL_INCLK_SHIFT_MASK (0x3 << 4)
+#define POWER_ANACLKCTRL_INCLK_SHIFT_OFFSET 4
+#define POWER_ANACLKCTRL_INDIV_MASK 0x7
+#define POWER_ANACLKCTRL_INDIV_OFFSET 0
+
+#define POWER_REFCTRL_FASTSETTLING (1 << 26)
+#define POWER_REFCTRL_RAISE_REF (1 << 25)
+#define POWER_REFCTRL_XTAL_BGR_BIAS (1 << 24)
+#define POWER_REFCTRL_VBG_ADJ_MASK (0x7 << 20)
+#define POWER_REFCTRL_VBG_ADJ_OFFSET 20
+#define POWER_REFCTRL_LOW_PWR (1 << 19)
+#define POWER_REFCTRL_BIAS_CTRL_MASK (0x3 << 16)
+#define POWER_REFCTRL_BIAS_CTRL_OFFSET 16
+#define POWER_REFCTRL_VDDXTAL_TO_VDDD (1 << 14)
+#define POWER_REFCTRL_ADJ_ANA (1 << 13)
+#define POWER_REFCTRL_ADJ_VAG (1 << 12)
+#define POWER_REFCTRL_ANA_REFVAL_MASK (0xf << 8)
+#define POWER_REFCTRL_ANA_REFVAL_OFFSET 8
+#define POWER_REFCTRL_VAG_VAL_MASK (0xf << 4)
+#define POWER_REFCTRL_VAG_VAL_OFFSET 4
+
+#endif /* __MX28_REGS_POWER_H__ */
+++ /dev/null
-/*
- * Freescale i.MX28 Power Controller Register Definitions
- *
- * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- */
-
-#ifndef __MX28_REGS_POWER_H__
-#define __MX28_REGS_POWER_H__
-
-#include <asm/arch/regs-common.h>
-
-#ifndef __ASSEMBLY__
-struct mxs_power_regs {
- mxs_reg_32(hw_power_ctrl)
- mxs_reg_32(hw_power_5vctrl)
- mxs_reg_32(hw_power_minpwr)
- mxs_reg_32(hw_power_charge)
- uint32_t hw_power_vdddctrl;
- uint32_t reserved_vddd[3];
- uint32_t hw_power_vddactrl;
- uint32_t reserved_vdda[3];
- uint32_t hw_power_vddioctrl;
- uint32_t reserved_vddio[3];
- uint32_t hw_power_vddmemctrl;
- uint32_t reserved_vddmem[3];
- uint32_t hw_power_dcdc4p2;
- uint32_t reserved_dcdc4p2[3];
- uint32_t hw_power_misc;
- uint32_t reserved_misc[3];
- uint32_t hw_power_dclimits;
- uint32_t reserved_dclimits[3];
- mxs_reg_32(hw_power_loopctrl)
- uint32_t hw_power_sts;
- uint32_t reserved_sts[3];
- mxs_reg_32(hw_power_speed)
- uint32_t hw_power_battmonitor;
- uint32_t reserved_battmonitor[3];
-
- uint32_t reserved[4];
-
- mxs_reg_32(hw_power_reset)
- mxs_reg_32(hw_power_debug)
- mxs_reg_32(hw_power_thermal)
- mxs_reg_32(hw_power_usb1ctrl)
- mxs_reg_32(hw_power_special)
- mxs_reg_32(hw_power_version)
- mxs_reg_32(hw_power_anaclkctrl)
- mxs_reg_32(hw_power_refctrl)
-};
-#endif
-
-#define POWER_CTRL_PSWITCH_MID_TRAN (1 << 27)
-#define POWER_CTRL_DCDC4P2_BO_IRQ (1 << 24)
-#define POWER_CTRL_ENIRQ_DCDC4P2_BO (1 << 23)
-#define POWER_CTRL_VDD5V_DROOP_IRQ (1 << 22)
-#define POWER_CTRL_ENIRQ_VDD5V_DROOP (1 << 21)
-#define POWER_CTRL_PSWITCH_IRQ (1 << 20)
-#define POWER_CTRL_PSWITCH_IRQ_SRC (1 << 19)
-#define POWER_CTRL_POLARITY_PSWITCH (1 << 18)
-#define POWER_CTRL_ENIRQ_PSWITCH (1 << 17)
-#define POWER_CTRL_POLARITY_DC_OK (1 << 16)
-#define POWER_CTRL_DC_OK_IRQ (1 << 15)
-#define POWER_CTRL_ENIRQ_DC_OK (1 << 14)
-#define POWER_CTRL_BATT_BO_IRQ (1 << 13)
-#define POWER_CTRL_ENIRQ_BATT_BO (1 << 12)
-#define POWER_CTRL_VDDIO_BO_IRQ (1 << 11)
-#define POWER_CTRL_ENIRQ_VDDIO_BO (1 << 10)
-#define POWER_CTRL_VDDA_BO_IRQ (1 << 9)
-#define POWER_CTRL_ENIRQ_VDDA_BO (1 << 8)
-#define POWER_CTRL_VDDD_BO_IRQ (1 << 7)
-#define POWER_CTRL_ENIRQ_VDDD_BO (1 << 6)
-#define POWER_CTRL_POLARITY_VBUSVALID (1 << 5)
-#define POWER_CTRL_VBUS_VALID_IRQ (1 << 4)
-#define POWER_CTRL_ENIRQ_VBUS_VALID (1 << 3)
-#define POWER_CTRL_POLARITY_VDD5V_GT_VDDIO (1 << 2)
-#define POWER_CTRL_VDD5V_GT_VDDIO_IRQ (1 << 1)
-#define POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO (1 << 0)
-
-#define POWER_5VCTRL_VBUSDROOP_TRSH_MASK (0x3 << 30)
-#define POWER_5VCTRL_VBUSDROOP_TRSH_OFFSET 30
-#define POWER_5VCTRL_VBUSDROOP_TRSH_4V3 (0x0 << 30)
-#define POWER_5VCTRL_VBUSDROOP_TRSH_4V4 (0x1 << 30)
-#define POWER_5VCTRL_VBUSDROOP_TRSH_4V5 (0x2 << 30)
-#define POWER_5VCTRL_VBUSDROOP_TRSH_4V7 (0x3 << 30)
-#define POWER_5VCTRL_HEADROOM_ADJ_MASK (0x7 << 24)
-#define POWER_5VCTRL_HEADROOM_ADJ_OFFSET 24
-#define POWER_5VCTRL_PWD_CHARGE_4P2_MASK (0x3 << 20)
-#define POWER_5VCTRL_PWD_CHARGE_4P2_OFFSET 20
-#define POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK (0x3f << 12)
-#define POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET 12
-#define POWER_5VCTRL_VBUSVALID_TRSH_MASK (0x7 << 8)
-#define POWER_5VCTRL_VBUSVALID_TRSH_OFFSET 8
-#define POWER_5VCTRL_VBUSVALID_TRSH_2V9 (0x0 << 8)
-#define POWER_5VCTRL_VBUSVALID_TRSH_4V0 (0x1 << 8)
-#define POWER_5VCTRL_VBUSVALID_TRSH_4V1 (0x2 << 8)
-#define POWER_5VCTRL_VBUSVALID_TRSH_4V2 (0x3 << 8)
-#define POWER_5VCTRL_VBUSVALID_TRSH_4V3 (0x4 << 8)
-#define POWER_5VCTRL_VBUSVALID_TRSH_4V4 (0x5 << 8)
-#define POWER_5VCTRL_VBUSVALID_TRSH_4V5 (0x6 << 8)
-#define POWER_5VCTRL_VBUSVALID_TRSH_4V6 (0x7 << 8)
-#define POWER_5VCTRL_PWDN_5VBRNOUT (1 << 7)
-#define POWER_5VCTRL_ENABLE_LINREG_ILIMIT (1 << 6)
-#define POWER_5VCTRL_DCDC_XFER (1 << 5)
-#define POWER_5VCTRL_VBUSVALID_5VDETECT (1 << 4)
-#define POWER_5VCTRL_VBUSVALID_TO_B (1 << 3)
-#define POWER_5VCTRL_ILIMIT_EQ_ZERO (1 << 2)
-#define POWER_5VCTRL_PWRUP_VBUS_CMPS (1 << 1)
-#define POWER_5VCTRL_ENABLE_DCDC (1 << 0)
-
-#define POWER_MINPWR_LOWPWR_4P2 (1 << 14)
-#define POWER_MINPWR_PWD_BO (1 << 12)
-#define POWER_MINPWR_USE_VDDXTAL_VBG (1 << 11)
-#define POWER_MINPWR_PWD_ANA_CMPS (1 << 10)
-#define POWER_MINPWR_ENABLE_OSC (1 << 9)
-#define POWER_MINPWR_SELECT_OSC (1 << 8)
-#define POWER_MINPWR_FBG_OFF (1 << 7)
-#define POWER_MINPWR_DOUBLE_FETS (1 << 6)
-#define POWER_MINPWR_HALFFETS (1 << 5)
-#define POWER_MINPWR_LESSANA_I (1 << 4)
-#define POWER_MINPWR_PWD_XTAL24 (1 << 3)
-#define POWER_MINPWR_DC_STOPCLK (1 << 2)
-#define POWER_MINPWR_EN_DC_PFM (1 << 1)
-#define POWER_MINPWR_DC_HALFCLK (1 << 0)
-
-#define POWER_CHARGE_ADJ_VOLT_MASK (0x7 << 24)
-#define POWER_CHARGE_ADJ_VOLT_OFFSET 24
-#define POWER_CHARGE_ADJ_VOLT_M025P (0x1 << 24)
-#define POWER_CHARGE_ADJ_VOLT_P050P (0x2 << 24)
-#define POWER_CHARGE_ADJ_VOLT_M075P (0x3 << 24)
-#define POWER_CHARGE_ADJ_VOLT_P025P (0x4 << 24)
-#define POWER_CHARGE_ADJ_VOLT_M050P (0x5 << 24)
-#define POWER_CHARGE_ADJ_VOLT_P075P (0x6 << 24)
-#define POWER_CHARGE_ADJ_VOLT_M100P (0x7 << 24)
-#define POWER_CHARGE_ENABLE_LOAD (1 << 22)
-#define POWER_CHARGE_ENABLE_FAULT_DETECT (1 << 20)
-#define POWER_CHARGE_CHRG_STS_OFF (1 << 19)
-#define POWER_CHARGE_LIION_4P1 (1 << 18)
-#define POWER_CHARGE_PWD_BATTCHRG (1 << 16)
-#define POWER_CHARGE_ENABLE_CHARGER_USB1 (1 << 13)
-#define POWER_CHARGE_ENABLE_CHARGER_USB0 (1 << 12)
-#define POWER_CHARGE_STOP_ILIMIT_MASK (0xf << 8)
-#define POWER_CHARGE_STOP_ILIMIT_OFFSET 8
-#define POWER_CHARGE_STOP_ILIMIT_10MA (0x1 << 8)
-#define POWER_CHARGE_STOP_ILIMIT_20MA (0x2 << 8)
-#define POWER_CHARGE_STOP_ILIMIT_50MA (0x4 << 8)
-#define POWER_CHARGE_STOP_ILIMIT_100MA (0x8 << 8)
-#define POWER_CHARGE_BATTCHRG_I_MASK 0x3f
-#define POWER_CHARGE_BATTCHRG_I_OFFSET 0
-#define POWER_CHARGE_BATTCHRG_I_10MA 0x01
-#define POWER_CHARGE_BATTCHRG_I_20MA 0x02
-#define POWER_CHARGE_BATTCHRG_I_50MA 0x04
-#define POWER_CHARGE_BATTCHRG_I_100MA 0x08
-#define POWER_CHARGE_BATTCHRG_I_200MA 0x10
-#define POWER_CHARGE_BATTCHRG_I_400MA 0x20
-
-#define POWER_VDDDCTRL_ADJTN_MASK (0xf << 28)
-#define POWER_VDDDCTRL_ADJTN_OFFSET 28
-#define POWER_VDDDCTRL_PWDN_BRNOUT (1 << 23)
-#define POWER_VDDDCTRL_DISABLE_STEPPING (1 << 22)
-#define POWER_VDDDCTRL_ENABLE_LINREG (1 << 21)
-#define POWER_VDDDCTRL_DISABLE_FET (1 << 20)
-#define POWER_VDDDCTRL_LINREG_OFFSET_MASK (0x3 << 16)
-#define POWER_VDDDCTRL_LINREG_OFFSET_OFFSET 16
-#define POWER_VDDDCTRL_LINREG_OFFSET_0STEPS (0x0 << 16)
-#define POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 16)
-#define POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 16)
-#define POWER_VDDDCTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 16)
-#define POWER_VDDDCTRL_BO_OFFSET_MASK (0x7 << 8)
-#define POWER_VDDDCTRL_BO_OFFSET_OFFSET 8
-#define POWER_VDDDCTRL_TRG_MASK 0x1f
-#define POWER_VDDDCTRL_TRG_OFFSET 0
-
-#define POWER_VDDACTRL_PWDN_BRNOUT (1 << 19)
-#define POWER_VDDACTRL_DISABLE_STEPPING (1 << 18)
-#define POWER_VDDACTRL_ENABLE_LINREG (1 << 17)
-#define POWER_VDDACTRL_DISABLE_FET (1 << 16)
-#define POWER_VDDACTRL_LINREG_OFFSET_MASK (0x3 << 12)
-#define POWER_VDDACTRL_LINREG_OFFSET_OFFSET 12
-#define POWER_VDDACTRL_LINREG_OFFSET_0STEPS (0x0 << 12)
-#define POWER_VDDACTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 12)
-#define POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 12)
-#define POWER_VDDACTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 12)
-#define POWER_VDDACTRL_BO_OFFSET_MASK (0x7 << 8)
-#define POWER_VDDACTRL_BO_OFFSET_OFFSET 8
-#define POWER_VDDACTRL_TRG_MASK 0x1f
-#define POWER_VDDACTRL_TRG_OFFSET 0
-
-#define POWER_VDDIOCTRL_ADJTN_MASK (0xf << 20)
-#define POWER_VDDIOCTRL_ADJTN_OFFSET 20
-#define POWER_VDDIOCTRL_PWDN_BRNOUT (1 << 18)
-#define POWER_VDDIOCTRL_DISABLE_STEPPING (1 << 17)
-#define POWER_VDDIOCTRL_DISABLE_FET (1 << 16)
-#define POWER_VDDIOCTRL_LINREG_OFFSET_MASK (0x3 << 12)
-#define POWER_VDDIOCTRL_LINREG_OFFSET_OFFSET 12
-#define POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS (0x0 << 12)
-#define POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 12)
-#define POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 12)
-#define POWER_VDDIOCTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 12)
-#define POWER_VDDIOCTRL_BO_OFFSET_MASK (0x7 << 8)
-#define POWER_VDDIOCTRL_BO_OFFSET_OFFSET 8
-#define POWER_VDDIOCTRL_TRG_MASK 0x1f
-#define POWER_VDDIOCTRL_TRG_OFFSET 0
-
-#define POWER_VDDMEMCTRL_PULLDOWN_ACTIVE (1 << 10)
-#define POWER_VDDMEMCTRL_ENABLE_ILIMIT (1 << 9)
-#define POWER_VDDMEMCTRL_ENABLE_LINREG (1 << 8)
-#define POWER_VDDMEMCTRL_BO_OFFSET_MASK (0x7 << 5)
-#define POWER_VDDMEMCTRL_BO_OFFSET_OFFSET 5
-#define POWER_VDDMEMCTRL_TRG_MASK 0x1f
-#define POWER_VDDMEMCTRL_TRG_OFFSET 0
-
-#define POWER_DCDC4P2_DROPOUT_CTRL_MASK (0xf << 28)
-#define POWER_DCDC4P2_DROPOUT_CTRL_OFFSET 28
-#define POWER_DCDC4P2_DROPOUT_CTRL_200MV (0x3 << 30)
-#define POWER_DCDC4P2_DROPOUT_CTRL_100MV (0x2 << 30)
-#define POWER_DCDC4P2_DROPOUT_CTRL_50MV (0x1 << 30)
-#define POWER_DCDC4P2_DROPOUT_CTRL_25MV (0x0 << 30)
-#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2 (0x0 << 28)
-#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2_LT_BATT (0x1 << 28)
-#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL (0x2 << 28)
-#define POWER_DCDC4P2_ISTEAL_THRESH_MASK (0x3 << 24)
-#define POWER_DCDC4P2_ISTEAL_THRESH_OFFSET 24
-#define POWER_DCDC4P2_ENABLE_4P2 (1 << 23)
-#define POWER_DCDC4P2_ENABLE_DCDC (1 << 22)
-#define POWER_DCDC4P2_HYST_DIR (1 << 21)
-#define POWER_DCDC4P2_HYST_THRESH (1 << 20)
-#define POWER_DCDC4P2_TRG_MASK (0x7 << 16)
-#define POWER_DCDC4P2_TRG_OFFSET 16
-#define POWER_DCDC4P2_TRG_4V2 (0x0 << 16)
-#define POWER_DCDC4P2_TRG_4V1 (0x1 << 16)
-#define POWER_DCDC4P2_TRG_4V0 (0x2 << 16)
-#define POWER_DCDC4P2_TRG_3V9 (0x3 << 16)
-#define POWER_DCDC4P2_TRG_BATT (0x4 << 16)
-#define POWER_DCDC4P2_BO_MASK (0x1f << 8)
-#define POWER_DCDC4P2_BO_OFFSET 8
-#define POWER_DCDC4P2_CMPTRIP_MASK 0x1f
-#define POWER_DCDC4P2_CMPTRIP_OFFSET 0
-
-#define POWER_MISC_FREQSEL_MASK (0x7 << 4)
-#define POWER_MISC_FREQSEL_OFFSET 4
-#define POWER_MISC_FREQSEL_20MHZ (0x1 << 4)
-#define POWER_MISC_FREQSEL_24MHZ (0x2 << 4)
-#define POWER_MISC_FREQSEL_19MHZ (0x3 << 4)
-#define POWER_MISC_FREQSEL_14MHZ (0x4 << 4)
-#define POWER_MISC_FREQSEL_18MHZ (0x5 << 4)
-#define POWER_MISC_FREQSEL_21MHZ (0x6 << 4)
-#define POWER_MISC_FREQSEL_17MHZ (0x7 << 4)
-#define POWER_MISC_DISABLE_FET_BO_LOGIC (1 << 3)
-#define POWER_MISC_DELAY_TIMING (1 << 2)
-#define POWER_MISC_TEST (1 << 1)
-#define POWER_MISC_SEL_PLLCLK (1 << 0)
-
-#define POWER_DCLIMITS_POSLIMIT_BUCK_MASK (0x7f << 8)
-#define POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET 8
-#define POWER_DCLIMITS_NEGLIMIT_MASK 0x7f
-#define POWER_DCLIMITS_NETLIMIT_OFFSET 0
-
-#define POWER_LOOPCTRL_TOGGLE_DIF (1 << 20)
-#define POWER_LOOPCTRL_HYST_SIGN (1 << 19)
-#define POWER_LOOPCTRL_EN_CM_HYST (1 << 18)
-#define POWER_LOOPCTRL_EN_DF_HYST (1 << 17)
-#define POWER_LOOPCTRL_CM_HYST_THRESH (1 << 16)
-#define POWER_LOOPCTRL_DF_HYST_THRESH (1 << 15)
-#define POWER_LOOPCTRL_RCSCALE_THRESH (1 << 14)
-#define POWER_LOOPCTRL_EN_RCSCALE_MASK (0x3 << 12)
-#define POWER_LOOPCTRL_EN_RCSCALE_OFFSET 12
-#define POWER_LOOPCTRL_EN_RCSCALE_DIS (0x0 << 12)
-#define POWER_LOOPCTRL_EN_RCSCALE_2X (0x1 << 12)
-#define POWER_LOOPCTRL_EN_RCSCALE_4X (0x2 << 12)
-#define POWER_LOOPCTRL_EN_RCSCALE_8X (0x3 << 12)
-#define POWER_LOOPCTRL_DC_FF_MASK (0x7 << 8)
-#define POWER_LOOPCTRL_DC_FF_OFFSET 8
-#define POWER_LOOPCTRL_DC_R_MASK (0xf << 4)
-#define POWER_LOOPCTRL_DC_R_OFFSET 4
-#define POWER_LOOPCTRL_DC_C_MASK 0x3
-#define POWER_LOOPCTRL_DC_C_OFFSET 0
-#define POWER_LOOPCTRL_DC_C_MAX 0x0
-#define POWER_LOOPCTRL_DC_C_2X 0x1
-#define POWER_LOOPCTRL_DC_C_4X 0x2
-#define POWER_LOOPCTRL_DC_C_MIN 0x3
-
-#define POWER_STS_PWRUP_SOURCE_MASK (0x3f << 24)
-#define POWER_STS_PWRUP_SOURCE_OFFSET 24
-#define POWER_STS_PWRUP_SOURCE_5V (0x20 << 24)
-#define POWER_STS_PWRUP_SOURCE_RTC (0x10 << 24)
-#define POWER_STS_PWRUP_SOURCE_PSWITCH_HIGH (0x02 << 24)
-#define POWER_STS_PWRUP_SOURCE_PSWITCH_MID (0x01 << 24)
-#define POWER_STS_PSWITCH_MASK (0x3 << 20)
-#define POWER_STS_PSWITCH_OFFSET 20
-#define POWER_STS_THERMAL_WARNING (1 << 19)
-#define POWER_STS_VDDMEM_BO (1 << 18)
-#define POWER_STS_AVALID0_STATUS (1 << 17)
-#define POWER_STS_BVALID0_STATUS (1 << 16)
-#define POWER_STS_VBUSVALID0_STATUS (1 << 15)
-#define POWER_STS_SESSEND0_STATUS (1 << 14)
-#define POWER_STS_BATT_BO (1 << 13)
-#define POWER_STS_VDD5V_FAULT (1 << 12)
-#define POWER_STS_CHRGSTS (1 << 11)
-#define POWER_STS_DCDC_4P2_BO (1 << 10)
-#define POWER_STS_DC_OK (1 << 9)
-#define POWER_STS_VDDIO_BO (1 << 8)
-#define POWER_STS_VDDA_BO (1 << 7)
-#define POWER_STS_VDDD_BO (1 << 6)
-#define POWER_STS_VDD5V_GT_VDDIO (1 << 5)
-#define POWER_STS_VDD5V_DROOP (1 << 4)
-#define POWER_STS_AVALID0 (1 << 3)
-#define POWER_STS_BVALID0 (1 << 2)
-#define POWER_STS_VBUSVALID0 (1 << 1)
-#define POWER_STS_SESSEND0 (1 << 0)
-
-#define POWER_SPEED_STATUS_MASK (0xffff << 8)
-#define POWER_SPEED_STATUS_OFFSET 8
-#define POWER_SPEED_STATUS_SEL_MASK (0x3 << 6)
-#define POWER_SPEED_STATUS_SEL_OFFSET 6
-#define POWER_SPEED_STATUS_SEL_DCDC_STAT (0x0 << 6)
-#define POWER_SPEED_STATUS_SEL_CORE_STAT (0x1 << 6)
-#define POWER_SPEED_STATUS_SEL_ARM_STAT (0x2 << 6)
-#define POWER_SPEED_CTRL_MASK 0x3
-#define POWER_SPEED_CTRL_OFFSET 0
-#define POWER_SPEED_CTRL_SS_OFF 0x0
-#define POWER_SPEED_CTRL_SS_ON 0x1
-#define POWER_SPEED_CTRL_SS_ENABLE 0x3
-
-#define POWER_BATTMONITOR_BATT_VAL_MASK (0x3ff << 16)
-#define POWER_BATTMONITOR_BATT_VAL_OFFSET 16
-#define POWER_BATTMONITOR_PWDN_BATTBRNOUT_5VDETECT_EN (1 << 11)
-#define POWER_BATTMONITOR_EN_BATADJ (1 << 10)
-#define POWER_BATTMONITOR_PWDN_BATTBRNOUT (1 << 9)
-#define POWER_BATTMONITOR_BRWNOUT_PWD (1 << 8)
-#define POWER_BATTMONITOR_BRWNOUT_LVL_MASK 0x1f
-#define POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET 0
-
-#define POWER_RESET_UNLOCK_MASK (0xffff << 16)
-#define POWER_RESET_UNLOCK_OFFSET 16
-#define POWER_RESET_UNLOCK_KEY (0x3e77 << 16)
-#define POWER_RESET_FASTFALL_PSWITCH_OFF (1 << 2)
-#define POWER_RESET_PWD_OFF (1 << 1)
-#define POWER_RESET_PWD (1 << 0)
-
-#define POWER_DEBUG_VBUSVALIDPIOLOCK (1 << 3)
-#define POWER_DEBUG_AVALIDPIOLOCK (1 << 2)
-#define POWER_DEBUG_BVALIDPIOLOCK (1 << 1)
-#define POWER_DEBUG_SESSENDPIOLOCK (1 << 0)
-
-#define POWER_THERMAL_TEST (1 << 8)
-#define POWER_THERMAL_PWD (1 << 7)
-#define POWER_THERMAL_LOW_POWER (1 << 6)
-#define POWER_THERMAL_OFFSET_ADJ_MASK (0x3 << 4)
-#define POWER_THERMAL_OFFSET_ADJ_OFFSET 4
-#define POWER_THERMAL_OFFSET_ADJ_ENABLE (1 << 3)
-#define POWER_THERMAL_TEMP_THRESHOLD_MASK 0x7
-#define POWER_THERMAL_TEMP_THRESHOLD_OFFSET 0
-
-#define POWER_USB1CTRL_AVALID1 (1 << 3)
-#define POWER_USB1CTRL_BVALID1 (1 << 2)
-#define POWER_USB1CTRL_VBUSVALID1 (1 << 1)
-#define POWER_USB1CTRL_SESSEND1 (1 << 0)
-
-#define POWER_SPECIAL_TEST_MASK 0xffffffff
-#define POWER_SPECIAL_TEST_OFFSET 0
-
-#define POWER_VERSION_MAJOR_MASK (0xff << 24)
-#define POWER_VERSION_MAJOR_OFFSET 24
-#define POWER_VERSION_MINOR_MASK (0xff << 16)
-#define POWER_VERSION_MINOR_OFFSET 16
-#define POWER_VERSION_STEP_MASK 0xffff
-#define POWER_VERSION_STEP_OFFSET 0
-
-#define POWER_ANACLKCTRL_CLKGATE_0 (1 << 31)
-#define POWER_ANACLKCTRL_OUTDIV_MASK (0x7 << 28)
-#define POWER_ANACLKCTRL_OUTDIV_OFFSET 28
-#define POWER_ANACLKCTRL_INVERT_OUTCLK (1 << 27)
-#define POWER_ANACLKCTRL_CLKGATE_I (1 << 26)
-#define POWER_ANACLKCTRL_DITHER_OFF (1 << 10)
-#define POWER_ANACLKCTRL_SLOW_DITHER (1 << 9)
-#define POWER_ANACLKCTRL_INVERT_INCLK (1 << 8)
-#define POWER_ANACLKCTRL_INCLK_SHIFT_MASK (0x3 << 4)
-#define POWER_ANACLKCTRL_INCLK_SHIFT_OFFSET 4
-#define POWER_ANACLKCTRL_INDIV_MASK 0x7
-#define POWER_ANACLKCTRL_INDIV_OFFSET 0
-
-#define POWER_REFCTRL_FASTSETTLING (1 << 26)
-#define POWER_REFCTRL_RAISE_REF (1 << 25)
-#define POWER_REFCTRL_XTAL_BGR_BIAS (1 << 24)
-#define POWER_REFCTRL_VBG_ADJ_MASK (0x7 << 20)
-#define POWER_REFCTRL_VBG_ADJ_OFFSET 20
-#define POWER_REFCTRL_LOW_PWR (1 << 19)
-#define POWER_REFCTRL_BIAS_CTRL_MASK (0x3 << 16)
-#define POWER_REFCTRL_BIAS_CTRL_OFFSET 16
-#define POWER_REFCTRL_VDDXTAL_TO_VDDD (1 << 14)
-#define POWER_REFCTRL_ADJ_ANA (1 << 13)
-#define POWER_REFCTRL_ADJ_VAG (1 << 12)
-#define POWER_REFCTRL_ANA_REFVAL_MASK (0xf << 8)
-#define POWER_REFCTRL_ANA_REFVAL_OFFSET 8
-#define POWER_REFCTRL_VAG_VAL_MASK (0xf << 4)
-#define POWER_REFCTRL_VAG_VAL_OFFSET 4
-
-#endif /* __MX28_REGS_POWER_H__ */
u32 param1;
};
+/* Board SDRC timing values */
+struct board_sdrc_timings {
+ u32 mcfg;
+ u32 ctrla;
+ u32 ctrlb;
+ u32 rfr_ctrl;
+ u32 mr;
+};
+
void prcm_init(void);
void per_clocks_enable(void);
void ehci_clocks_enable(void);
void memif_init(void);
void sdrc_init(void);
void do_sdrc_init(u32, u32);
-void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
- u32 *mr);
+
+void get_board_mem_timings(struct board_sdrc_timings *timings);
void identify_nand_chip(int *mfr, int *id);
void emif4_init(void);
void gpmc_init(void);
return S5PC110_GPIO_BASE;
}
-#define s5pc110_gpio_get_nr(bank, pin) \
+static inline unsigned int s5p_gpio_part_max(int nr)
+{
+ return 0;
+}
+
+#define s5pc110_gpio_get_nr(bank, pin) \
((((((unsigned int)&(((struct s5pc110_gpio *)S5PC110_GPIO_BASE)->bank))\
- S5PC110_GPIO_BASE) / sizeof(struct s5p_gpio_bank)) \
* GPIO_PER_BANK) + pin)
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_TEGRA_DC_H
+#define __ASM_ARCH_TEGRA_DC_H
+
+/* Register definitions for the Tegra display controller */
+
+/* CMD register 0x000 ~ 0x43 */
+struct dc_cmd_reg {
+ /* Address 0x000 ~ 0x002 */
+ uint gen_incr_syncpt; /* _CMD_GENERAL_INCR_SYNCPT_0 */
+ uint gen_incr_syncpt_ctrl; /* _CMD_GENERAL_INCR_SYNCPT_CNTRL_0 */
+ uint gen_incr_syncpt_err; /* _CMD_GENERAL_INCR_SYNCPT_ERROR_0 */
+
+ uint reserved0[5]; /* reserved_0[5] */
+
+ /* Address 0x008 ~ 0x00a */
+ uint win_a_incr_syncpt; /* _CMD_WIN_A_INCR_SYNCPT_0 */
+ uint win_a_incr_syncpt_ctrl; /* _CMD_WIN_A_INCR_SYNCPT_CNTRL_0 */
+ uint win_a_incr_syncpt_err; /* _CMD_WIN_A_INCR_SYNCPT_ERROR_0 */
+
+ uint reserved1[5]; /* reserved_1[5] */
+
+ /* Address 0x010 ~ 0x012 */
+ uint win_b_incr_syncpt; /* _CMD_WIN_B_INCR_SYNCPT_0 */
+ uint win_b_incr_syncpt_ctrl; /* _CMD_WIN_B_INCR_SYNCPT_CNTRL_0 */
+ uint win_b_incr_syncpt_err; /* _CMD_WIN_B_INCR_SYNCPT_ERROR_0 */
+
+ uint reserved2[5]; /* reserved_2[5] */
+
+ /* Address 0x018 ~ 0x01a */
+ uint win_c_incr_syncpt; /* _CMD_WIN_C_INCR_SYNCPT_0 */
+ uint win_c_incr_syncpt_ctrl; /* _CMD_WIN_C_INCR_SYNCPT_CNTRL_0 */
+ uint win_c_incr_syncpt_err; /* _CMD_WIN_C_INCR_SYNCPT_ERROR_0 */
+
+ uint reserved3[13]; /* reserved_3[13] */
+
+ /* Address 0x028 */
+ uint cont_syncpt_vsync; /* _CMD_CONT_SYNCPT_VSYNC_0 */
+
+ uint reserved4[7]; /* reserved_4[7] */
+
+ /* Address 0x030 ~ 0x033 */
+ uint ctxsw; /* _CMD_CTXSW_0 */
+ uint disp_cmd_opt0; /* _CMD_DISPLAY_COMMAND_OPTION0_0 */
+ uint disp_cmd; /* _CMD_DISPLAY_COMMAND_0 */
+ uint sig_raise; /* _CMD_SIGNAL_RAISE_0 */
+
+ uint reserved5[2]; /* reserved_0[2] */
+
+ /* Address 0x036 ~ 0x03e */
+ uint disp_pow_ctrl; /* _CMD_DISPLAY_POWER_CONTROL_0 */
+ uint int_stat; /* _CMD_INT_STATUS_0 */
+ uint int_mask; /* _CMD_INT_MASK_0 */
+ uint int_enb; /* _CMD_INT_ENABLE_0 */
+ uint int_type; /* _CMD_INT_TYPE_0 */
+ uint int_polarity; /* _CMD_INT_POLARITY_0 */
+ uint sig_raise1; /* _CMD_SIGNAL_RAISE1_0 */
+ uint sig_raise2; /* _CMD_SIGNAL_RAISE2_0 */
+ uint sig_raise3; /* _CMD_SIGNAL_RAISE3_0 */
+
+ uint reserved6; /* reserved_6 */
+
+ /* Address 0x040 ~ 0x043 */
+ uint state_access; /* _CMD_STATE_ACCESS_0 */
+ uint state_ctrl; /* _CMD_STATE_CONTROL_0 */
+ uint disp_win_header; /* _CMD_DISPLAY_WINDOW_HEADER_0 */
+ uint reg_act_ctrl; /* _CMD_REG_ACT_CONTROL_0 */
+};
+
+enum {
+ PIN_REG_COUNT = 4,
+ PIN_OUTPUT_SEL_COUNT = 7,
+};
+
+/* COM register 0x300 ~ 0x329 */
+struct dc_com_reg {
+ /* Address 0x300 ~ 0x301 */
+ uint crc_ctrl; /* _COM_CRC_CONTROL_0 */
+ uint crc_checksum; /* _COM_CRC_CHECKSUM_0 */
+
+ /* _COM_PIN_OUTPUT_ENABLE0/1/2/3_0: Address 0x302 ~ 0x305 */
+ uint pin_output_enb[PIN_REG_COUNT];
+
+ /* _COM_PIN_OUTPUT_POLARITY0/1/2/3_0: Address 0x306 ~ 0x309 */
+ uint pin_output_polarity[PIN_REG_COUNT];
+
+ /* _COM_PIN_OUTPUT_DATA0/1/2/3_0: Address 0x30a ~ 0x30d */
+ uint pin_output_data[PIN_REG_COUNT];
+
+ /* _COM_PIN_INPUT_ENABLE0_0: Address 0x30e ~ 0x311 */
+ uint pin_input_enb[PIN_REG_COUNT];
+
+ /* Address 0x312 ~ 0x313 */
+ uint pin_input_data0; /* _COM_PIN_INPUT_DATA0_0 */
+ uint pin_input_data1; /* _COM_PIN_INPUT_DATA1_0 */
+
+ /* _COM_PIN_OUTPUT_SELECT0/1/2/3/4/5/6_0: Address 0x314 ~ 0x31a */
+ uint pin_output_sel[PIN_OUTPUT_SEL_COUNT];
+
+ /* Address 0x31b ~ 0x329 */
+ uint pin_misc_ctrl; /* _COM_PIN_MISC_CONTROL_0 */
+ uint pm0_ctrl; /* _COM_PM0_CONTROL_0 */
+ uint pm0_duty_cycle; /* _COM_PM0_DUTY_CYCLE_0 */
+ uint pm1_ctrl; /* _COM_PM1_CONTROL_0 */
+ uint pm1_duty_cycle; /* _COM_PM1_DUTY_CYCLE_0 */
+ uint spi_ctrl; /* _COM_SPI_CONTROL_0 */
+ uint spi_start_byte; /* _COM_SPI_START_BYTE_0 */
+ uint hspi_wr_data_ab; /* _COM_HSPI_WRITE_DATA_AB_0 */
+ uint hspi_wr_data_cd; /* _COM_HSPI_WRITE_DATA_CD */
+ uint hspi_cs_dc; /* _COM_HSPI_CS_DC_0 */
+ uint scratch_reg_a; /* _COM_SCRATCH_REGISTER_A_0 */
+ uint scratch_reg_b; /* _COM_SCRATCH_REGISTER_B_0 */
+ uint gpio_ctrl; /* _COM_GPIO_CTRL_0 */
+ uint gpio_debounce_cnt; /* _COM_GPIO_DEBOUNCE_COUNTER_0 */
+ uint crc_checksum_latched; /* _COM_CRC_CHECKSUM_LATCHED_0 */
+};
+
+enum dc_disp_h_pulse_pos {
+ H_PULSE0_POSITION_A,
+ H_PULSE0_POSITION_B,
+ H_PULSE0_POSITION_C,
+ H_PULSE0_POSITION_D,
+ H_PULSE0_POSITION_COUNT,
+};
+
+struct _disp_h_pulse {
+ /* _DISP_H_PULSE0/1/2_CONTROL_0 */
+ uint h_pulse_ctrl;
+ /* _DISP_H_PULSE0/1/2_POSITION_A/B/C/D_0 */
+ uint h_pulse_pos[H_PULSE0_POSITION_COUNT];
+};
+
+enum dc_disp_v_pulse_pos {
+ V_PULSE0_POSITION_A,
+ V_PULSE0_POSITION_B,
+ V_PULSE0_POSITION_C,
+ V_PULSE0_POSITION_COUNT,
+};
+
+struct _disp_v_pulse0 {
+ /* _DISP_H_PULSE0/1_CONTROL_0 */
+ uint v_pulse_ctrl;
+ /* _DISP_H_PULSE0/1_POSITION_A/B/C_0 */
+ uint v_pulse_pos[V_PULSE0_POSITION_COUNT];
+};
+
+struct _disp_v_pulse2 {
+ /* _DISP_H_PULSE2/3_CONTROL_0 */
+ uint v_pulse_ctrl;
+ /* _DISP_H_PULSE2/3_POSITION_A_0 */
+ uint v_pulse_pos_a;
+};
+
+enum dc_disp_h_pulse_reg {
+ H_PULSE0,
+ H_PULSE1,
+ H_PULSE2,
+ H_PULSE_COUNT,
+};
+
+enum dc_disp_pp_select {
+ PP_SELECT_A,
+ PP_SELECT_B,
+ PP_SELECT_C,
+ PP_SELECT_D,
+ PP_SELECT_COUNT,
+};
+
+/* DISP register 0x400 ~ 0x4c1 */
+struct dc_disp_reg {
+ /* Address 0x400 ~ 0x40a */
+ uint disp_signal_opt0; /* _DISP_DISP_SIGNAL_OPTIONS0_0 */
+ uint disp_signal_opt1; /* _DISP_DISP_SIGNAL_OPTIONS1_0 */
+ uint disp_win_opt; /* _DISP_DISP_WIN_OPTIONS_0 */
+ uint mem_high_pri; /* _DISP_MEM_HIGH_PRIORITY_0 */
+ uint mem_high_pri_timer; /* _DISP_MEM_HIGH_PRIORITY_TIMER_0 */
+ uint disp_timing_opt; /* _DISP_DISP_TIMING_OPTIONS_0 */
+ uint ref_to_sync; /* _DISP_REF_TO_SYNC_0 */
+ uint sync_width; /* _DISP_SYNC_WIDTH_0 */
+ uint back_porch; /* _DISP_BACK_PORCH_0 */
+ uint disp_active; /* _DISP_DISP_ACTIVE_0 */
+ uint front_porch; /* _DISP_FRONT_PORCH_0 */
+
+ /* Address 0x40b ~ 0x419: _DISP_H_PULSE0/1/2_ */
+ struct _disp_h_pulse h_pulse[H_PULSE_COUNT];
+
+ /* Address 0x41a ~ 0x421 */
+ struct _disp_v_pulse0 v_pulse0; /* _DISP_V_PULSE0_ */
+ struct _disp_v_pulse0 v_pulse1; /* _DISP_V_PULSE1_ */
+
+ /* Address 0x422 ~ 0x425 */
+ struct _disp_v_pulse2 v_pulse3; /* _DISP_V_PULSE2_ */
+ struct _disp_v_pulse2 v_pulse4; /* _DISP_V_PULSE3_ */
+
+ /* Address 0x426 ~ 0x429 */
+ uint m0_ctrl; /* _DISP_M0_CONTROL_0 */
+ uint m1_ctrl; /* _DISP_M1_CONTROL_0 */
+ uint di_ctrl; /* _DISP_DI_CONTROL_0 */
+ uint pp_ctrl; /* _DISP_PP_CONTROL_0 */
+
+ /* Address 0x42a ~ 0x42d: _DISP_PP_SELECT_A/B/C/D_0 */
+ uint pp_select[PP_SELECT_COUNT];
+
+ /* Address 0x42e ~ 0x435 */
+ uint disp_clk_ctrl; /* _DISP_DISP_CLOCK_CONTROL_0 */
+ uint disp_interface_ctrl; /* _DISP_DISP_INTERFACE_CONTROL_0 */
+ uint disp_color_ctrl; /* _DISP_DISP_COLOR_CONTROL_0 */
+ uint shift_clk_opt; /* _DISP_SHIFT_CLOCK_OPTIONS_0 */
+ uint data_enable_opt; /* _DISP_DATA_ENABLE_OPTIONS_0 */
+ uint serial_interface_opt; /* _DISP_SERIAL_INTERFACE_OPTIONS_0 */
+ uint lcd_spi_opt; /* _DISP_LCD_SPI_OPTIONS_0 */
+ uint border_color; /* _DISP_BORDER_COLOR_0 */
+
+ /* Address 0x436 ~ 0x439 */
+ uint color_key0_lower; /* _DISP_COLOR_KEY0_LOWER_0 */
+ uint color_key0_upper; /* _DISP_COLOR_KEY0_UPPER_0 */
+ uint color_key1_lower; /* _DISP_COLOR_KEY1_LOWER_0 */
+ uint color_key1_upper; /* _DISP_COLOR_KEY1_UPPER_0 */
+
+ uint reserved0[2]; /* reserved_0[2] */
+
+ /* Address 0x43c ~ 0x442 */
+ uint cursor_foreground; /* _DISP_CURSOR_FOREGROUND_0 */
+ uint cursor_background; /* _DISP_CURSOR_BACKGROUND_0 */
+ uint cursor_start_addr; /* _DISP_CURSOR_START_ADDR_0 */
+ uint cursor_start_addr_ns; /* _DISP_CURSOR_START_ADDR_NS_0 */
+ uint cursor_pos; /* _DISP_CURSOR_POSITION_0 */
+ uint cursor_pos_ns; /* _DISP_CURSOR_POSITION_NS_0 */
+ uint seq_ctrl; /* _DISP_INIT_SEQ_CONTROL_0 */
+
+ /* Address 0x442 ~ 0x446 */
+ uint spi_init_seq_data_a; /* _DISP_SPI_INIT_SEQ_DATA_A_0 */
+ uint spi_init_seq_data_b; /* _DISP_SPI_INIT_SEQ_DATA_B_0 */
+ uint spi_init_seq_data_c; /* _DISP_SPI_INIT_SEQ_DATA_C_0 */
+ uint spi_init_seq_data_d; /* _DISP_SPI_INIT_SEQ_DATA_D_0 */
+
+ uint reserved1[0x39]; /* reserved1[0x39], */
+
+ /* Address 0x480 ~ 0x484 */
+ uint dc_mccif_fifoctrl; /* _DISP_DC_MCCIF_FIFOCTRL_0 */
+ uint mccif_disp0a_hyst; /* _DISP_MCCIF_DISPLAY0A_HYST_0 */
+ uint mccif_disp0b_hyst; /* _DISP_MCCIF_DISPLAY0B_HYST_0 */
+ uint mccif_disp0c_hyst; /* _DISP_MCCIF_DISPLAY0C_HYST_0 */
+ uint mccif_disp1b_hyst; /* _DISP_MCCIF_DISPLAY1B_HYST_0 */
+
+ uint reserved2[0x3b]; /* reserved2[0x3b] */
+
+ /* Address 0x4c0 ~ 0x4c1 */
+ uint dac_crt_ctrl; /* _DISP_DAC_CRT_CTRL_0 */
+ uint disp_misc_ctrl; /* _DISP_DISP_MISC_CONTROL_0 */
+};
+
+enum dc_winc_filter_p {
+ WINC_FILTER_COUNT = 0x10,
+};
+
+/* Window A/B/C register 0x500 ~ 0x628 */
+struct dc_winc_reg {
+
+ /* Address 0x500 */
+ uint color_palette; /* _WINC_COLOR_PALETTE_0 */
+
+ uint reserved0[0xff]; /* reserved_0[0xff] */
+
+ /* Address 0x600 */
+ uint palette_color_ext; /* _WINC_PALETTE_COLOR_EXT_0 */
+
+ /* _WINC_H_FILTER_P00~0F_0 */
+ /* Address 0x601 ~ 0x610 */
+ uint h_filter_p[WINC_FILTER_COUNT];
+
+ /* Address 0x611 ~ 0x618 */
+ uint csc_yof; /* _WINC_CSC_YOF_0 */
+ uint csc_kyrgb; /* _WINC_CSC_KYRGB_0 */
+ uint csc_kur; /* _WINC_CSC_KUR_0 */
+ uint csc_kvr; /* _WINC_CSC_KVR_0 */
+ uint csc_kug; /* _WINC_CSC_KUG_0 */
+ uint csc_kvg; /* _WINC_CSC_KVG_0 */
+ uint csc_kub; /* _WINC_CSC_KUB_0 */
+ uint csc_kvb; /* _WINC_CSC_KVB_0 */
+
+ /* Address 0x619 ~ 0x628: _WINC_V_FILTER_P00~0F_0 */
+ uint v_filter_p[WINC_FILTER_COUNT];
+};
+
+/* WIN A/B/C Register 0x700 ~ 0x714*/
+struct dc_win_reg {
+ /* Address 0x700 ~ 0x714 */
+ uint win_opt; /* _WIN_WIN_OPTIONS_0 */
+ uint byte_swap; /* _WIN_BYTE_SWAP_0 */
+ uint buffer_ctrl; /* _WIN_BUFFER_CONTROL_0 */
+ uint color_depth; /* _WIN_COLOR_DEPTH_0 */
+ uint pos; /* _WIN_POSITION_0 */
+ uint size; /* _WIN_SIZE_0 */
+ uint prescaled_size; /* _WIN_PRESCALED_SIZE_0 */
+ uint h_initial_dda; /* _WIN_H_INITIAL_DDA_0 */
+ uint v_initial_dda; /* _WIN_V_INITIAL_DDA_0 */
+ uint dda_increment; /* _WIN_DDA_INCREMENT_0 */
+ uint line_stride; /* _WIN_LINE_STRIDE_0 */
+ uint buf_stride; /* _WIN_BUF_STRIDE_0 */
+ uint uv_buf_stride; /* _WIN_UV_BUF_STRIDE_0 */
+ uint buffer_addr_mode; /* _WIN_BUFFER_ADDR_MODE_0 */
+ uint dv_ctrl; /* _WIN_DV_CONTROL_0 */
+ uint blend_nokey; /* _WIN_BLEND_NOKEY_0 */
+ uint blend_1win; /* _WIN_BLEND_1WIN_0 */
+ uint blend_2win_x; /* _WIN_BLEND_2WIN_X_0 */
+ uint blend_2win_y; /* _WIN_BLEND_2WIN_Y_0 */
+ uint blend_3win_xy; /* _WIN_BLEND_3WIN_XY_0 */
+ uint hp_fetch_ctrl; /* _WIN_HP_FETCH_CONTROL_0 */
+};
+
+/* WINBUF A/B/C Register 0x800 ~ 0x80a */
+struct dc_winbuf_reg {
+ /* Address 0x800 ~ 0x80a */
+ uint start_addr; /* _WINBUF_START_ADDR_0 */
+ uint start_addr_ns; /* _WINBUF_START_ADDR_NS_0 */
+ uint start_addr_u; /* _WINBUF_START_ADDR_U_0 */
+ uint start_addr_u_ns; /* _WINBUF_START_ADDR_U_NS_0 */
+ uint start_addr_v; /* _WINBUF_START_ADDR_V_0 */
+ uint start_addr_v_ns; /* _WINBUF_START_ADDR_V_NS_0 */
+ uint addr_h_offset; /* _WINBUF_ADDR_H_OFFSET_0 */
+ uint addr_h_offset_ns; /* _WINBUF_ADDR_H_OFFSET_NS_0 */
+ uint addr_v_offset; /* _WINBUF_ADDR_V_OFFSET_0 */
+ uint addr_v_offset_ns; /* _WINBUF_ADDR_V_OFFSET_NS_0 */
+ uint uflow_status; /* _WINBUF_UFLOW_STATUS_0 */
+};
+
+/* Display Controller (DC_) regs */
+struct dc_ctlr {
+ struct dc_cmd_reg cmd; /* CMD register 0x000 ~ 0x43 */
+ uint reserved0[0x2bc];
+
+ struct dc_com_reg com; /* COM register 0x300 ~ 0x329 */
+ uint reserved1[0xd6];
+
+ struct dc_disp_reg disp; /* DISP register 0x400 ~ 0x4c1 */
+ uint reserved2[0x3e];
+
+ struct dc_winc_reg winc; /* Window A/B/C 0x500 ~ 0x628 */
+ uint reserved3[0xd7];
+
+ struct dc_win_reg win; /* WIN A/B/C 0x700 ~ 0x714*/
+ uint reserved4[0xeb];
+
+ struct dc_winbuf_reg winbuf; /* WINBUF A/B/C 0x800 ~ 0x80a */
+};
+
+#define BIT(pos) (1U << pos)
+
+/* DC_CMD_DISPLAY_COMMAND 0x032 */
+#define CTRL_MODE_SHIFT 5
+#define CTRL_MODE_MASK (0x3 << CTRL_MODE_SHIFT)
+enum {
+ CTRL_MODE_STOP,
+ CTRL_MODE_C_DISPLAY,
+ CTRL_MODE_NC_DISPLAY,
+};
+
+/* _WIN_COLOR_DEPTH_0 */
+enum win_color_depth_id {
+ COLOR_DEPTH_P1,
+ COLOR_DEPTH_P2,
+ COLOR_DEPTH_P4,
+ COLOR_DEPTH_P8,
+ COLOR_DEPTH_B4G4R4A4,
+ COLOR_DEPTH_B5G5R5A,
+ COLOR_DEPTH_B5G6R5,
+ COLOR_DEPTH_AB5G5R5,
+ COLOR_DEPTH_B8G8R8A8 = 12,
+ COLOR_DEPTH_R8G8B8A8,
+ COLOR_DEPTH_B6x2G6x2R6x2A8,
+ COLOR_DEPTH_R6x2G6x2B6x2A8,
+ COLOR_DEPTH_YCbCr422,
+ COLOR_DEPTH_YUV422,
+ COLOR_DEPTH_YCbCr420P,
+ COLOR_DEPTH_YUV420P,
+ COLOR_DEPTH_YCbCr422P,
+ COLOR_DEPTH_YUV422P,
+ COLOR_DEPTH_YCbCr422R,
+ COLOR_DEPTH_YUV422R,
+ COLOR_DEPTH_YCbCr422RA,
+ COLOR_DEPTH_YUV422RA,
+};
+
+/* DC_CMD_DISPLAY_POWER_CONTROL 0x036 */
+#define PW0_ENABLE BIT(0)
+#define PW1_ENABLE BIT(2)
+#define PW2_ENABLE BIT(4)
+#define PW3_ENABLE BIT(6)
+#define PW4_ENABLE BIT(8)
+#define PM0_ENABLE BIT(16)
+#define PM1_ENABLE BIT(18)
+#define SPI_ENABLE BIT(24)
+#define HSPI_ENABLE BIT(25)
+
+/* DC_CMD_STATE_CONTROL 0x041 */
+#define GENERAL_ACT_REQ BIT(0)
+#define WIN_A_ACT_REQ BIT(1)
+#define WIN_B_ACT_REQ BIT(2)
+#define WIN_C_ACT_REQ BIT(3)
+#define GENERAL_UPDATE BIT(8)
+#define WIN_A_UPDATE BIT(9)
+#define WIN_B_UPDATE BIT(10)
+#define WIN_C_UPDATE BIT(11)
+
+/* DC_CMD_DISPLAY_WINDOW_HEADER 0x042 */
+#define WINDOW_A_SELECT BIT(4)
+#define WINDOW_B_SELECT BIT(5)
+#define WINDOW_C_SELECT BIT(6)
+
+/* DC_DISP_DISP_CLOCK_CONTROL 0x42e */
+#define SHIFT_CLK_DIVIDER_SHIFT 0
+#define SHIFT_CLK_DIVIDER_MASK (0xff << SHIFT_CLK_DIVIDER_SHIFT)
+#define PIXEL_CLK_DIVIDER_SHIFT 8
+#define PIXEL_CLK_DIVIDER_MSK (0xf << PIXEL_CLK_DIVIDER_SHIFT)
+enum {
+ PIXEL_CLK_DIVIDER_PCD1,
+ PIXEL_CLK_DIVIDER_PCD1H,
+ PIXEL_CLK_DIVIDER_PCD2,
+ PIXEL_CLK_DIVIDER_PCD3,
+ PIXEL_CLK_DIVIDER_PCD4,
+ PIXEL_CLK_DIVIDER_PCD6,
+ PIXEL_CLK_DIVIDER_PCD8,
+ PIXEL_CLK_DIVIDER_PCD9,
+ PIXEL_CLK_DIVIDER_PCD12,
+ PIXEL_CLK_DIVIDER_PCD16,
+ PIXEL_CLK_DIVIDER_PCD18,
+ PIXEL_CLK_DIVIDER_PCD24,
+ PIXEL_CLK_DIVIDER_PCD13,
+};
+
+/* DC_DISP_DISP_INTERFACE_CONTROL 0x42f */
+#define DATA_FORMAT_SHIFT 0
+#define DATA_FORMAT_MASK (0xf << DATA_FORMAT_SHIFT)
+enum {
+ DATA_FORMAT_DF1P1C,
+ DATA_FORMAT_DF1P2C24B,
+ DATA_FORMAT_DF1P2C18B,
+ DATA_FORMAT_DF1P2C16B,
+ DATA_FORMAT_DF2S,
+ DATA_FORMAT_DF3S,
+ DATA_FORMAT_DFSPI,
+ DATA_FORMAT_DF1P3C24B,
+ DATA_FORMAT_DF1P3C18B,
+};
+#define DATA_ALIGNMENT_SHIFT 8
+enum {
+ DATA_ALIGNMENT_MSB,
+ DATA_ALIGNMENT_LSB,
+};
+#define DATA_ORDER_SHIFT 9
+enum {
+ DATA_ORDER_RED_BLUE,
+ DATA_ORDER_BLUE_RED,
+};
+
+/* DC_DISP_DATA_ENABLE_OPTIONS 0x432 */
+#define DE_SELECT_SHIFT 0
+#define DE_SELECT_MASK (0x3 << DE_SELECT_SHIFT)
+#define DE_SELECT_ACTIVE_BLANK 0x0
+#define DE_SELECT_ACTIVE 0x1
+#define DE_SELECT_ACTIVE_IS 0x2
+#define DE_CONTROL_SHIFT 2
+#define DE_CONTROL_MASK (0x7 << DE_CONTROL_SHIFT)
+enum {
+ DE_CONTROL_ONECLK,
+ DE_CONTROL_NORMAL,
+ DE_CONTROL_EARLY_EXT,
+ DE_CONTROL_EARLY,
+ DE_CONTROL_ACTIVE_BLANK,
+};
+
+/* DC_WIN_WIN_OPTIONS 0x700 */
+#define H_DIRECTION BIT(0)
+enum {
+ H_DIRECTION_INCREMENT,
+ H_DIRECTION_DECREMENT,
+};
+#define V_DIRECTION BIT(2)
+enum {
+ V_DIRECTION_INCREMENT,
+ V_DIRECTION_DECREMENT,
+};
+#define COLOR_EXPAND BIT(6)
+#define CP_ENABLE BIT(16)
+#define DV_ENABLE BIT(20)
+#define WIN_ENABLE BIT(30)
+
+/* DC_WIN_BYTE_SWAP 0x701 */
+#define BYTE_SWAP_SHIFT 0
+#define BYTE_SWAP_MASK (3 << BYTE_SWAP_SHIFT)
+enum {
+ BYTE_SWAP_NOSWAP,
+ BYTE_SWAP_SWAP2,
+ BYTE_SWAP_SWAP4,
+ BYTE_SWAP_SWAP4HW
+};
+
+/* DC_WIN_POSITION 0x704 */
+#define H_POSITION_SHIFT 0
+#define H_POSITION_MASK (0x1FFF << H_POSITION_SHIFT)
+#define V_POSITION_SHIFT 16
+#define V_POSITION_MASK (0x1FFF << V_POSITION_SHIFT)
+
+/* DC_WIN_SIZE 0x705 */
+#define H_SIZE_SHIFT 0
+#define H_SIZE_MASK (0x1FFF << H_SIZE_SHIFT)
+#define V_SIZE_SHIFT 16
+#define V_SIZE_MASK (0x1FFF << V_SIZE_SHIFT)
+
+/* DC_WIN_PRESCALED_SIZE 0x706 */
+#define H_PRESCALED_SIZE_SHIFT 0
+#define H_PRESCALED_SIZE_MASK (0x7FFF << H_PRESCALED_SIZE)
+#define V_PRESCALED_SIZE_SHIFT 16
+#define V_PRESCALED_SIZE_MASK (0x1FFF << V_PRESCALED_SIZE)
+
+/* DC_WIN_DDA_INCREMENT 0x709 */
+#define H_DDA_INC_SHIFT 0
+#define H_DDA_INC_MASK (0xFFFF << H_DDA_INC_SHIFT)
+#define V_DDA_INC_SHIFT 16
+#define V_DDA_INC_MASK (0xFFFF << V_DDA_INC_SHIFT)
+
+#endif /* __ASM_ARCH_TEGRA_DC_H */
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_TEGRA_DISPLAY_H
+#define __ASM_ARCH_TEGRA_DISPLAY_H
+
+#include <asm/arch/dc.h>
+#include <fdtdec.h>
+
+/* This holds information about a window which can be displayed */
+struct disp_ctl_win {
+ enum win_color_depth_id fmt; /* Color depth/format */
+ unsigned bpp; /* Bits per pixel */
+ phys_addr_t phys_addr; /* Physical address in memory */
+ unsigned x; /* Horizontal address offset (bytes) */
+ unsigned y; /* Veritical address offset (bytes) */
+ unsigned w; /* Width of source window */
+ unsigned h; /* Height of source window */
+ unsigned stride; /* Number of bytes per line */
+ unsigned out_x; /* Left edge of output window (col) */
+ unsigned out_y; /* Top edge of output window (row) */
+ unsigned out_w; /* Width of output window in pixels */
+ unsigned out_h; /* Height of output window in pixels */
+};
+
+#define FDT_LCD_TIMINGS 4
+
+enum {
+ FDT_LCD_TIMING_REF_TO_SYNC,
+ FDT_LCD_TIMING_SYNC_WIDTH,
+ FDT_LCD_TIMING_BACK_PORCH,
+ FDT_LCD_TIMING_FRONT_PORCH,
+
+ FDT_LCD_TIMING_COUNT,
+};
+
+enum lcd_cache_t {
+ FDT_LCD_CACHE_OFF = 0,
+ FDT_LCD_CACHE_WRITE_THROUGH = 1 << 0,
+ FDT_LCD_CACHE_WRITE_BACK = 1 << 1,
+ FDT_LCD_CACHE_FLUSH = 1 << 2,
+ FDT_LCD_CACHE_WRITE_BACK_FLUSH = FDT_LCD_CACHE_WRITE_BACK |
+ FDT_LCD_CACHE_FLUSH,
+};
+
+/* Information about the display controller */
+struct fdt_disp_config {
+ int valid; /* config is valid */
+ int width; /* width in pixels */
+ int height; /* height in pixels */
+ int bpp; /* number of bits per pixel */
+
+ /*
+ * log2 of number of bpp, in general, unless it bpp is 24 in which
+ * case this field holds 24 also! This is a U-Boot thing.
+ */
+ int log2_bpp;
+ struct disp_ctlr *disp; /* Display controller to use */
+ fdt_addr_t frame_buffer; /* Address of frame buffer */
+ unsigned pixel_clock; /* Pixel clock in Hz */
+ uint horiz_timing[FDT_LCD_TIMING_COUNT]; /* Horizontal timing */
+ uint vert_timing[FDT_LCD_TIMING_COUNT]; /* Vertical timing */
+ int panel_node; /* node offset of panel information */
+};
+
+/* Information about the LCD panel */
+struct fdt_panel_config {
+ int pwm_channel; /* PWM channel to use for backlight */
+ enum lcd_cache_t cache_type;
+
+ struct fdt_gpio_state backlight_en; /* GPIO for backlight enable */
+ struct fdt_gpio_state lvds_shutdown; /* GPIO for lvds shutdown */
+ struct fdt_gpio_state backlight_vdd; /* GPIO for backlight vdd */
+ struct fdt_gpio_state panel_vdd; /* GPIO for panel vdd */
+ /*
+ * Panel required timings
+ * Timing 1: delay between panel_vdd-rise and data-rise
+ * Timing 2: delay between data-rise and backlight_vdd-rise
+ * Timing 3: delay between backlight_vdd and pwm-rise
+ * Timing 4: delay between pwm-rise and backlight_en-rise
+ */
+ uint panel_timings[FDT_LCD_TIMINGS];
+};
+
+/**
+ * Register a new display based on device tree configuration.
+ *
+ * The frame buffer can be positioned by U-Boot or overriden by the fdt.
+ * You should pass in the U-Boot address here, and check the contents of
+ * struct fdt_disp_config to see what was actually chosen.
+ *
+ * @param blob Device tree blob
+ * @param default_lcd_base Default address of LCD frame buffer
+ * @return 0 if ok, -1 on error (unsupported bits per pixel)
+ */
+int tegra_display_probe(const void *blob, void *default_lcd_base);
+
+/**
+ * Return the current display configuration
+ *
+ * @return pointer to display configuration, or NULL if there is no valid
+ * config
+ */
+struct fdt_disp_config *tegra_display_get_config(void);
+
+/**
+ * Perform the next stage of the LCD init if it is time to do so.
+ *
+ * LCD init can be time-consuming because of the number of delays we need
+ * while waiting for the backlight power supply, etc. This function can
+ * be called at various times during U-Boot operation to advance the
+ * initialization of the LCD to the next stage if sufficient time has
+ * passed since the last stage. It keeps track of what stage it is up to
+ * and the time that it is permitted to move to the next stage.
+ *
+ * The final call should have wait=1 to complete the init.
+ *
+ * @param blob fdt blob containing LCD information
+ * @param wait 1 to wait until all init is complete, and then return
+ * 0 to return immediately, potentially doing nothing if it is
+ * not yet time for the next init.
+ */
+int tegra_lcd_check_next_stage(const void *blob, int wait);
+
+/**
+ * Set up the maximum LCD size so we can size the frame buffer.
+ *
+ * @param blob fdt blob containing LCD information
+ */
+void tegra_lcd_early_init(const void *blob);
+
+#endif /*__ASM_ARCH_TEGRA_DISPLAY_H*/
void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
/* Set the complete configuration for a pin group */
-void pinmux_config_pingroup(struct pingroup_config *config);
+void pinmux_config_pingroup(const struct pingroup_config *config);
void pinmux_set_tristate(enum pmux_pingrp pin, int enable);
* @param config List of config items
* @param len Number of config items in list
*/
-void pinmux_config_table(struct pingroup_config *config, int len);
+void pinmux_config_table(const struct pingroup_config *config, int len);
#endif /* PINMUX_H */
--- /dev/null
+/*
+ * Tegra pulse width frequency modulator definitions
+ *
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_TEGRA_PWM_H
+#define __ASM_ARCH_TEGRA_PWM_H
+
+/* This is a single PWM channel */
+struct pwm_ctlr {
+ uint control; /* Control register */
+ uint reserved[3]; /* Space space */
+};
+
+#define PWM_NUM_CHANNELS 4
+
+/* PWM_CONTROLLER_PWM_CSR_0/1/2/3_0 */
+#define PWM_ENABLE_SHIFT 31
+#define PWM_ENABLE_MASK (0x1 << PWM_ENABLE_SHIFT)
+
+#define PWM_WIDTH_SHIFT 16
+#define PWM_WIDTH_MASK (0x7FFF << PWM_WIDTH_SHIFT)
+
+#define PWM_DIVIDER_SHIFT 0
+#define PWM_DIVIDER_MASK (0x1FFF << PWM_DIVIDER_SHIFT)
+
+/**
+ * Program the PWM with the given parameters.
+ *
+ * @param channel PWM channel to update
+ * @param rate Clock rate to use for PWM
+ * @param pulse_width high pulse width: 0=always low, 1=1/256 pulse high,
+ * n = n/256 pulse high
+ * @param freq_divider frequency divider value (1 to use rate as is)
+ */
+void pwm_enable(unsigned channel, int rate, int pulse_width, int freq_divider);
+
+/**
+ * Request a pwm channel as referenced by a device tree node.
+ *
+ * This channel can then be passed to pwm_enable().
+ *
+ * @param blob Device tree blob
+ * @param node Node containing reference to pwm
+ * @param prop_name Property name of pwm reference
+ * @return channel number, if ok, else -1
+ */
+int pwm_request(const void *blob, int node, const char *prop_name);
+
+/**
+ * Set up the pwm controller, by looking it up in the fdt.
+ *
+ * @return 0 if ok, -1 if the device tree node was not found or invalid.
+ */
+int pwm_init(const void *blob);
+
+#endif /* __ASM_ARCH_TEGRA_PWM_H */
unsigned long reloc_off;
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
unsigned long tlb_addr;
+ unsigned long tlb_size;
#endif
const void *fdt_blob; /* Our device tree, NULL if none */
void **jt; /* jump table */
#define METHOD_GPIO_24XX 4
+/**
+ * Check if gpio is valid.
+ *
+ * @param gpio GPIO number
+ * @return 1 if ok, 0 on error
+ */
+int gpio_is_valid(int gpio);
#endif /* _GPIO_H_ */
isb();
}
+/* options available for data cache on each page */
+enum dcache_option {
+ DCACHE_OFF = 0x12,
+ DCACHE_WRITETHROUGH = 0x1a,
+ DCACHE_WRITEBACK = 0x1e,
+};
+
+/* Size of an MMU section */
+enum {
+ MMU_SECTION_SHIFT = 20,
+ MMU_SECTION_SIZE = 1 << MMU_SECTION_SHIFT,
+};
+
+/**
+ * Change the cache settings for a region.
+ *
+ * \param start start address of memory region to change
+ * \param size size of memory region to change
+ * \param option dcache option to select
+ */
+void mmu_set_region_dcache_behaviour(u32 start, int size,
+ enum dcache_option option);
+
+/**
+ * Register an update to the page tables, and flush the TLB
+ *
+ * \param start start address of update in page table
+ * \param stop stop address of update in page table
+ */
+void mmu_page_table_flush(unsigned long start, unsigned long stop);
+
#endif /* __ASSEMBLY__ */
#define arch_align_stack(x) (x)
GLCOBJS += div0.o
+SOBJS-y += crt0.o
+
ifndef CONFIG_SPL_BUILD
COBJS-y += board.o
COBJS-y += bootm.o
COBJS-$(CONFIG_SYS_L2_PL310) += cache-pl310.o
-COBJS-y += interrupts.o
-COBJS-y += reset.o
SOBJS-$(CONFIG_USE_ARCH_MEMSET) += memset.o
SOBJS-$(CONFIG_USE_ARCH_MEMCPY) += memcpy.o
else
COBJS-$(CONFIG_SPL_FRAMEWORK) += spl.o
endif
+COBJS-y += interrupts.o
+COBJS-y += reset.o
+
COBJS-y += cache.o
COBJS-y += cache-cp15.o
#include <common.h>
#include <command.h>
+#include <environment.h>
#include <malloc.h>
#include <stdio_dev.h>
#include <version.h>
int power_init_board(void)
__attribute__((weak, alias("__power_init_board")));
+ /* Record the board_init_f() bootstage (after arch_cpu_init()) */
+static int mark_bootstage(void)
+{
+ bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f");
+
+ return 0;
+}
+
init_fnc_t *init_sequence[] = {
arch_cpu_init, /* basic arch cpu dependent setup */
-
-#if defined(CONFIG_BOARD_EARLY_INIT_F)
- board_early_init_f,
-#endif
+ mark_bootstage,
#ifdef CONFIG_OF_CONTROL
fdtdec_check_fdt,
+#endif
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+ board_early_init_f,
#endif
timer_init, /* initialize timer */
#ifdef CONFIG_BOARD_POSTCLK_INIT
void *new_fdt = NULL;
size_t fdt_size = 0;
- bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f");
-
- /* Pointer is writable since we allocated a register for it */
- gd = (gd_t *) ((CONFIG_SYS_INIT_SP_ADDR) & ~0x07);
- /* compiler optimization barrier needed for GCC >= 3.4 */
- __asm__ __volatile__("": : :"memory");
-
memset((void *)gd, 0, sizeof(gd_t));
gd->mon_len = _bss_end_ofs;
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
/* reserve TLB table */
- addr -= (4096 * 4);
+ gd->tlb_size = 4096 * 4;
+ addr -= gd->tlb_size;
/* round down to next 64 kB limit */
addr &= ~(0x10000 - 1);
gd->tlb_addr = addr;
- debug("TLB table at: %08lx\n", addr);
+ debug("TLB table from %08lx to %08lx\n", addr, addr + gd->tlb_size);
#endif
/* round down to next 4 kB limit */
gd->fdt_blob = new_fdt;
}
memcpy(id, (void *)gd, sizeof(gd_t));
-
- relocate_code(addr_sp, id, addr);
-
- /* NOTREACHED - relocate_code() does not return */
}
#if !defined(CONFIG_SYS_NO_FLASH)
#endif
/*
- ************************************************************************
+ * Tell if it's OK to load the environment early in boot.
+ *
+ * If CONFIG_OF_CONFIG is defined, we'll check with the FDT to see
+ * if this is OK (defaulting to saying it's not OK).
+ *
+ * NOTE: Loading the environment early can be a bad idea if security is
+ * important, since no verification is done on the environment.
+ *
+ * @return 0 if environment should not be loaded, !=0 if it is ok to load
+ */
+static int should_load_env(void)
+{
+#ifdef CONFIG_OF_CONTROL
+ return fdtdec_get_config_int(gd->fdt_blob, "load-environment", 0);
+#elif defined CONFIG_DELAY_ENVIRONMENT
+ return 0;
+#else
+ return 1;
+#endif
+}
+
+#if defined(CONFIG_DISPLAY_BOARDINFO_LATE) && defined(CONFIG_OF_CONTROL)
+static void display_fdt_model(const void *blob)
+{
+ const char *model;
+
+ model = (char *)fdt_getprop(blob, 0, "model", NULL);
+ printf("Model: %s\n", model ? model : "<unknown>");
+}
+#endif
+
+/************************************************************************
*
* This is the next part if the initialization sequence: we are now
* running from RAM and have a "normal" C environment, i. e. global
ulong flash_size;
#endif
- gd = id;
-
gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_R, "board_init_r");
#endif
#ifdef CONFIG_GENERIC_MMC
- puts("MMC: ");
- mmc_initialize(gd->bd);
+ puts("MMC: ");
+ mmc_initialize(gd->bd);
#endif
#ifdef CONFIG_HAS_DATAFLASH
#endif
/* initialize environment */
- env_relocate();
+ if (should_load_env())
+ env_relocate();
+ else
+ set_default_env(NULL);
#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
arm_pci_init();
console_init_r(); /* fully init console as a device */
+#ifdef CONFIG_DISPLAY_BOARDINFO_LATE
+# ifdef CONFIG_OF_CONTROL
+ /* Put this here so it appears on the LCD, now it is ready */
+ display_fdt_model(gd->fdt_blob);
+# else
+ checkboard();
+# endif
+#endif
+
#if defined(CONFIG_ARCH_MISC_INIT)
/* miscellaneous arch dependent initialisations */
arch_misc_init();
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
-#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
-#define CACHE_SETUP 0x1a
-#else
-#define CACHE_SETUP 0x1e
-#endif
-
DECLARE_GLOBAL_DATA_PTR;
void __arm_init_before_mmu(void)
asm volatile("" : : : "memory");
}
-static inline void dram_bank_mmu_setup(int bank)
+void set_section_dcache(int section, enum dcache_option option)
+{
+ u32 *page_table = (u32 *)gd->tlb_addr;
+ u32 value;
+
+ value = (section << MMU_SECTION_SHIFT) | (3 << 10);
+ value |= option;
+ page_table[section] = value;
+}
+
+void __mmu_page_table_flush(unsigned long start, unsigned long stop)
+{
+ debug("%s: Warning: not implemented\n", __func__);
+}
+
+void mmu_page_table_flush(unsigned long start, unsigned long stop)
+ __attribute__((weak, alias("__mmu_page_table_flush")));
+
+void mmu_set_region_dcache_behaviour(u32 start, int size,
+ enum dcache_option option)
{
u32 *page_table = (u32 *)gd->tlb_addr;
+ u32 upto, end;
+
+ end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
+ start = start >> MMU_SECTION_SHIFT;
+ debug("%s: start=%x, size=%x, option=%d\n", __func__, start, size,
+ option);
+ for (upto = start; upto < end; upto++)
+ set_section_dcache(upto, option);
+ mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]);
+}
+
+static inline void dram_bank_mmu_setup(int bank)
+{
bd_t *bd = gd->bd;
int i;
for (i = bd->bi_dram[bank].start >> 20;
i < (bd->bi_dram[bank].start + bd->bi_dram[bank].size) >> 20;
i++) {
- page_table[i] = i << 20 | (3 << 10) | CACHE_SETUP;
+#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
+ set_section_dcache(i, DCACHE_WRITETHROUGH);
+#else
+ set_section_dcache(i, DCACHE_WRITEBACK);
+#endif
}
}
/* to activate the MMU we need to set up virtual memory: use 1M areas */
static inline void mmu_setup(void)
{
- u32 *page_table = (u32 *)gd->tlb_addr;
int i;
u32 reg;
arm_init_before_mmu();
/* Set up an identity-mapping for all 4GB, rw for everyone */
for (i = 0; i < 4096; i++)
- page_table[i] = i << 20 | (3 << 10) | 0x12;
+ set_section_dcache(i, DCACHE_OFF);
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
dram_bank_mmu_setup(i);
/* Copy the page table address to cp15 */
asm volatile("mcr p15, 0, %0, c2, c0, 0"
- : : "r" (page_table) : "memory");
+ : : "r" (gd->tlb_addr) : "memory");
/* Set the access control to all-supervisor */
asm volatile("mcr p15, 0, %0, c3, c0, 0"
: : "r" (~0));
return;
/* if disabling data cache, disable mmu too */
cache_bit |= CR_M;
- flush_dcache_all();
}
+ reg = get_cr();
+ cp_delay();
+ if (cache_bit == (CR_C | CR_M))
+ flush_dcache_all();
set_cr(reg & ~cache_bit);
}
#endif
--- /dev/null
+/*
+ * crt0 - C-runtime startup Code for ARM U-Boot
+ *
+ * Copyright (c) 2012 Albert ARIBAUD <albert.u.boot@aribaud.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm-offsets.h>
+
+/*
+ * This file handles the target-independent stages of the U-Boot
+ * start-up where a C runtime environment is needed. Its entry point
+ * is _main and is branched into from the target's start.S file.
+ *
+ * _main execution sequence is:
+ *
+ * 1. Set up initial environment for calling board_init_f().
+ * This environment only provides a stack and a place to store
+ * the GD ('global data') structure, both located in some readily
+ * available RAM (SRAM, locked cache...). In this context, VARIABLE
+ * global data, initialized or not (BSS), are UNAVAILABLE; only
+ * CONSTANT initialized data are available.
+ *
+ * 2. Call board_init_f(). This function prepares the hardware for
+ * execution from system RAM (DRAM, DDR...) As system RAM may not
+ * be available yet, , board_init_f() must use the current GD to
+ * store any data which must be passed on to later stages. These
+ * data include the relocation destination, the future stack, and
+ * the future GD location.
+ *
+ * (the following applies only to non-SPL builds)
+ *
+ * 3. Set up intermediate environment where the stack and GD are the
+ * ones allocated by board_init_f() in system RAM, but BSS and
+ * initialized non-const data are still not available.
+ *
+ * 4. Call relocate_code(). This function relocates U-Boot from its
+ * current location into the relocation destination computed by
+ * board_init_f().
+ *
+ * 5. Set up final environment for calling board_init_r(). This
+ * environment has BSS (initialized to 0), initialized non-const
+ * data (initialized to their intended value), and stack in system
+ * RAM. GD has retained values set by board_init_f(). Some CPUs
+ * have some work left to do at this point regarding memory, so
+ * call c_runtime_cpu_setup.
+ *
+ * 6. Branch to either nand_boot() or board_init_r().
+ */
+
+/*
+ * declare nand_boot() or board_init_r() to jump to at end of crt0
+ */
+
+#if defined(CONFIG_NAND_SPL)
+
+.globl nand_boot
+
+#elif ! defined(CONFIG_SPL_BUILD)
+
+.globl board_init_r
+
+#endif
+
+/*
+ * start and end of BSS
+ */
+
+.globl __bss_start
+.globl __bss_end__
+
+/*
+ * entry point of crt0 sequence
+ */
+
+.global _main
+
+_main:
+
+/*
+ * Set up initial C runtime environment and call board_init_f(0).
+ */
+
+#if defined(CONFIG_NAND_SPL)
+ /* deprecated, use instead CONFIG_SPL_BUILD */
+ ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
+#elif defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
+ ldr sp, =(CONFIG_SPL_STACK)
+#else
+ ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
+#endif
+ bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
+ sub sp, #GD_SIZE /* allocate one GD above SP */
+ bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
+ mov r8, sp /* GD is above SP */
+ mov r0, #0
+ bl board_init_f
+
+#if ! defined(CONFIG_SPL_BUILD)
+
+/*
+ * Set up intermediate environment (new sp and gd) and call
+ * relocate_code(addr_sp, gd, addr_moni). Trick here is that
+ * we'll return 'here' but relocated.
+ */
+
+ ldr sp, [r8, #GD_START_ADDR_SP] /* r8 = gd->start_addr_sp */
+ bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
+ ldr r8, [r8, #GD_BD] /* r8 = gd->bd */
+ sub r8, r8, #GD_SIZE /* new GD is below bd */
+
+ adr lr, here
+ ldr r0, [r8, #GD_RELOC_OFF] /* lr = gd->start_addr_sp */
+ add lr, lr, r0
+ ldr r0, [r8, #GD_START_ADDR_SP] /* r0 = gd->start_addr_sp */
+ mov r1, r8 /* r1 = gd */
+ ldr r2, [r8, #GD_RELOCADDR] /* r2 = gd->relocaddr */
+ b relocate_code
+here:
+
+/* Set up final (full) environment */
+
+ bl c_runtime_cpu_setup /* we still call old routine here */
+
+ ldr r0, =__bss_start /* this is auto-relocated! */
+ ldr r1, =__bss_end__ /* this is auto-relocated! */
+
+ mov r2, #0x00000000 /* prepare zero to clear BSS */
+
+clbss_l:cmp r0, r1 /* while not at end of BSS */
+ strlo r2, [r0] /* clear 32-bit BSS word */
+ addlo r0, r0, #4 /* move to next */
+ blo clbss_l
+
+ bl coloured_LED_init
+ bl red_led_on
+
+#if defined(CONFIG_NAND_SPL)
+
+ /* call _nand_boot() */
+ ldr pc, =nand_boot
+
+#else
+
+ /* call board_init_r(gd_t *id, ulong dest_addr) */
+ mov r0, r8 /* gd_t */
+ ldr r1, [r8, #GD_RELOCADDR] /* dest_addr */
+ /* call board_init_r */
+ ldr pc, =board_init_r /* this is auto-relocated! */
+
+#endif
+
+ /* we should not return here. */
+
+#endif
gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
- serial_initialize();
-
debug ("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
WATCHDOG_RESET ();
gd->reloc_off = dest_addr - CONFIG_SYS_MONITOR_BASE;
+ serial_initialize();
+
monitor_flash_len = (ulong)&__init_end - dest_addr;
#if defined(CONFIG_NEEDS_MANUAL_RELOC)
# include <asm/cpu_sh7724.h>
#elif defined (CONFIG_CPU_SH7734)
# include <asm/cpu_sh7734.h>
+#elif defined (CONFIG_CPU_SH7752)
+# include <asm/cpu_sh7752.h>
#elif defined (CONFIG_CPU_SH7757)
# include <asm/cpu_sh7757.h>
#elif defined (CONFIG_CPU_SH7763)
--- /dev/null
+/*
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _ASM_CPU_SH7752_H_
+#define _ASM_CPU_SH7752_H_
+
+#define CCR 0xFF00001C
+#define WTCNT 0xFFCC0000
+#define CCR_CACHE_INIT 0x0000090b
+#define CACHE_OC_NUM_WAYS 1
+
+#ifndef __ASSEMBLY__ /* put C only stuff in this section */
+/* MMU */
+struct mmu_regs {
+ unsigned int reserved[4];
+ unsigned int mmucr;
+};
+#define MMU_BASE ((struct mmu_regs *)0xff000000)
+
+/* Watchdog */
+#define WTCSR0 0xffcc0002
+#define WRSTCSR_R 0xffcc0003
+#define WRSTCSR_W 0xffcc0002
+#define WTCSR_PREFIX 0xa500
+#define WRSTCSR_PREFIX 0x6900
+#define WRSTCSR_WOVF_PREFIX 0x9600
+
+/* SCIF */
+#define SCIF0_BASE 0xfe4b0000 /* The real name is SCIF2 */
+#define SCIF1_BASE 0xfe4c0000 /* The real name is SCIF3 */
+#define SCIF2_BASE 0xfe4d0000 /* The real name is SCIF4 */
+
+/* TMU0 */
+#define TMU_BASE 0xFE430000
+
+/* ETHER, GETHER MAC address */
+struct ether_mac_regs {
+ unsigned int reserved[114];
+ unsigned int mahr;
+ unsigned int reserved2;
+ unsigned int malr;
+};
+#define GETHER0_MAC_BASE ((struct ether_mac_regs *)0xfee0400)
+#define GETHER1_MAC_BASE ((struct ether_mac_regs *)0xfee0c00)
+#define ETHER0_MAC_BASE ((struct ether_mac_regs *)0xfef0000)
+#define ETHER1_MAC_BASE ((struct ether_mac_regs *)0xfef0800)
+
+/* GETHER */
+struct gether_control_regs {
+ unsigned int gbecont;
+};
+#define GETHER_CONTROL_BASE ((struct gether_control_regs *)0xffc10100)
+#define GBECONT_RMII1 0x00020000
+#define GBECONT_RMII0 0x00010000
+
+/* SerMux */
+struct sermux_regs {
+ unsigned char smr0;
+ unsigned char smr1;
+ unsigned char smr2;
+ unsigned char smr3;
+ unsigned char smr4;
+ unsigned char smr5;
+};
+#define SERMUX_BASE ((struct sermux_regs *)0xfe470000)
+
+
+/* USB0/1 */
+struct usb_common_regs {
+ unsigned short reserved[129];
+ unsigned short suspmode;
+};
+#define USB0_COMMON_BASE ((struct usb_common_regs *)0xfe450000)
+#define USB1_COMMON_BASE ((struct usb_common_regs *)0xfe4f0000)
+
+struct usb0_phy_regs {
+ unsigned short reset;
+ unsigned short reserved[4];
+ unsigned short portsel;
+};
+#define USB0_PHY_BASE ((struct usb0_phy_regs *)0xfe5f0000)
+
+struct usb1_port_regs {
+ unsigned int port1sel;
+ unsigned int reserved;
+ unsigned int usb1intsts;
+};
+#define USB1_PORT_BASE ((struct usb1_port_regs *)0xfe4f2000)
+
+struct usb1_alignment_regs {
+ unsigned int ehcidatac; /* 0xfe4fe018 */
+ unsigned int reserved[63];
+ unsigned int ohcidatac;
+};
+#define USB1_ALIGNMENT_BASE ((struct usb1_alignment_regs *)0xfe4fe018)
+
+/* GPIO */
+struct gpio_regs {
+ unsigned short pacr;
+ unsigned short pbcr;
+ unsigned short pccr;
+ unsigned short pdcr;
+ unsigned short pecr;
+ unsigned short pfcr;
+ unsigned short pgcr;
+ unsigned short phcr;
+ unsigned short picr;
+ unsigned short pjcr;
+ unsigned short pkcr;
+ unsigned short plcr;
+ unsigned short pmcr;
+ unsigned short pncr;
+ unsigned short pocr;
+ unsigned short reserved;
+ unsigned short pqcr;
+ unsigned short prcr;
+ unsigned short pscr;
+ unsigned short ptcr;
+ unsigned short pucr;
+ unsigned short pvcr;
+ unsigned short pwcr;
+ unsigned short pxcr;
+ unsigned short pycr;
+ unsigned short pzcr;
+ unsigned char padr;
+ unsigned char reserved_a;
+ unsigned char pbdr;
+ unsigned char reserved_b;
+ unsigned char pcdr;
+ unsigned char reserved_c;
+ unsigned char pddr;
+ unsigned char reserved_d;
+ unsigned char pedr;
+ unsigned char reserved_e;
+ unsigned char pfdr;
+ unsigned char reserved_f;
+ unsigned char pgdr;
+ unsigned char reserved_g;
+ unsigned char phdr;
+ unsigned char reserved_h;
+ unsigned char pidr;
+ unsigned char reserved_i;
+ unsigned char pjdr;
+ unsigned char reserved_j;
+ unsigned char pkdr;
+ unsigned char reserved_k;
+ unsigned char pldr;
+ unsigned char reserved_l;
+ unsigned char pmdr;
+ unsigned char reserved_m;
+ unsigned char pndr;
+ unsigned char reserved_n;
+ unsigned char podr;
+ unsigned char reserved_o;
+ unsigned char ppdr;
+ unsigned char reserved_p;
+ unsigned char pqdr;
+ unsigned char reserved_q;
+ unsigned char prdr;
+ unsigned char reserved_r;
+ unsigned char psdr;
+ unsigned char reserved_s;
+ unsigned char ptdr;
+ unsigned char reserved_t;
+ unsigned char pudr;
+ unsigned char reserved_u;
+ unsigned char pvdr;
+ unsigned char reserved_v;
+ unsigned char pwdr;
+ unsigned char reserved_w;
+ unsigned char pxdr;
+ unsigned char reserved_x;
+ unsigned char pydr;
+ unsigned char reserved_y;
+ unsigned char pzdr;
+ unsigned char reserved_z;
+ unsigned short ncer;
+ unsigned short ncmcr;
+ unsigned short nccsr;
+ unsigned char reserved2[2];
+ unsigned short psel0; /* +0x70 */
+ unsigned short psel1;
+ unsigned short psel2;
+ unsigned short psel3;
+ unsigned short psel4;
+ unsigned short psel5;
+ unsigned short psel6;
+ unsigned short reserved3[2];
+ unsigned short psel7;
+};
+#define GPIO_BASE ((struct gpio_regs *)0xffec0000)
+
+#endif /* ifndef __ASSEMBLY__ */
+#endif /* _ASM_CPU_SH7752_H_ */
NET2BIG_V2_OE_LOW, NET2BIG_V2_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
- u32 kwmpp_config[] = {
+ static const u32 kwmpp_config[] = {
MPP0_SPI_SCn,
MPP1_SPI_MOSI,
MPP2_SPI_SCK,
NETSPACE_V2_OE_LOW, NETSPACE_V2_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
- u32 kwmpp_config[] = {
+ static const u32 kwmpp_config[] = {
MPP0_SPI_SCn,
MPP1_SPI_MOSI,
MPP2_SPI_SCK,
--- /dev/null
+#
+# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+#
+# Based on Kirkwood support:
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := $(BOARD).o ../common/common.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#
+# Copyright (C) 2012 Albert ARIBAUD <albert.u.boot@aribaud.net>
+#
+# Based on netspace_v2 kwbimage.cfg:
+# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+#
+# Based on Kirkwood support:
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM nand # Boot from NAND flash
+NAND_PAGE_SIZE 800
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Values taken from image original LaCie U-Boot header dump!
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1B1B1B9B
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000c30 # DDR Configuration register
+
+DATA 0xFFD01404 0x37743000 # DDR Controller Control Low
+
+DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1)
+
+DATA 0xFFD0140C 0x00000A19 # DDR Timing (High)
+
+DATA 0xFFD01410 0x0000CCCC # DDR Address Control
+
+DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
+
+DATA 0xFFD01418 0x00000000 # DDR Operation
+
+DATA 0xFFD0141C 0x00000662 # DDR Mode
+
+DATA 0xFFD01420 0x00000004 # DDR Extended Mode
+
+DATA 0xFFD01424 0x0000F07F # DDR Controller Control High
+
+DATA 0xFFD01428 0x00096630 # DDR2 ODT Read Timing (default values)
+
+DATA 0xFFD0147C 0x00009663 # DDR2 ODT Write Timing (default values)
+
+DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
+DATA 0xFFD01508 0x00000000 # CS[1]n Base address to 0x0
+DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
+DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
+DATA 0xFFD01494 0x00120012 # DDR ODT Control (Low)
+DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
+DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
+DATA 0xFFD01480 0x00000001 # DDR Initialization Control
+DATA 0xFFD20134 0x66666666
+DATA 0xFFD20138 0x66666666
+DATA 0xFFD10000 0x01112222
+DATA 0xFFD1000C 0x00000000
+DATA 0xFFD10104 0x00000000
+DATA 0xFFD10100 0x40000000
+# End of Header extension
+DATA 0x0 0x0
--- /dev/null
+/*
+ * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+ *
+ * Based on Kirkwood support:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/kirkwood.h>
+#include <asm/arch/mpp.h>
+#include <asm/arch/gpio.h>
+
+#include "../common/common.h"
+#include "netdev.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* GPIO configuration: start FAN at low speed, USB and HDD */
+
+#define WIRELESS_SPACE_OE_LOW 0xFF006808
+#define WIRELESS_SPACE_OE_HIGH 0x0000F989
+#define WIRELESS_SPACE_OE_VAL_LOW 0x00010080
+#define WIRELESS_SPACE_OE_VAL_HIGH 0x00000240
+
+#define WIRELESS_SPACE_REAR_BUTTON 13
+#define WIRELESS_SPACE_FRONT_BUTTON 43
+
+const u32 kwmpp_config[] = {
+ MPP0_NF_IO2,
+ MPP1_NF_IO3,
+ MPP2_NF_IO4,
+ MPP3_NF_IO5,
+ MPP4_NF_IO6,
+ MPP5_NF_IO7,
+ MPP6_SYSRST_OUTn,
+ MPP7_GPO, /* Fan speed (bit 1) */
+ MPP8_TW_SDA,
+ MPP9_TW_SCK,
+ MPP10_UART0_TXD,
+ MPP11_UART0_RXD,
+ MPP13_GPIO, /* Red led */
+ MPP14_GPIO, /* USB fuse */
+ MPP15_SATA0_ACTn,
+ MPP16_GPIO, /* SATA 0 power */
+ MPP17_GPIO, /* SATA 1 power */
+ MPP18_NF_IO0,
+ MPP19_NF_IO1,
+ MPP20_GE1_0, /* Gigabit Ethernet 1 */
+ MPP21_GE1_1,
+ MPP22_GE1_2,
+ MPP23_GE1_3,
+ MPP24_GE1_4,
+ MPP25_GE1_5,
+ MPP26_GE1_6,
+ MPP27_GE1_7,
+ MPP28_GE1_8,
+ MPP29_GE1_9,
+ MPP30_GE1_10,
+ MPP31_GE1_11,
+ MPP32_GE1_12,
+ MPP33_GE1_13,
+ MPP34_GE1_14,
+ MPP35_GE1_15,
+ MPP36_GPIO, /* Fan speed (bit 2) */
+ MPP37_GPIO, /* Fan speed (bit 0) */
+ MPP38_GPIO, /* Fan power */
+ MPP39_GPIO, /* Fan rotation fail */
+ MPP40_GPIO, /* Ethernet switch link */
+ MPP41_GPIO, /* USB enable host vbus */
+ MPP42_GPIO, /* LED clock control */
+ MPP43_GPIO, /* WPS button (0=Pushed, 1=Released) */
+ MPP44_GPIO, /* Red LED on/off */
+ MPP45_GPIO, /* Red LED timer blink (on=off=100ms) */
+ MPP46_GPIO, /* Green LED on/off */
+ MPP47_GPIO, /* LED (blue, green) SATA activity blink */
+ MPP48_GPIO, /* Blue LED on/off */
+ 0
+};
+
+struct mv88e61xx_config swcfg = {
+ .name = "egiga0",
+ .vlancfg = MV88E61XX_VLANCFG_ROUTER,
+ .rgmii_delay = MV88E61XX_RGMII_DELAY_EN,
+ .led_init = MV88E61XX_LED_INIT_EN,
+ .mdip = MV88E61XX_MDIP_NOCHANGE,
+ .portstate = MV88E61XX_PORTSTT_FORWARDING,
+ .cpuport = 0x20,
+ .ports_enabled = 0x3F,
+};
+
+int board_early_init_f(void)
+{
+ /* Gpio configuration */
+ kw_config_gpio(WIRELESS_SPACE_OE_VAL_LOW, WIRELESS_SPACE_OE_VAL_HIGH,
+ WIRELESS_SPACE_OE_LOW, WIRELESS_SPACE_OE_HIGH);
+
+ /* Multi-Purpose Pins Functionality configuration */
+ kirkwood_mpp_conf(kwmpp_config, NULL);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* Machine number */
+ gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
+
+ /* Boot parameters address */
+ gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+
+ return 0;
+}
+
+#if defined(CONFIG_MISC_INIT_R)
+int misc_init_r(void)
+{
+#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
+ if (!getenv("ethaddr")) {
+ uchar mac[6];
+ if (lacie_read_mac_address(mac) == 0)
+ eth_setenv_enetaddr("ethaddr", mac);
+ }
+#endif
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
+/* Configure and initialize PHY */
+void reset_phy(void)
+{
+ /* configure switch on egiga0 */
+ mv88e61xx_switch_initialize(&swcfg);
+}
+#endif
+
+#if defined(CONFIG_KIRKWOOD_GPIO) && defined(CONFIG_WIRELESS_SPACE_CMD)
+/* Return GPIO button status */
+static int
+do_ws(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ if (strcmp(argv[1], "button") == 0) {
+ if (strcmp(argv[2], "rear") == 0)
+ /* invert GPIO result for intuitive while/until use */
+ return !kw_gpio_get_value(WIRELESS_SPACE_REAR_BUTTON);
+ else if (strcmp(argv[2], "front") == 0)
+ return kw_gpio_get_value(WIRELESS_SPACE_FRONT_BUTTON);
+ else
+ return -1;
+ } else {
+ return -1;
+ }
+}
+
+U_BOOT_CMD(ws, 3, 0, do_ws,
+ "Return GPIO button status 0=off 1=on",
+ "- ws button rear|front: test buttons' states\n"
+);
+#endif
DREAMPLUG_OE_LOW, DREAMPLUG_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
- u32 kwmpp_config[] = {
+ static const u32 kwmpp_config[] = {
MPP0_SPI_SCn, /* SPI Flash */
MPP1_SPI_MOSI,
MPP2_SPI_SCK,
GURUPLUG_OE_LOW, GURUPLUG_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
- u32 kwmpp_config[] = {
+ static const u32 kwmpp_config[] = {
MPP0_NF_IO2,
MPP1_NF_IO3,
MPP2_NF_IO4,
MV88F6281GTW_GE_OE_LOW, MV88F6281GTW_GE_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
- u32 kwmpp_config[] = {
+ static const u32 kwmpp_config[] = {
MPP0_SPI_SCn,
MPP1_SPI_MOSI,
MPP2_SPI_SCK,
OPENRD_OE_LOW, OPENRD_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
- u32 kwmpp_config[] = {
+ static const u32 kwmpp_config[] = {
MPP0_NF_IO2,
MPP1_NF_IO3,
MPP2_NF_IO4,
RD6281A_OE_LOW, RD6281A_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
- u32 kwmpp_config[] = {
+ static const u32 kwmpp_config[] = {
MPP0_NF_IO2,
MPP1_NF_IO3,
MPP2_NF_IO4,
SHEEVAPLUG_OE_LOW, SHEEVAPLUG_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
- u32 kwmpp_config[] = {
+ static const u32 kwmpp_config[] = {
MPP0_NF_IO2,
MPP1_NF_IO3,
MPP2_NF_IO4,
DOCKSTAR_OE_LOW, DOCKSTAR_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
- u32 kwmpp_config[] = {
+ static const u32 kwmpp_config[] = {
MPP0_NF_IO2,
MPP1_NF_IO3,
MPP2_NF_IO4,
at91_macb_hw_init();
#endif
+#if defined(CONFIG_USB_OHCI_NEW) || defined(CONFIG_USB_EHCI)
+ at91_uhp_hw_init();
+#endif
#ifdef CONFIG_LCD
at91sam9x5ek_lcd_hw_init();
#endif
* you can do this only with a working network connection. Therefore, a random
* ethernet address is generated if none is set and a DHCP request is sent.
* After a successful DHCP response is received, the network settings are
- * configured and the ncip parameter is set to the serverip. Eg. for a working
- * resuce mode, you should set 'next-server' to the host where the netconsole
- * client is started.
+ * configured and the ncip is unset. Therefore, all netconsole packets are
+ * broadcasted.
* Additionally, the bootsource is set to 'rescue'.
*/
* Multi-Purpose Pins Functionality configuration
* These strappings are taken from the original vendor uboot port.
*/
- u32 kwmpp_config[] = {
+ static const u32 kwmpp_config[] = {
MPP0_SPI_SCn,
MPP1_SPI_MOSI,
MPP2_SPI_SCK,
POGO_E02_OE_LOW, POGO_E02_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
- u32 kwmpp_config[] = {
+ static const u32 kwmpp_config[] = {
MPP0_NF_IO2,
MPP1_NF_IO3,
MPP2_NF_IO4,
#include <netdev.h>
#include <net.h>
#include <i2c.h>
+#include <usb.h>
#include <twl4030.h>
#include <linux/compiler.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-types.h>
+#include <asm/ehci-omap.h>
+#include <asm/gpio.h>
#include "eeprom.h"
MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA6*/
MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA7*/
+ /* USB EHCI */
+ MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT0*/
+ MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT1*/
+ MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT2*/
+ MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT3*/
+ MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT4*/
+ MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT5*/
+ MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT6*/
+ MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT7*/
+ MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DIR*/
+ MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_NXT*/
+ MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB1_CLK*/
+ MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB1_STP*/
+
+ MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT0*/
+ MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT1*/
+ MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M3)); /*HSUSB2_DT2*/
+ MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M3)); /*HSUSB2_DT3*/
+ MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | EN | M3)); /*HSUSB2_DT4*/
+ MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | EN | M3)); /*HSUSB2_DT5*/
+ MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M3)); /*HSUSB2_DT6*/
+ MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M3)); /*HSUSB2_DT7*/
+ MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DIR*/
+ MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_NXT*/
+ MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB2_CLK*/
+ MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_STP*/
+
+ /* SB_T35_USB_HUB_RESET_GPIO */
+ MUX_VAL(CP(CAM_WEN), (IDIS | PTD | DIS | M4)); /*GPIO_167*/
+
/* I2C1 */
MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)); /*I2C1_SCL*/
MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)); /*I2C1_SDA*/
serialnr->low = 0;
serialnr->high = 0;
};
+
+#ifdef CONFIG_USB_EHCI_OMAP
+struct omap_usbhs_board_data usbhs_bdata = {
+ .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
+ .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
+ .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
+};
+
+#define SB_T35_USB_HUB_RESET_GPIO 167
+int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+{
+ u8 val;
+ int offset;
+
+ if (gpio_request(SB_T35_USB_HUB_RESET_GPIO, "SB-T35 usb hub reset")) {
+ printf("Error: can't obtain GPIO %d for SB-T35 usb hub reset",
+ SB_T35_USB_HUB_RESET_GPIO);
+ return -1;
+ }
+
+ gpio_direction_output(SB_T35_USB_HUB_RESET_GPIO, 0);
+ udelay(10);
+ gpio_set_value(SB_T35_USB_HUB_RESET_GPIO, 1);
+ udelay(1000);
+
+ offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_GPIODATADIR1;
+ twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, &val, offset);
+ /* Set GPIO6 and GPIO7 of TPS65930 as output */
+ val |= 0xC0;
+ twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, val, offset);
+ offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_SETGPIODATAOUT1;
+ /* Take both PHYs out of reset */
+ twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0xC0, offset);
+ udelay(1);
+
+ return omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor);
+}
+
+int ehci_hcd_stop(void)
+{
+ return omap_ehci_hcd_stop();
+}
+
+#endif /* CONFIG_USB_EHCI_OMAP */
pin_mux_mmc();
debug("board_mmc_init: init eMMC\n");
- /* init dev 0, eMMC chip, with 4-bit bus */
- /* The board has an 8-bit bus, but 8-bit doesn't work yet */
- tegra_mmc_init(0, 4, -1, -1);
+ /* init dev 0, eMMC chip, with 8-bit bus */
+ tegra_mmc_init(0, 8, -1, -1);
debug("board_mmc_init: init SD slot\n");
/* init dev 3, SD slot, with 4-bit bus */
aliases {
usb0 = "/usb@c5008000";
+ usb1 = "/usb@c5000000";
};
memory {
};
usb@c5000000 {
- status = "disabled";
+ nvidia,vbus-gpio = <&gpio 170 0>; /* PV2 */
};
usb@c5004000 {
#include <mmc.h>
#endif
+void pin_mux_usb(void)
+{
+ /*
+ * USB1 internal/external mux GPIO, which masquerades as a VBUS GPIO
+ * in the current device tree.
+ */
+ pinmux_tristate_disable(PINGRP_UAC);
+}
void pin_mux_spi(void)
{
* provides the timing values back to the function that configures
* the memory. We have either one or two banks of 128MB DDR.
*/
-void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
- u32 *mr)
+void get_board_mem_timings(struct board_sdrc_timings *timings)
{
/* General SDRC config */
- *mcfg = MICRON_V_MCFG_165(128 << 20);
- *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+ timings->mcfg = MICRON_V_MCFG_165(128 << 20);
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
/* AC timings */
- *ctrla = MICRON_V_ACTIMA_165;
- *ctrlb = MICRON_V_ACTIMB_165;
- *mr = MICRON_V_MR_165;
+ timings->ctrla = MICRON_V_ACTIMA_165;
+ timings->ctrlb = MICRON_V_ACTIMB_165;
+ timings->mr = MICRON_V_MR_165;
}
DNS325_OE_LOW, DNS325_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
- u32 kwmpp_config[] = {
+ static const u32 kwmpp_config[] = {
MPP0_NF_IO2,
MPP1_NF_IO3,
MPP2_NF_IO4,
DECLARE_GLOBAL_DATA_PTR;
-#ifdef CONFIG_HW_WATCHDOG
-void hw_watchdog_reset(void)
-{
- mxc_hw_watchdog_reset();
-}
-#endif
-
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
pmic_reg_write(p, REG_INT_STATUS1, RTCRSTI);
#ifdef CONFIG_HW_WATCHDOG
- mxc_hw_watchdog_enable();
+ hw_watchdog_init();
#endif
return 0;
#include <common.h>
#include <asm/io.h>
+#include <asm/gpio.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/imx25-pinmux.h>
#include <asm/arch/sys_proto.h>
+#include <asm/arch/clock.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <fsl_pmic.h>
+#include <mc34704.h>
+
+#define FEC_RESET_B IMX_GPIO_NR(2, 3)
+#define FEC_ENABLE_B IMX_GPIO_NR(4, 8)
+#define CARD_DETECT IMX_GPIO_NR(2, 1)
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg esdhc_cfg[1] = {
+ {IMX_MMC_SDHC1_BASE},
+};
+#endif
+
+static void mx25pdk_fec_init(void)
+{
+ struct iomuxc_mux_ctl *muxctl;
+ struct iomuxc_pad_ctl *padctl;
+ u32 gpio_mux_mode = MX25_PIN_MUX_MODE(5);
+ u32 gpio_mux_mode0_sion = MX25_PIN_MUX_MODE(0) | MX25_PIN_MUX_SION;
+
+ /* FEC pin init is generic */
+ mx25_fec_init_pins();
+
+ muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
+ padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
+ /*
+ * Set up FEC_RESET_B and FEC_ENABLE_B
+ *
+ * FEC_RESET_B: gpio2_3 is ALT 5 mode of pin D12
+ * FEC_ENABLE_B: gpio4_8 is ALT 5 mode of pin A17
+ */
+ writel(gpio_mux_mode, &muxctl->pad_d12);
+ writel(gpio_mux_mode, &muxctl->pad_a17);
+
+ writel(0x0, &padctl->pad_d12);
+ writel(0x0, &padctl->pad_a17);
+
+ /* Assert RESET and ENABLE low */
+ gpio_direction_output(FEC_RESET_B, 0);
+ gpio_direction_output(FEC_ENABLE_B, 0);
+
+ udelay(10);
+
+ /* Deassert RESET and ENABLE */
+ gpio_set_value(FEC_RESET_B, 1);
+ gpio_set_value(FEC_ENABLE_B, 1);
+
+ /* Setup I2C pins so that PMIC can turn on PHY supply */
+ writel(gpio_mux_mode0_sion, &muxctl->pad_i2c1_clk);
+ writel(gpio_mux_mode0_sion, &muxctl->pad_i2c1_dat);
+ writel(0x1E8, &padctl->pad_i2c1_clk);
+ writel(0x1E8, &padctl->pad_i2c1_dat);
+}
+
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
return 0;
}
+int board_late_init(void)
+{
+ struct pmic *p;
+ int ret;
+
+ mx25pdk_fec_init();
+
+ ret = pmic_init(I2C_PMIC);
+ if (ret)
+ return ret;
+
+ p = pmic_get("FSL_PMIC");
+ if (!p)
+ return -ENODEV;
+
+ /* Turn on Ethernet PHY supply */
+ pmic_reg_write(p, MC34704_GENERAL2_REG, ONOFFE);
+
+ return 0;
+}
+
+#ifdef CONFIG_FSL_ESDHC
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct iomuxc_mux_ctl *muxctl;
+ struct iomuxc_pad_ctl *padctl;
+ u32 gpio_mux_mode = MX25_PIN_MUX_MODE(5);
+
+ /*
+ * Set up the Card Detect pin.
+ *
+ * SD1_GPIO_CD: gpio2_1 is ALT 5 mode of pin A15
+ *
+ */
+ muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
+ padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
+
+ writel(gpio_mux_mode, &muxctl->pad_a15);
+ writel(0x0, &padctl->pad_a15);
+
+ gpio_direction_input(CARD_DETECT);
+ return !gpio_get_value(CARD_DETECT);
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ struct iomuxc_mux_ctl *muxctl;
+ u32 sdhc1_mux_mode = MX25_PIN_MUX_MODE(0) | MX25_PIN_MUX_SION;
+
+ muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
+ writel(sdhc1_mux_mode, &muxctl->pad_sd1_cmd);
+ writel(sdhc1_mux_mode, &muxctl->pad_sd1_clk);
+ writel(sdhc1_mux_mode, &muxctl->pad_sd1_data0);
+ writel(sdhc1_mux_mode, &muxctl->pad_sd1_data1);
+ writel(sdhc1_mux_mode, &muxctl->pad_sd1_data2);
+ writel(sdhc1_mux_mode, &muxctl->pad_sd1_data3);
+
+ esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
+ return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
+}
+#endif
+
int checkboard(void)
{
puts("Board: MX25PDK\n");
. = ALIGN(4);
+ __image_copy_end = .;
+
.rel.dyn : {
__rel_dyn_start = .;
*(.rel*)
DECLARE_GLOBAL_DATA_PTR;
-#ifdef CONFIG_HW_WATCHDOG
-void hw_watchdog_reset(void)
-{
- mxc_hw_watchdog_reset();
-}
-#endif
-
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
pmic_reg_write(p, REG_POWER_CTL0, val | COINCHEN);
pmic_reg_write(p, REG_INT_STATUS1, RTCRSTI);
#ifdef CONFIG_HW_WATCHDOG
- mxc_hw_watchdog_enable();
+ hw_watchdog_init();
#endif
return 0;
}
orr r1, r1, #0x00000C00
orr r1, r1, #0x00000003
str r1, [r0, #CLKCTL_CGR1]
+
+ ldr r1, [r0, #CLKCTL_CGR2]
+ orr r1, r1, #0x00C00000
+ str r1, [r0, #CLKCTL_CGR2]
.endm
.macro setup_sdram
mxc_request_iomux(MX35_PIN_CSPI1_SCLK, MUX_CONFIG_SION);
}
+static void setup_iomux_usbotg(void)
+{
+ int in_pad, out_pad;
+
+ /* Set up pins for USBOTG. */
+ mxc_request_iomux(MX35_PIN_USBOTG_PWR,
+ MUX_CONFIG_SION | MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_USBOTG_OC,
+ MUX_CONFIG_SION | MUX_CONFIG_FUNC);
+
+ in_pad = PAD_CTL_DRV_3_3V | PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_PUE_PUD | PAD_CTL_100K_PD | PAD_CTL_ODE_CMOS |
+ PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW;
+ out_pad = PAD_CTL_DRV_3_3V | PAD_CTL_HYS_CMOS | PAD_CTL_PKE_NONE |
+ PAD_CTL_ODE_CMOS | PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW;
+
+ mxc_iomux_set_pad(MX35_PIN_USBOTG_PWR, out_pad);
+ mxc_iomux_set_pad(MX35_PIN_USBOTG_OC, in_pad);
+}
+
static void setup_iomux_fec(void)
{
int pad;
__raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
setup_iomux_i2c();
+ setup_iomux_usbotg();
setup_iomux_fec();
setup_iomux_spi();
mxc_request_iomux(MX35_PIN_COMPARE, MUX_CONFIG_GPIO);
mxc_iomux_set_input(MUX_IN_GPIO1_IN_5, INPUT_CTL_PATH0);
- gpio_direction_output(37, 1);
+ gpio_direction_output(IMX_GPIO_NR(2, 5), 1);
}
val = mc9sdz60_reg_read(MC9SDZ60_REG_GPIO_1) | 0x04;
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
- lcd_enable();
-
return 0;
}
.vmode = FB_VMODE_NONINTERLACED
};
+static struct fb_videomode const dvi = {
+ .name = "DVI panel",
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 768,
+ .pixclock = 15385,
+ .left_margin = 220,
+ .right_margin = 40,
+ .upper_margin = 21,
+ .lower_margin = 7,
+ .hsync_len = 60,
+ .vsync_len = 10,
+ .sync = 0,
+ .vmode = FB_VMODE_NONINTERLACED
+};
+
void setup_iomux_lcd(void)
{
/* DI2_PIN15 */
gpio_direction_output(MX51EVK_LCD_BACKLIGHT, 1);
}
-void lcd_enable(void)
+int board_video_skip(void)
{
- int ret = ipuv3_fb_init(&claa_wvga, 1, IPU_PIX_FMT_RGB565);
+ int ret;
+ char const *e = getenv("panel");
+
+ if (e) {
+ if (strcmp(e, "claa") == 0) {
+ ret = ipuv3_fb_init(&claa_wvga, 1, IPU_PIX_FMT_RGB565);
+ if (ret)
+ printf("claa cannot be configured: %d\n", ret);
+ return ret;
+ }
+ }
+
+ /*
+ * 'panel' env variable not found or has different value than 'claa'
+ * Defaulting to dvi output.
+ */
+ ret = ipuv3_fb_init(&dvi, 0, IPU_PIX_FMT_RGB24);
if (ret)
- printf("LCD cannot be configured: %d\n", ret);
+ printf("dvi cannot be configured: %d\n", ret);
+ return ret;
}
static int power_init(void)
{
unsigned int val;
- int ret = -1;
+ int ret;
struct pmic *p;
- int retval;
if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) {
- retval = pmic_dialog_init(I2C_PMIC);
- if (retval)
- return retval;
+ ret = pmic_dialog_init(I2C_PMIC);
+ if (ret)
+ return ret;
p = pmic_get("DIALOG_PMIC");
if (!p)
/* Set VDDA to 1.25V */
val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V;
ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val);
+ if (ret) {
+ printf("Writing to BUCKCORE_REG failed: %d\n", ret);
+ return ret;
+ }
- ret |= pmic_reg_read(p, DA9053_SUPPLY_REG, &val);
+ pmic_reg_read(p, DA9053_SUPPLY_REG, &val);
val |= DA9052_SUPPLY_VBCOREGO;
- ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, val);
+ ret = pmic_reg_write(p, DA9053_SUPPLY_REG, val);
+ if (ret) {
+ printf("Writing to SUPPLY_REG failed: %d\n", ret);
+ return ret;
+ }
/* Set Vcc peripheral to 1.30V */
- ret |= pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62);
- ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62);
+ ret = pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62);
+ if (ret) {
+ printf("Writing to BUCKPRO_REG failed: %d\n", ret);
+ return ret;
+ }
+
+ ret = pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62);
+ if (ret) {
+ printf("Writing to SUPPLY_REG failed: %d\n", ret);
+ return ret;
+ }
+
+ return ret;
}
if (!i2c_probe(CONFIG_SYS_FSL_PMIC_I2C_ADDR)) {
- retval = pmic_init(I2C_PMIC);
- if (retval)
- return retval;
+ ret = pmic_init(I2C_PMIC);
+ if (ret)
+ return ret;
- p = pmic_get("DIALOG_PMIC");
+ p = pmic_get("FSL_PMIC");
if (!p)
return -ENODEV;
pmic_reg_read(p, REG_SW_0, &val);
val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_250V_MC34708;
ret = pmic_reg_write(p, REG_SW_0, val);
+ if (ret) {
+ printf("Writing to REG_SW_0 failed: %d\n", ret);
+ return ret;
+ }
/* Set VCC as 1.30V on SW2 */
pmic_reg_read(p, REG_SW_1, &val);
val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_300V_MC34708;
- ret |= pmic_reg_write(p, REG_SW_1, val);
+ ret = pmic_reg_write(p, REG_SW_1, val);
+ if (ret) {
+ printf("Writing to REG_SW_1 failed: %d\n", ret);
+ return ret;
+ }
/* Set global reset timer to 4s */
pmic_reg_read(p, REG_POWER_CTL2, &val);
val = (val & ~TIMER_MASK_MC34708) | TIMER_4S_MC34708;
- ret |= pmic_reg_write(p, REG_POWER_CTL2, val);
+ ret = pmic_reg_write(p, REG_POWER_CTL2, val);
+ if (ret) {
+ printf("Writing to REG_POWER_CTL2 failed: %d\n", ret);
+ return ret;
+ }
/* Set VUSBSEL and VUSBEN for USB PHY supply*/
pmic_reg_read(p, REG_MODE_0, &val);
val |= (VUSBSEL_MC34708 | VUSBEN_MC34708);
- ret |= pmic_reg_write(p, REG_MODE_0, val);
+ ret = pmic_reg_write(p, REG_MODE_0, val);
+ if (ret) {
+ printf("Writing to REG_MODE_0 failed: %d\n", ret);
+ return ret;
+ }
/* Set SWBST to 5V in auto mode */
val = SWBST_AUTO;
- ret |= pmic_reg_write(p, SWBST_CTRL, val);
+ ret = pmic_reg_write(p, SWBST_CTRL, val);
+ if (ret) {
+ printf("Writing to SWBST_CTRL failed: %d\n", ret);
+ return ret;
+ }
+
+ return ret;
}
- return ret;
+ return -1;
}
static void clock_1GHz(void)
mxc_set_sata_internal_clock();
setup_iomux_i2c();
+
+ return 0;
+}
+
+int board_late_init(void)
+{
if (!power_init())
clock_1GHz();
print_cpuinfo();
- lcd_enable();
-
return 0;
}
.vmode = FB_VMODE_NONINTERLACED
};
+static struct fb_videomode const seiko_wvga = {
+ .name = "Seiko-43WVF1G",
+ .refresh = 60,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = 29851, /* picosecond (33.5 MHz) */
+ .left_margin = 89,
+ .right_margin = 164,
+ .upper_margin = 23,
+ .lower_margin = 10,
+ .hsync_len = 10,
+ .vsync_len = 10,
+ .sync = 0,
+};
+
void setup_iomux_lcd(void)
{
mxc_request_iomux(MX53_PIN_DI0_DISP_CLK, IOMUX_CONFIG_ALT0);
gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_GPIO_1), 1);
}
-void lcd_enable(void)
+int board_video_skip(void)
{
- int ret = ipuv3_fb_init(&claa_wvga, 0, IPU_PIX_FMT_RGB565);
+ int ret;
+ char const *e = getenv("panel");
+
+ if (e) {
+ if (strcmp(e, "seiko") == 0) {
+ ret = ipuv3_fb_init(&seiko_wvga, 0, IPU_PIX_FMT_RGB24);
+ if (ret)
+ printf("Seiko cannot be configured: %d\n", ret);
+ return ret;
+ }
+ }
+
+ /*
+ * 'panel' env variable not found or has different value than 'seiko'
+ * Defaulting to claa lcd.
+ */
+ ret = ipuv3_fb_init(&claa_wvga, 0, IPU_PIX_FMT_RGB565);
if (ret)
- printf("LCD cannot be configured: %d\n", ret);
+ printf("CLAA cannot be configured: %d\n", ret);
+ return ret;
}
gpio_set_value(IMX_GPIO_NR(1, 25), 1);
}
+iomux_v3_cfg_t const usdhc2_pads[] = {
+ MX6Q_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_NANDF_D4__USDHC2_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_NANDF_D5__USDHC2_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_NANDF_D6__USDHC2_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_NANDF_D7__USDHC2_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+};
+
iomux_v3_cfg_t const usdhc3_pads[] = {
MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6Q_PAD_NANDF_D0__GPIO_2_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
};
+iomux_v3_cfg_t const usdhc4_pads[] = {
+ MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
static void setup_iomux_uart(void)
{
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
}
#ifdef CONFIG_FSL_ESDHC
-struct fsl_esdhc_cfg usdhc_cfg[1] = {
+struct fsl_esdhc_cfg usdhc_cfg[3] = {
+ {USDHC2_BASE_ADDR},
{USDHC3_BASE_ADDR},
+ {USDHC4_BASE_ADDR},
};
+#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2)
+#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0)
+
int board_mmc_getcd(struct mmc *mmc)
{
- gpio_direction_input(IMX_GPIO_NR(2, 0));
- return !gpio_get_value(IMX_GPIO_NR(2, 0));
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+
+ switch (cfg->esdhc_base) {
+ case USDHC2_BASE_ADDR:
+ return !gpio_get_value(USDHC2_CD_GPIO);
+ case USDHC3_BASE_ADDR:
+ return !gpio_get_value(USDHC3_CD_GPIO);
+ default:
+ return 1; /* eMMC/uSDHC4 is always present */
+ }
}
int board_mmc_init(bd_t *bis)
{
- imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ int i;
+
+ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ switch (i) {
+ case 0:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+ gpio_direction_input(USDHC2_CD_GPIO);
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+ break;
+ case 1:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ gpio_direction_input(USDHC3_CD_GPIO);
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ break;
+ case 2:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+ usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+ break;
+ default:
+ printf("Warning: you configured more USDHC controllers"
+ "(%d) than supported by the board\n", i + 1);
+ return 0;
+ }
+
+ if (fsl_esdhc_initialize(bis, &usdhc_cfg[i]))
+ printf("Warning: failed to initialize mmc dev %d\n", i);
+ }
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
- return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+ return 0;
}
#endif
#include <asm/arch/pxa.h>
#include <asm/arch/pxa-regs.h>
#include <asm/io.h>
+#include <usb.h>
DECLARE_GLOBAL_DATA_PTR;
+int board_eth_init(bd_t *bis)
+{
+ usb_eth_initialize(bis);
+ return 0;
+}
+
int board_init(void)
{
/* We have RAM, disable cache */
/* adress of boot parameters */
gd->bd->bi_boot_params = 0xa0000100;
+ /* Let host see that device is disconnected */
+ udc_disconnect();
+ mdelay(500);
+
return 0;
}
int board_late_init(void)
{
#ifdef CONFIG_HW_WATCHDOG
- mxc_hw_watchdog_enable();
+ hw_watchdog_init();
#endif
return 0;
ICONNECT_OE_LOW, ICONNECT_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
- u32 kwmpp_config[] = {
+ static const u32 kwmpp_config[] = {
MPP0_NF_IO2,
MPP1_NF_IO3,
MPP2_NF_IO4,
* Description: If we use SPL then there is no x-loader nor config header
* so we have to setup the DDR timings ourself on both banks.
*/
-void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
- u32 *mr)
+void get_board_mem_timings(struct board_sdrc_timings *timings)
{
- *mr = MICRON_V_MR_165;
+ timings->mr = MICRON_V_MR_165;
#ifdef CONFIG_BOOT_NAND
- *mcfg = MICRON_V_MCFG_200(256 << 20);
- *ctrla = MICRON_V_ACTIMA_200;
- *ctrlb = MICRON_V_ACTIMB_200;
- *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+ timings->mcfg = MICRON_V_MCFG_200(256 << 20);
+ timings->ctrla = MICRON_V_ACTIMA_200;
+ timings->ctrlb = MICRON_V_ACTIMB_200;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
#else
if (get_cpu_family() == CPU_OMAP34XX) {
- *mcfg = NUMONYX_V_MCFG_165(256 << 20);
- *ctrla = NUMONYX_V_ACTIMA_165;
- *ctrlb = NUMONYX_V_ACTIMB_165;
- *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+ timings->mcfg = NUMONYX_V_MCFG_165(256 << 20);
+ timings->ctrla = NUMONYX_V_ACTIMA_165;
+ timings->ctrlb = NUMONYX_V_ACTIMB_165;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
} else {
- *mcfg = NUMONYX_V_MCFG_200(256 << 20);
- *ctrla = NUMONYX_V_ACTIMA_200;
- *ctrlb = NUMONYX_V_ACTIMB_200;
- *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+ timings->mcfg = NUMONYX_V_MCFG_200(256 << 20);
+ timings->ctrla = NUMONYX_V_ACTIMA_200;
+ timings->ctrlb = NUMONYX_V_ACTIMB_200;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
}
#endif
}
* Description: If we use SPL then there is no x-loader nor config header
* so we have to setup the DDR timings ourself on both banks.
*/
-void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
- u32 *mr)
+void get_board_mem_timings(struct board_sdrc_timings *timings)
{
- *mr = MICRON_V_MR_165;
+ timings->mr = MICRON_V_MR_165;
#ifdef CONFIG_BOOT_NAND
- *mcfg = MICRON_V_MCFG_200(256 << 20);
- *ctrla = MICRON_V_ACTIMA_200;
- *ctrlb = MICRON_V_ACTIMB_200;
- *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+ timings->mcfg = MICRON_V_MCFG_200(256 << 20);
+ timings->ctrla = MICRON_V_ACTIMA_200;
+ timings->ctrlb = MICRON_V_ACTIMB_200;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
#else
if (get_cpu_family() == CPU_OMAP34XX) {
- *mcfg = NUMONYX_V_MCFG_165(256 << 20);
- *ctrla = NUMONYX_V_ACTIMA_165;
- *ctrlb = NUMONYX_V_ACTIMB_165;
- *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+ timings->mcfg = NUMONYX_V_MCFG_165(256 << 20);
+ timings->ctrla = NUMONYX_V_ACTIMA_165;
+ timings->ctrlb = NUMONYX_V_ACTIMB_165;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
} else {
- *mcfg = NUMONYX_V_MCFG_200(256 << 20);
- *ctrla = NUMONYX_V_ACTIMA_200;
- *ctrlb = NUMONYX_V_ACTIMB_200;
- *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+ timings->mcfg = NUMONYX_V_MCFG_200(256 << 20);
+ timings->ctrla = NUMONYX_V_ACTIMA_200;
+ timings->ctrlb = NUMONYX_V_ACTIMB_200;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
}
#endif
}
TK71_OE_LOW, TK71_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
- u32 kwmpp_config[] = {
+ static const u32 kwmpp_config[] = {
MPP0_NF_IO2,
MPP1_NF_IO3,
MPP2_NF_IO4,
{
#if defined(CONFIG_HARD_I2C) && !defined(MACH_TYPE_KM_KIRKWOOD)
- immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ;
+ immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c;
/*
#define MASK_RBI_DEFECT_16 0x01
/* Multi-Purpose Pins Functionality configuration */
-u32 kwmpp_config[] = {
+static const u32 kwmpp_config[] = {
MPP0_NF_IO2,
MPP1_NF_IO3,
MPP2_NF_IO4,
int misc_init_r(void)
{
- char *str;
- int mach_type;
-
- str = getenv("mach_type");
- if (str != NULL) {
- mach_type = simple_strtoul(str, NULL, 10);
- printf("Overwriting MACH_TYPE with %d!!!\n", mach_type);
- gd->bd->bi_arch_number = mach_type;
- }
#if defined(CONFIG_KM_MGCOGE3UN)
char *wait_for_ne;
wait_for_ne = getenv("waitforne");
int board_init(void)
{
- /*
- * arch number of board
- */
- gd->bd->bi_arch_number = MACH_TYPE_KM_KIRKWOOD;
-
/* address of boot parameters */
gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register
DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register
DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register
-DATA 0xFFD20154 0x00000200 # CPU RAM Management Control3 Register
-DATA 0xFFD2014C 0x00001C00 # CPU RAM Management Control1 Register
-DATA 0xFFD20148 0x00000001 # CPU RAM Management Control0 Register
+
+# NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched!
+# If not it could cause KW Exceptions during boot in Fast Corners/High Voltage
#Dram initalization
DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register
DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register
DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register
DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register
-DATA 0xFFD20154 0x00000200 # CPU RAM Management Control3 Register
-DATA 0xFFD2014C 0x00001C00 # CPU RAM Management Control1 Register
-DATA 0xFFD20148 0x00000001 # CPU RAM Management Control0 Register
+
+# NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched!
+# If not it could cause KW Exceptions during boot in Fast Corners/High Voltage
#Dram initalization
DATA 0xFFD01400 0x43000400 # SDRAM Configuration Register
# bit 19-18: 1, ECC RAM WTC RAM0
# bit 31-20: ???,Reserve
-DATA 0xFFD20154 0x00000200 # CPU RAM Management Control3 Register
-# bit 23-0: 0x000200, Addr Config tuning
-# bit 31-24: 0, Reserved
-
-# ??? Missing register # CPU RAM Management Control2 Register
-
-DATA 0xFFD2014C 0x00001C00 # CPU RAM Management Control1 Register
-# bit 15-0: 0x1C00, Opmux Tuning
-# bit 31-16: 0, Pc Dp Tuning
-
-DATA 0xFFD20148 0x00000001 # CPU RAM Management Control0 Register
-# bit 1-0: 1, addr clk tune
-# bit 3-2: 0, reserved
-# bit 5-4: 0, dtcmp clk tune
-# bit 7-6: 0, reserved
-# bit 9-8: 0, macdrv clk tune
-# bit 11-10: 0, opmuxgm2 clk tune
-# bit 15-14: 0, rf clk tune
-# bit 17-16: 0, rfbypass clk tune
-# bit 19-18: 0, pc dp clk tune
-# bit 23-20: 0, icache clk tune
-# bit 27:24: 0, dcache clk tune
-# bit 31:28: 0, regfile tunin
+# NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched!
+# If not it could cause KW Exceptions during boot in Fast Corners/High Voltage
# SDRAM initalization
DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register
# bit 19-18: 1, ECC RAM WTC RAM0
# bit 31-20: ?,Reserved
-DATA 0xFFD20154 0x00000200 # CPU RAM Management Control3 Register
-# bit 23-0: 0x000200, Addr Config tuning
-# bit 31-24: 0, Reserved
-
-# ??? Missing register # CPU RAM Management Control2 Register
-
-DATA 0xFFD2014C 0x00001C00 # CPU RAM Management Control1 Register
-# bit 15-0: 0x1C00, Opmux Tuning
-# bit 31-16: 0, Pc Dp Tuning
-
-DATA 0xFFD20148 0x00000001 # CPU RAM Management Control0 Register
-# bit 1-0: 1, addr clk tune
-# bit 3-2: 0, reserved
-# bit 5-4: 0, dtcmp clk tune
-# bit 7-6: 0, reserved
-# bit 9-8: 0, macdrv clk tune
-# bit 11-10: 0, opmuxgm2 clk tune
-# bit 15-14: 0, rf clk tune
-# bit 17-16: 0, rfbypass clk tune
-# bit 19-18: 0, pc dp clk tune
-# bit 23-20: 0, icache clk tune
-# bit 27:24: 0, dcache clk tune
-# bit 31:28: 0, regfile tunin
+# NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched!
+# If not it could cause KW Exceptions during boot in Fast Corners/High Voltage
# SDRAM initalization
DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register
#include <linux/compiler.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
+#include <asm/arch/display.h>
#include <asm/arch/emc.h>
#include <asm/arch/funcmux.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/pmu.h>
+#include <asm/arch/pwm.h>
#include <asm/arch/tegra.h>
#include <asm/arch/usb.h>
#include <asm/arch-tegra/board.h>
#ifdef CONFIG_TEGRA_SPI
pin_mux_spi();
spi_init();
+#endif
+#ifdef CONFIG_PWM_TEGRA
+ if (pwm_init(gd->fdt_blob))
+ debug("%s: Failed to init pwm\n", __func__);
+#endif
+#ifdef CONFIG_LCD
+ tegra_lcd_check_next_stage(gd->fdt_blob, 0);
#endif
/* boot param addr */
gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
pin_mux_usb();
board_usb_init(gd->fdt_blob);
#endif
+#ifdef CONFIG_LCD
+ tegra_lcd_check_next_stage(gd->fdt_blob, 0);
+#endif
#ifdef CONFIG_TEGRA_NAND
pin_mux_nand();
/* Initialize periph GPIOs */
gpio_early_init();
gpio_early_init_uart();
+#ifdef CONFIG_LCD
+ tegra_lcd_early_init(gd->fdt_blob);
+#endif
return 0;
}
#endif /* EARLY_INIT */
+
+int board_late_init(void)
+{
+#ifdef CONFIG_LCD
+ /* Make sure we finish initing the LCD */
+ tegra_lcd_check_next_stage(gd->fdt_blob, 1);
+#endif
+ return 0;
+}
compatible = "hynix,hy27uf4g2b", "nand-flash";
};
};
+
+ host1x {
+ status = "okay";
+ dc@54200000 {
+ status = "okay";
+ rgb {
+ status = "okay";
+ nvidia,panel = <&lcd_panel>;
+ };
+ };
+ };
+
+ lcd_panel: panel {
+ /* Seaboard has 1366x768 */
+ clock = <70600000>;
+ xres = <1366>;
+ yres = <768>;
+ left-margin = <58>;
+ right-margin = <58>;
+ hsync-len = <58>;
+ lower-margin = <4>;
+ upper-margin = <4>;
+ vsync-len = <4>;
+ hsync-active-high;
+ nvidia,bits-per-pixel = <16>;
+ nvidia,pwm = <&pwm 2 0>;
+ nvidia,backlight-enable-gpios = <&gpio 28 0>; /* PD4 */
+ nvidia,lvds-shutdown-gpios = <&gpio 10 0>; /* PB2 */
+ nvidia,backlight-vdd-gpios = <&gpio 176 0>; /* PW0 */
+ nvidia,panel-vdd-gpios = <&gpio 22 0>; /* PC6 */
+ nvidia,panel-timings = <400 4 203 17 15>;
+ };
+
};
pin_mux_mmc();
debug("board_mmc_init: init SD slot J26\n");
- /* init dev 0, SD slot J26, with 4-bit bus */
- /* The board has an 8-bit bus, but 8-bit doesn't work yet */
- tegra_mmc_init(0, 4, GPIO_PI6, GPIO_PH2);
+ /* init dev 0, SD slot J26, with 8-bit bus */
+ tegra_mmc_init(0, 8, GPIO_PI6, GPIO_PH2);
debug("board_mmc_init: init SD slot J5\n");
/* init dev 2, SD slot J5, with 4-bit bus */
pin_mux_mmc();
debug("board_mmc_init: init eMMC\n");
- /* init dev 0, eMMC chip, with 4-bit bus */
- /* The board has an 8-bit bus, but 8-bit doesn't work yet */
- tegra_mmc_init(0, 4, -1, -1);
+ /* init dev 0, eMMC chip, with 8-bit bus */
+ tegra_mmc_init(0, 8, -1, -1);
debug("board_mmc_init: init SD slot\n");
/* init dev 1, SD slot, with 4-bit bus */
* Description: If we use SPL then there is no x-loader nor config header
* so we have to setup the DDR timings ourself on both banks.
*/
-void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
- u32 *mr)
+void get_board_mem_timings(struct board_sdrc_timings *timings)
{
- *mr = MICRON_V_MR_165;
+ timings->mr = MICRON_V_MR_165;
switch (get_board_revision()) {
case REVISION_0: /* Micron 1286MB/256MB, 1/2 banks of 128MB */
- *mcfg = MICRON_V_MCFG_165(128 << 20);
- *ctrla = MICRON_V_ACTIMA_165;
- *ctrlb = MICRON_V_ACTIMB_165;
- *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+ timings->mcfg = MICRON_V_MCFG_165(128 << 20);
+ timings->ctrla = MICRON_V_ACTIMA_165;
+ timings->ctrlb = MICRON_V_ACTIMB_165;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
break;
case REVISION_1: /* Micron 256MB/512MB, 1/2 banks of 256MB */
- *mcfg = MICRON_V_MCFG_165(256 << 20);
- *ctrla = MICRON_V_ACTIMA_165;
- *ctrlb = MICRON_V_ACTIMB_165;
- *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+ timings->mcfg = MICRON_V_MCFG_165(256 << 20);
+ timings->ctrla = MICRON_V_ACTIMA_165;
+ timings->ctrlb = MICRON_V_ACTIMB_165;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
break;
case REVISION_2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */
- *mcfg = HYNIX_V_MCFG_165(256 << 20);
- *ctrla = HYNIX_V_ACTIMA_165;
- *ctrlb = HYNIX_V_ACTIMB_165;
- *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+ timings->mcfg = HYNIX_V_MCFG_165(256 << 20);
+ timings->ctrla = HYNIX_V_ACTIMA_165;
+ timings->ctrlb = HYNIX_V_ACTIMB_165;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
break;
default:
- *mcfg = MICRON_V_MCFG_165(128 << 20);
- *ctrla = MICRON_V_ACTIMA_165;
- *ctrlb = MICRON_V_ACTIMB_165;
- *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+ timings->mcfg = MICRON_V_MCFG_165(128 << 20);
+ timings->ctrla = MICRON_V_ACTIMA_165;
+ timings->ctrlb = MICRON_V_ACTIMB_165;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
}
}
#endif
/* Set SATA activity LEDs to default off */
writel(MVSATAHC_LED_POLARITY_CTRL, MVSATAHC_LED_CONF_REG);
/* Multi-Purpose Pins Functionality configuration */
- u32 kwmpp_config[] = {
+ static const u32 kwmpp_config[] = {
MPP0_NF_IO2,
MPP1_NF_IO3,
MPP2_NF_IO4,
--- /dev/null
+#
+# Copyright (C) 2012 Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := sh7752evb.o spi-boot.o
+SOBJS := lowlevel_init.o
+
+$(LIB): $(obj).depend $(COBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(COBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/processor.h>
+#include <asm/macro.h>
+
+.macro or32, addr, data
+ mov.l \addr, r1
+ mov.l \data, r0
+ mov.l @r1, r2
+ or r2, r0
+ mov.l r0, @r1
+.endm
+
+.macro wait_DBCMD
+ mov.l DBWAIT_A, r0
+ mov.l @r0, r1
+.endm
+
+ .global lowlevel_init
+ .section .spiboot1.text
+ .align 2
+
+lowlevel_init:
+ /*------- GPIO -------*/
+ write16 PDCR_A, PDCR_D ! SPI0
+ write16 PGCR_A, PGCR_D ! SPI0, GETHER MDIO gate(PTG1)
+ write16 PJCR_A, PJCR_D ! SCIF4
+ write16 PTCR_A, PTCR_D ! STATUS
+ write16 PSEL1_A, PSEL1_D ! SPI0
+ write16 PSEL2_A, PSEL2_D ! SPI0
+ write16 PSEL5_A, PSEL5_D ! STATUS
+
+ bra exit_gpio
+ nop
+
+ .align 2
+
+/*------- GPIO -------*/
+PDCR_A: .long 0xffec0006
+PGCR_A: .long 0xffec000c
+PJCR_A: .long 0xffec0012
+PTCR_A: .long 0xffec0026
+PSEL1_A: .long 0xffec0072
+PSEL2_A: .long 0xffec0074
+PSEL5_A: .long 0xffec007a
+
+PDCR_D: .long 0x0000
+PGCR_D: .long 0x0004
+PJCR_D: .long 0x0000
+PTCR_D: .long 0x0000
+PSEL1_D: .long 0x0000
+PSEL2_D: .long 0x3000
+PSEL5_D: .long 0x0ffc
+
+ .align 2
+
+exit_gpio:
+ mov #0, r14
+ mova 2f, r0
+ mov.l PC_MASK, r1
+ tst r0, r1
+ bf 2f
+
+ bra exit_pmb
+ nop
+
+ .align 2
+
+/* If CPU runs on SDRAM (PC=0x5???????) or not. */
+PC_MASK: .long 0x20000000
+
+2:
+ mov #1, r14
+
+ mov.l EXPEVT_A, r0
+ mov.l @r0, r0
+ mov.l EXPEVT_POWER_ON_RESET, r1
+ cmp/eq r0, r1
+ bt 1f
+
+ /*
+ * If EXPEVT value is manual reset or tlb multipul-hit,
+ * initialization of DDR3IF is not necessary.
+ */
+ bra exit_ddr
+ nop
+
+1:
+ /*------- Reset -------*/
+ write32 MRSTCR0_A, MRSTCR0_D
+ write32 MRSTCR1_A, MRSTCR1_D
+
+ /* For Core Reset */
+ mov.l DBACEN_A, r0
+ mov.l @r0, r0
+ cmp/eq #0, r0
+ bt 3f
+
+ /*
+ * If DBACEN == 1(DBSC was already enabled), we have to avoid the
+ * initialization of DDR3-SDRAM.
+ */
+ bra exit_ddr
+ nop
+
+3:
+ /*------- DDR3IF -------*/
+ /* oscillation stabilization time */
+ wait_timer WAIT_OSC_TIME
+
+ /* step 3 */
+ write32 DBCMD_A, DBCMD_RSTL_VAL
+ wait_timer WAIT_30US
+
+ /* step 4 */
+ write32 DBCMD_A, DBCMD_PDEN_VAL
+
+ /* step 5 */
+ write32 DBKIND_A, DBKIND_D
+
+ /* step 6 */
+ write32 DBCONF_A, DBCONF_D
+ write32 DBTR0_A, DBTR0_D
+ write32 DBTR1_A, DBTR1_D
+ write32 DBTR2_A, DBTR2_D
+ write32 DBTR3_A, DBTR3_D
+ write32 DBTR4_A, DBTR4_D
+ write32 DBTR5_A, DBTR5_D
+ write32 DBTR6_A, DBTR6_D
+ write32 DBTR7_A, DBTR7_D
+ write32 DBTR8_A, DBTR8_D
+ write32 DBTR9_A, DBTR9_D
+ write32 DBTR10_A, DBTR10_D
+ write32 DBTR11_A, DBTR11_D
+ write32 DBTR12_A, DBTR12_D
+ write32 DBTR13_A, DBTR13_D
+ write32 DBTR14_A, DBTR14_D
+ write32 DBTR15_A, DBTR15_D
+ write32 DBTR16_A, DBTR16_D
+ write32 DBTR17_A, DBTR17_D
+ write32 DBTR18_A, DBTR18_D
+ write32 DBTR19_A, DBTR19_D
+ write32 DBRNK0_A, DBRNK0_D
+
+ /* step 7 */
+ write32 DBPDCNT3_A, DBPDCNT3_D
+
+ /* step 8 */
+ write32 DBPDCNT1_A, DBPDCNT1_D
+ write32 DBPDCNT2_A, DBPDCNT2_D
+ write32 DBPDLCK_A, DBPDLCK_D
+ write32 DBPDRGA_A, DBPDRGA_D
+ write32 DBPDRGD_A, DBPDRGD_D
+
+ /* step 9 */
+ wait_timer WAIT_30US
+
+ /* step 10 */
+ write32 DBPDCNT0_A, DBPDCNT0_D
+
+ /* step 11 */
+ wait_timer WAIT_30US
+ wait_timer WAIT_30US
+
+ /* step 12 */
+ write32 DBCMD_A, DBCMD_WAIT_VAL
+ wait_DBCMD
+
+ /* step 13 */
+ write32 DBCMD_A, DBCMD_RSTH_VAL
+ wait_DBCMD
+
+ /* step 14 */
+ write32 DBCMD_A, DBCMD_WAIT_VAL
+ write32 DBCMD_A, DBCMD_WAIT_VAL
+ write32 DBCMD_A, DBCMD_WAIT_VAL
+ write32 DBCMD_A, DBCMD_WAIT_VAL
+
+ /* step 15 */
+ write32 DBCMD_A, DBCMD_PDXT_VAL
+
+ /* step 16 */
+ write32 DBCMD_A, DBCMD_MRS2_VAL
+
+ /* step 17 */
+ write32 DBCMD_A, DBCMD_MRS3_VAL
+
+ /* step 18 */
+ write32 DBCMD_A, DBCMD_MRS1_VAL
+
+ /* step 19 */
+ write32 DBCMD_A, DBCMD_MRS0_VAL
+
+ /* step 20 */
+ write32 DBCMD_A, DBCMD_ZQCL_VAL
+
+ write32 DBCMD_A, DBCMD_REF_VAL
+ write32 DBCMD_A, DBCMD_REF_VAL
+ wait_DBCMD
+
+ /* step 21 */
+ write32 DBADJ0_A, DBADJ0_D
+ write32 DBADJ1_A, DBADJ1_D
+ write32 DBADJ2_A, DBADJ2_D
+
+ /* step 22 */
+ write32 DBRFCNF0_A, DBRFCNF0_D
+ write32 DBRFCNF1_A, DBRFCNF1_D
+ write32 DBRFCNF2_A, DBRFCNF2_D
+
+ /* step 23 */
+ write32 DBCALCNF_A, DBCALCNF_D
+
+ /* step 24 */
+ write32 DBRFEN_A, DBRFEN_D
+ write32 DBCMD_A, DBCMD_SRXT_VAL
+
+ /* step 25 */
+ write32 DBACEN_A, DBACEN_D
+
+ /* step 26 */
+ wait_DBCMD
+
+ bra exit_ddr
+ nop
+
+ .align 2
+
+EXPEVT_A: .long 0xff000024
+EXPEVT_POWER_ON_RESET: .long 0x00000000
+
+/*------- Reset -------*/
+MRSTCR0_A: .long 0xffd50030
+MRSTCR0_D: .long 0xfe1ffe7f
+MRSTCR1_A: .long 0xffd50034
+MRSTCR1_D: .long 0xfff3ffff
+
+/*------- DDR3IF -------*/
+DBCMD_A: .long 0xfe800018
+DBKIND_A: .long 0xfe800020
+DBCONF_A: .long 0xfe800024
+DBTR0_A: .long 0xfe800040
+DBTR1_A: .long 0xfe800044
+DBTR2_A: .long 0xfe800048
+DBTR3_A: .long 0xfe800050
+DBTR4_A: .long 0xfe800054
+DBTR5_A: .long 0xfe800058
+DBTR6_A: .long 0xfe80005c
+DBTR7_A: .long 0xfe800060
+DBTR8_A: .long 0xfe800064
+DBTR9_A: .long 0xfe800068
+DBTR10_A: .long 0xfe80006c
+DBTR11_A: .long 0xfe800070
+DBTR12_A: .long 0xfe800074
+DBTR13_A: .long 0xfe800078
+DBTR14_A: .long 0xfe80007c
+DBTR15_A: .long 0xfe800080
+DBTR16_A: .long 0xfe800084
+DBTR17_A: .long 0xfe800088
+DBTR18_A: .long 0xfe80008c
+DBTR19_A: .long 0xfe800090
+DBRNK0_A: .long 0xfe800100
+DBPDCNT0_A: .long 0xfe800200
+DBPDCNT1_A: .long 0xfe800204
+DBPDCNT2_A: .long 0xfe800208
+DBPDCNT3_A: .long 0xfe80020c
+DBPDLCK_A: .long 0xfe800280
+DBPDRGA_A: .long 0xfe800290
+DBPDRGD_A: .long 0xfe8002a0
+DBADJ0_A: .long 0xfe8000c0
+DBADJ1_A: .long 0xfe8000c4
+DBADJ2_A: .long 0xfe8000c8
+DBRFCNF0_A: .long 0xfe8000e0
+DBRFCNF1_A: .long 0xfe8000e4
+DBRFCNF2_A: .long 0xfe8000e8
+DBCALCNF_A: .long 0xfe8000f4
+DBRFEN_A: .long 0xfe800014
+DBACEN_A: .long 0xfe800010
+DBWAIT_A: .long 0xfe80001c
+
+WAIT_OSC_TIME: .long 6000
+WAIT_30US: .long 13333
+
+DBCMD_RSTL_VAL: .long 0x20000000
+DBCMD_PDEN_VAL: .long 0x1000d73c
+DBCMD_WAIT_VAL: .long 0x0000d73c
+DBCMD_RSTH_VAL: .long 0x2100d73c
+DBCMD_PDXT_VAL: .long 0x110000c8
+DBCMD_MRS0_VAL: .long 0x28000930
+DBCMD_MRS1_VAL: .long 0x29000004
+DBCMD_MRS2_VAL: .long 0x2a000008
+DBCMD_MRS3_VAL: .long 0x2b000000
+DBCMD_ZQCL_VAL: .long 0x03000200
+DBCMD_REF_VAL: .long 0x0c000000
+DBCMD_SRXT_VAL: .long 0x19000000
+DBKIND_D: .long 0x00000007
+DBCONF_D: .long 0x0f030a01
+DBTR0_D: .long 0x00000007
+DBTR1_D: .long 0x00000006
+DBTR2_D: .long 0x00000000
+DBTR3_D: .long 0x00000007
+DBTR4_D: .long 0x00070007
+DBTR5_D: .long 0x0000001b
+DBTR6_D: .long 0x00000014
+DBTR7_D: .long 0x00000005
+DBTR8_D: .long 0x00000015
+DBTR9_D: .long 0x00000006
+DBTR10_D: .long 0x00000008
+DBTR11_D: .long 0x00000007
+DBTR12_D: .long 0x0000000e
+DBTR13_D: .long 0x00000056
+DBTR14_D: .long 0x00000006
+DBTR15_D: .long 0x00000004
+DBTR16_D: .long 0x00150002
+DBTR17_D: .long 0x000c0017
+DBTR18_D: .long 0x00000200
+DBTR19_D: .long 0x00000040
+DBRNK0_D: .long 0x00000001
+DBPDCNT0_D: .long 0x00000001
+DBPDCNT1_D: .long 0x00000001
+DBPDCNT2_D: .long 0x00000000
+DBPDCNT3_D: .long 0x00004010
+DBPDLCK_D: .long 0x0000a55a
+DBPDRGA_D: .long 0x00000028
+DBPDRGD_D: .long 0x00017100
+
+DBADJ0_D: .long 0x00000000
+DBADJ1_D: .long 0x00000000
+DBADJ2_D: .long 0x18061806
+DBRFCNF0_D: .long 0x000001ff
+DBRFCNF1_D: .long 0x08001000
+DBRFCNF2_D: .long 0x00000000
+DBCALCNF_D: .long 0x0000ffff
+DBRFEN_D: .long 0x00000001
+DBACEN_D: .long 0x00000001
+
+ .align 2
+exit_ddr:
+#if defined(CONFIG_SH_32BIT)
+ /*------- set PMB -------*/
+ write32 PASCR_A, PASCR_29BIT_D
+ write32 MMUCR_A, MMUCR_D
+
+ /*****************************************************************
+ * ent virt phys v sz c wt
+ * 0 0xa0000000 0x00000000 1 128M 0 1
+ * 1 0xa8000000 0x48000000 1 128M 0 1
+ * 5 0x88000000 0x48000000 1 128M 1 1
+ */
+ write32 PMB_ADDR_SPIBOOT_A, PMB_ADDR_SPIBOOT_D
+ write32 PMB_DATA_SPIBOOT_A, PMB_DATA_SPIBOOT_D
+ write32 PMB_ADDR_DDR_C1_A, PMB_ADDR_DDR_C1_D
+ write32 PMB_DATA_DDR_C1_A, PMB_DATA_DDR_C1_D
+ write32 PMB_ADDR_DDR_N1_A, PMB_ADDR_DDR_N1_D
+ write32 PMB_DATA_DDR_N1_A, PMB_DATA_DDR_N1_D
+
+ write32 PMB_ADDR_ENTRY2, PMB_ADDR_NOT_USE_D
+ write32 PMB_ADDR_ENTRY3, PMB_ADDR_NOT_USE_D
+ write32 PMB_ADDR_ENTRY4, PMB_ADDR_NOT_USE_D
+ write32 PMB_ADDR_ENTRY6, PMB_ADDR_NOT_USE_D
+ write32 PMB_ADDR_ENTRY7, PMB_ADDR_NOT_USE_D
+ write32 PMB_ADDR_ENTRY8, PMB_ADDR_NOT_USE_D
+ write32 PMB_ADDR_ENTRY9, PMB_ADDR_NOT_USE_D
+ write32 PMB_ADDR_ENTRY10, PMB_ADDR_NOT_USE_D
+ write32 PMB_ADDR_ENTRY11, PMB_ADDR_NOT_USE_D
+ write32 PMB_ADDR_ENTRY12, PMB_ADDR_NOT_USE_D
+ write32 PMB_ADDR_ENTRY13, PMB_ADDR_NOT_USE_D
+ write32 PMB_ADDR_ENTRY14, PMB_ADDR_NOT_USE_D
+ write32 PMB_ADDR_ENTRY15, PMB_ADDR_NOT_USE_D
+
+ write32 PASCR_A, PASCR_INIT
+ mov.l DUMMY_ADDR, r0
+ icbi @r0
+#endif /* if defined(CONFIG_SH_32BIT) */
+
+exit_pmb:
+ /* CPU is running on ILRAM? */
+ mov r14, r0
+ tst #1, r0
+ bt 1f
+
+ mov.l _stack_ilram, r15
+ mov.l _spiboot_main, r0
+100: bsrf r0
+ nop
+
+ .align 2
+_spiboot_main: .long (spiboot_main - (100b + 4))
+_stack_ilram: .long 0xe5204000
+
+1:
+ write32 CCR_A, CCR_D
+
+ rts
+ nop
+
+ .align 2
+
+#if defined(CONFIG_SH_32BIT)
+/*------- set PMB -------*/
+PMB_ADDR_SPIBOOT_A: .long PMB_ADDR_BASE(0)
+PMB_ADDR_DDR_N1_A: .long PMB_ADDR_BASE(1)
+PMB_ADDR_DDR_C1_A: .long PMB_ADDR_BASE(5)
+PMB_ADDR_ENTRY2: .long PMB_ADDR_BASE(2)
+PMB_ADDR_ENTRY3: .long PMB_ADDR_BASE(3)
+PMB_ADDR_ENTRY4: .long PMB_ADDR_BASE(4)
+PMB_ADDR_ENTRY6: .long PMB_ADDR_BASE(6)
+PMB_ADDR_ENTRY7: .long PMB_ADDR_BASE(7)
+PMB_ADDR_ENTRY8: .long PMB_ADDR_BASE(8)
+PMB_ADDR_ENTRY9: .long PMB_ADDR_BASE(9)
+PMB_ADDR_ENTRY10: .long PMB_ADDR_BASE(10)
+PMB_ADDR_ENTRY11: .long PMB_ADDR_BASE(11)
+PMB_ADDR_ENTRY12: .long PMB_ADDR_BASE(12)
+PMB_ADDR_ENTRY13: .long PMB_ADDR_BASE(13)
+PMB_ADDR_ENTRY14: .long PMB_ADDR_BASE(14)
+PMB_ADDR_ENTRY15: .long PMB_ADDR_BASE(15)
+
+PMB_ADDR_SPIBOOT_D: .long mk_pmb_addr_val(0xa0)
+PMB_ADDR_DDR_C1_D: .long mk_pmb_addr_val(0x88)
+PMB_ADDR_DDR_N1_D: .long mk_pmb_addr_val(0xa8)
+PMB_ADDR_NOT_USE_D: .long 0x00000000
+
+PMB_DATA_SPIBOOT_A: .long PMB_DATA_BASE(0)
+PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(1)
+PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(5)
+
+/* ppn ub v s1 s0 c wt */
+PMB_DATA_SPIBOOT_D: .long mk_pmb_data_val(0x00, 0, 1, 1, 0, 0, 1)
+PMB_DATA_DDR_C1_D: .long mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1)
+PMB_DATA_DDR_N1_D: .long mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1)
+
+PASCR_A: .long 0xff000070
+DUMMY_ADDR: .long 0xa0000000
+PASCR_29BIT_D: .long 0x00000000
+PASCR_INIT: .long 0x80000080
+MMUCR_A: .long 0xff000010
+MMUCR_D: .long 0x00000004 /* clear ITLB */
+#endif /* CONFIG_SH_32BIT */
+
+CCR_A: .long CCR
+CCR_D: .long CCR_CACHE_INIT
--- /dev/null
+/*
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/mmc.h>
+#include <spi_flash.h>
+
+int checkboard(void)
+{
+ puts("BOARD: SH7752 evaluation board (R0P7752C00000RZ)\n");
+
+ return 0;
+}
+
+static void init_gpio(void)
+{
+ struct gpio_regs *gpio = GPIO_BASE;
+ struct sermux_regs *sermux = SERMUX_BASE;
+
+ /* GPIO */
+ writew(0x0000, &gpio->pacr); /* GETHER */
+ writew(0x0001, &gpio->pbcr); /* INTC */
+ writew(0x0000, &gpio->pccr); /* PWMU, INTC */
+ writew(0xeaff, &gpio->pecr); /* GPIO */
+ writew(0x0000, &gpio->pfcr); /* WDT */
+ writew(0x0000, &gpio->phcr); /* SPI1 */
+ writew(0x0000, &gpio->picr); /* SDHI */
+ writew(0x0003, &gpio->pkcr); /* SerMux */
+ writew(0x0000, &gpio->plcr); /* SerMux */
+ writew(0x0000, &gpio->pmcr); /* RIIC */
+ writew(0x0000, &gpio->pncr); /* USB, SGPIO */
+ writew(0x0000, &gpio->pocr); /* SGPIO */
+ writew(0xd555, &gpio->pqcr); /* GPIO */
+ writew(0x0000, &gpio->prcr); /* RIIC */
+ writew(0x0000, &gpio->pscr); /* RIIC */
+ writeb(0x00, &gpio->pudr);
+ writew(0x5555, &gpio->pucr); /* Debug LED */
+ writew(0x0000, &gpio->pvcr); /* RSPI */
+ writew(0x0000, &gpio->pwcr); /* EVC */
+ writew(0x0000, &gpio->pxcr); /* LBSC */
+ writew(0x0000, &gpio->pycr); /* LBSC */
+ writew(0x0000, &gpio->pzcr); /* eMMC */
+ writew(0xfe00, &gpio->psel0);
+ writew(0xff00, &gpio->psel3);
+ writew(0x771f, &gpio->psel4);
+ writew(0x00ff, &gpio->psel6);
+ writew(0xfc00, &gpio->psel7);
+
+ writeb(0x10, &sermux->smr0); /* SMR0: SerMux mode 0 */
+}
+
+static void init_usb_phy(void)
+{
+ struct usb_common_regs *common0 = USB0_COMMON_BASE;
+ struct usb_common_regs *common1 = USB1_COMMON_BASE;
+ struct usb0_phy_regs *phy = USB0_PHY_BASE;
+ struct usb1_port_regs *port = USB1_PORT_BASE;
+ struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE;
+
+ writew(0x0100, &phy->reset); /* set reset */
+ /* port0 = USB0, port1 = USB1 */
+ writew(0x0002, &phy->portsel);
+ writel(0x0001, &port->port1sel); /* port1 = Host */
+ writew(0x0111, &phy->reset); /* clear reset */
+
+ writew(0x4000, &common0->suspmode);
+ writew(0x4000, &common1->suspmode);
+
+#if defined(__LITTLE_ENDIAN)
+ writel(0x00000000, &align->ehcidatac);
+ writel(0x00000000, &align->ohcidatac);
+#endif
+}
+
+static void init_gether_mdio(void)
+{
+ struct gpio_regs *gpio = GPIO_BASE;
+
+ writew(readw(&gpio->pgcr) | 0x0004, &gpio->pgcr);
+ writeb(readb(&gpio->pgdr) | 0x02, &gpio->pgdr); /* Use ET0-MDIO */
+}
+
+static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string)
+{
+ struct ether_mac_regs *ether;
+ unsigned char mac[6];
+ unsigned long val;
+
+ eth_parse_enetaddr(mac_string, mac);
+
+ if (!channel)
+ ether = GETHER0_MAC_BASE;
+ else
+ ether = GETHER1_MAC_BASE;
+
+ val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
+ writel(val, ðer->mahr);
+ val = (mac[4] << 8) | mac[5];
+ writel(val, ðer->malr);
+}
+
+/*****************************************************************
+ * This PMB must be set on this timing. The lowlevel_init is run on
+ * Area 0(phys 0x00000000), so we have to map it.
+ *
+ * The new PMB table is following:
+ * ent virt phys v sz c wt
+ * 0 0xa0000000 0x40000000 1 128M 0 1
+ * 1 0xa8000000 0x48000000 1 128M 0 1
+ * 2 0xb0000000 0x50000000 1 128M 0 1
+ * 3 0xb8000000 0x58000000 1 128M 0 1
+ * 4 0x80000000 0x40000000 1 128M 1 1
+ * 5 0x88000000 0x48000000 1 128M 1 1
+ * 6 0x90000000 0x50000000 1 128M 1 1
+ * 7 0x98000000 0x58000000 1 128M 1 1
+ */
+static void set_pmb_on_board_init(void)
+{
+ struct mmu_regs *mmu = MMU_BASE;
+
+ /* clear ITLB */
+ writel(0x00000004, &mmu->mmucr);
+
+ /* delete PMB for SPIBOOT */
+ writel(0, PMB_ADDR_BASE(0));
+ writel(0, PMB_DATA_BASE(0));
+
+ /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
+ /* ppn ub v s1 s0 c wt */
+ writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0));
+ writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0));
+ writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2));
+ writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2));
+ writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3));
+ writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3));
+ writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4));
+ writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4));
+ writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6));
+ writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6));
+ writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7));
+ writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7));
+}
+
+int board_init(void)
+{
+ init_gpio();
+ set_pmb_on_board_init();
+
+ init_usb_phy();
+ init_gether_mdio();
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+ printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
+
+ return 0;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ struct gpio_regs *gpio = GPIO_BASE;
+
+ writew(readw(&gpio->pgcr) | 0x0040, &gpio->pgcr);
+ writeb(readb(&gpio->pgdr) & ~0x08, &gpio->pgdr); /* Reset */
+ udelay(1);
+ writeb(readb(&gpio->pgdr) | 0x08, &gpio->pgdr); /* Release reset */
+ udelay(200);
+
+ return mmcif_mmc_init();
+}
+
+static int get_sh_eth_mac_raw(unsigned char *buf, int size)
+{
+ struct spi_flash *spi;
+ int ret;
+
+ spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
+ if (spi == NULL) {
+ printf("%s: spi_flash probe failed.\n", __func__);
+ return 1;
+ }
+
+ ret = spi_flash_read(spi, SH7752EVB_ETHERNET_MAC_BASE, size, buf);
+ if (ret) {
+ printf("%s: spi_flash read failed.\n", __func__);
+ spi_flash_free(spi);
+ return 1;
+ }
+ spi_flash_free(spi);
+
+ return 0;
+}
+
+static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf)
+{
+ memcpy(mac_string, &buf[channel * (SH7752EVB_ETHERNET_MAC_SIZE + 1)],
+ SH7752EVB_ETHERNET_MAC_SIZE);
+ mac_string[SH7752EVB_ETHERNET_MAC_SIZE] = 0x00; /* terminate */
+
+ return 0;
+}
+
+static void init_ethernet_mac(void)
+{
+ char mac_string[64];
+ char env_string[64];
+ int i;
+ unsigned char *buf;
+
+ buf = malloc(256);
+ if (!buf) {
+ printf("%s: malloc failed.\n", __func__);
+ return;
+ }
+ get_sh_eth_mac_raw(buf, 256);
+
+ /* Gigabit Ethernet */
+ for (i = 0; i < SH7752EVB_ETHERNET_NUM_CH; i++) {
+ get_sh_eth_mac(i, mac_string, buf);
+ if (i == 0)
+ setenv("ethaddr", mac_string);
+ else {
+ sprintf(env_string, "eth%daddr", i);
+ setenv(env_string, mac_string);
+ }
+ set_mac_to_sh_giga_eth_register(i, mac_string);
+ }
+
+ free(buf);
+}
+
+int board_late_init(void)
+{
+ init_ethernet_mac();
+
+ return 0;
+}
+
+int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int i, ret;
+ char mac_string[256];
+ struct spi_flash *spi;
+ unsigned char *buf;
+
+ if (argc != 3) {
+ buf = malloc(256);
+ if (!buf) {
+ printf("%s: malloc failed.\n", __func__);
+ return 1;
+ }
+
+ get_sh_eth_mac_raw(buf, 256);
+
+ /* print current MAC address */
+ for (i = 0; i < SH7752EVB_ETHERNET_NUM_CH; i++) {
+ get_sh_eth_mac(i, mac_string, buf);
+ printf("GETHERC ch%d = %s\n", i, mac_string);
+ }
+ free(buf);
+ return 0;
+ }
+
+ /* new setting */
+ memset(mac_string, 0xff, sizeof(mac_string));
+ sprintf(mac_string, "%s\t%s",
+ argv[1], argv[2]);
+
+ /* write MAC data to SPI rom */
+ spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
+ if (!spi) {
+ printf("%s: spi_flash probe failed.\n", __func__);
+ return 1;
+ }
+
+ ret = spi_flash_erase(spi, SH7752EVB_ETHERNET_MAC_BASE_SPI,
+ SH7752EVB_SPI_SECTOR_SIZE);
+ if (ret) {
+ printf("%s: spi_flash erase failed.\n", __func__);
+ return 1;
+ }
+
+ ret = spi_flash_write(spi, SH7752EVB_ETHERNET_MAC_BASE_SPI,
+ sizeof(mac_string), mac_string);
+ if (ret) {
+ printf("%s: spi_flash write failed.\n", __func__);
+ spi_flash_free(spi);
+ return 1;
+ }
+ spi_flash_free(spi);
+
+ puts("The writing of the MAC address to SPI ROM was completed.\n");
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ write_mac, 3, 1, do_write_mac,
+ "write MAC address for GETHERC",
+ "[GETHERC ch0] [GETHERC ch1]\n"
+);
--- /dev/null
+/*
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License. See the file "COPYING.LIB" in the main
+ * directory of this archive for more details.
+ */
+
+#include <common.h>
+
+#define CONFIG_RAM_BOOT_PHYS CONFIG_SYS_TEXT_BASE
+#define CONFIG_SPI_ADDR 0x00000000
+#define CONFIG_SPI_LENGTH CONFIG_SYS_MONITOR_LEN
+#define CONFIG_RAM_BOOT CONFIG_SYS_TEXT_BASE
+
+#define SPIWDMADR 0xFE001018
+#define SPIWDMCNTR 0xFE001020
+#define SPIDMCOR 0xFE001028
+#define SPIDMINTSR 0xFE001188
+#define SPIDMINTMR 0xFE001190
+
+#define SPIDMINTSR_DMEND 0x00000004
+
+#define TBR 0xFE002000
+#define RBR 0xFE002000
+
+#define CR1 0xFE002008
+#define CR2 0xFE002010
+#define CR3 0xFE002018
+#define CR4 0xFE002020
+
+/* CR1 */
+#define SPI_TBE 0x80
+#define SPI_TBF 0x40
+#define SPI_RBE 0x20
+#define SPI_RBF 0x10
+#define SPI_PFONRD 0x08
+#define SPI_SSDB 0x04
+#define SPI_SSD 0x02
+#define SPI_SSA 0x01
+
+/* CR2 */
+#define SPI_RSTF 0x80
+#define SPI_LOOPBK 0x40
+#define SPI_CPOL 0x20
+#define SPI_CPHA 0x10
+#define SPI_L1M0 0x08
+
+/* CR4 */
+#define SPI_TBEI 0x80
+#define SPI_TBFI 0x40
+#define SPI_RBEI 0x20
+#define SPI_RBFI 0x10
+#define SPI_SpiS0 0x02
+#define SPI_SSS 0x01
+
+#define spi_write(val, addr) (*(volatile unsigned long *)(addr)) = val
+#define spi_read(addr) (*(volatile unsigned long *)(addr))
+
+/* M25P80 */
+#define M25_READ 0x03
+
+#define __uses_spiboot2 __attribute__((section(".spiboot2.text")))
+static void __uses_spiboot2 spi_reset(void)
+{
+ int timeout = 0x00100000;
+
+ /* Make sure the last transaction is finalized */
+ spi_write(0x00, CR3);
+ spi_write(0x02, CR1);
+ while (!(spi_read(CR4) & SPI_SpiS0)) {
+ if (timeout-- < 0)
+ break;
+ }
+ spi_write(0x00, CR1);
+
+ spi_write(spi_read(CR2) | SPI_RSTF, CR2); /* fifo reset */
+ spi_write(spi_read(CR2) & ~SPI_RSTF, CR2);
+
+ spi_write(0, SPIDMCOR);
+}
+
+static void __uses_spiboot2 spi_read_flash(void *buf, unsigned long addr,
+ unsigned long len)
+{
+ spi_write(M25_READ, TBR);
+ spi_write((addr >> 16) & 0xFF, TBR);
+ spi_write((addr >> 8) & 0xFF, TBR);
+ spi_write(addr & 0xFF, TBR);
+
+ spi_write(SPIDMINTSR_DMEND, SPIDMINTSR);
+ spi_write((unsigned long)buf, SPIWDMADR);
+ spi_write(len & 0xFFFFFFE0, SPIWDMCNTR);
+ spi_write(1, SPIDMCOR);
+
+ spi_write(0xff, CR3);
+ spi_write(spi_read(CR1) | SPI_SSDB, CR1);
+ spi_write(spi_read(CR1) | SPI_SSA, CR1);
+
+ while (!(spi_read(SPIDMINTSR) & SPIDMINTSR_DMEND))
+ ;
+
+ /* Nagate SP0-SS0 */
+ spi_write(0, CR1);
+}
+
+void __uses_spiboot2 spiboot_main(void)
+{
+ void (*_start)(void) = (void *)CONFIG_SYS_TEXT_BASE;
+
+ spi_reset();
+ spi_read_flash((void *)CONFIG_RAM_BOOT_PHYS, CONFIG_SPI_ADDR,
+ CONFIG_SPI_LENGTH);
+
+ _start();
+}
--- /dev/null
+/*
+ * Copyright (C) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * Copyright (C) 2012
+ * Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
+OUTPUT_ARCH(sh)
+ENTRY(_start)
+
+SECTIONS
+{
+ /*
+ * entry and reloct_dst will be provided via ldflags
+ */
+ . = .;
+
+ PROVIDE (_ftext = .);
+ PROVIDE (_fcode = .);
+ PROVIDE (_start = .);
+
+ .text :
+ {
+ KEEP(arch/sh/cpu/sh4/start.o (.text))
+ *(.spiboot1.text)
+ *(.spiboot2.text)
+ . = ALIGN(8192);
+ common/env_embedded.o (.ppcenv)
+ . = ALIGN(8192);
+ common/env_embedded.o (.ppcenvr)
+ . = ALIGN(8192);
+ *(.text)
+ . = ALIGN(4);
+ } =0xFF
+ PROVIDE (_ecode = .);
+ .rodata :
+ {
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ . = ALIGN(4);
+ }
+ PROVIDE (_etext = .);
+
+
+ PROVIDE (_fdata = .);
+ .data :
+ {
+ *(.data)
+ . = ALIGN(4);
+ }
+ PROVIDE (_edata = .);
+
+ PROVIDE (_fgot = .);
+ .got :
+ {
+ *(.got)
+ . = ALIGN(4);
+ }
+ PROVIDE (_egot = .);
+
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
+
+ PROVIDE (reloc_dst_end = .);
+ /* _reloc_dst_end = .; */
+
+ PROVIDE (bss_start = .);
+ PROVIDE (__bss_start = .);
+ .bss (NOLOAD) :
+ {
+ *(.bss)
+ . = ALIGN(4);
+ }
+ PROVIDE (bss_end = .);
+
+ PROVIDE (__bss_end__ = .);
+}
--- /dev/null
+/*
+ * SAMSUNG SMDK5250 board device tree source
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+/include/ ARCH_CPU_DTS
+
+/ {
+ model = "SAMSUNG SMDK5250 board based on EXYNOS5250";
+ compatible = "samsung,smdk5250", "samsung,exynos5250";
+
+ aliases {
+ i2c0 = "/i2c@12c60000";
+ i2c1 = "/i2c@12c70000";
+ i2c2 = "/i2c@12c80000";
+ i2c3 = "/i2c@12c90000";
+ i2c4 = "/i2c@12ca0000";
+ i2c5 = "/i2c@12cb0000";
+ i2c6 = "/i2c@12cc0000";
+ i2c7 = "/i2c@12cd0000";
+ spi0 = "/spi@12d20000";
+ spi1 = "/spi@12d30000";
+ spi2 = "/spi@12d40000";
+ spi3 = "/spi@131a0000";
+ spi4 = "/spi@131b0000";
+ };
+
+ sromc@12250000 {
+ bank = <1>;
+ srom-timing = <1 9 12 1 6 1 1>;
+ width = <2>;
+ lan@5000000 {
+ compatible = "smsc,lan9215", "smsc,lan";
+ reg = <0x5000000 0x100>;
+ phy-mode = "mii";
+ };
+ };
+
+ sound@12d60000 {
+ samsung,i2s-epll-clock-frequency = <192000000>;
+ samsung,i2s-sampling-rate = <48000>;
+ samsung,i2s-bits-per-sample = <16>;
+ samsung,i2s-channels = <2>;
+ samsung,i2s-lr-clk-framesize = <256>;
+ samsung,i2s-bit-clk-framesize = <32>;
+ samsung,codec-type = "wm8994";
+ };
+
+ i2c@12c70000 {
+ soundcodec@1a {
+ reg = <0x1a>;
+ compatible = "wolfson,wm8994-codec";
+ };
+ };
+
+ i2c@12c60000 {
+ pmic@9 {
+ reg = <0x9>;
+ compatible = "maxim,max77686_pmic";
+ };
+ };
+};
endif
ifdef CONFIG_SPL_BUILD
-COBJS += mmc_boot.o
+COBJS += spl_boot.o
endif
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+++ /dev/null
-/*
- * Copyright (C) 2012 Samsung Electronics
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include<common.h>
-#include<config.h>
-
-/*
-* Copy U-boot from mmc to RAM:
-* COPY_BL2_FNPTR_ADDR: Address in iRAM, which Contains
-* Pointer to API (Data transfer from mmc to ram)
-*/
-void copy_uboot_to_ram(void)
-{
- u32 (*copy_bl2)(u32, u32, u32) = (void *) *(u32 *)COPY_BL2_FNPTR_ADDR;
-
- copy_bl2(BL2_START_OFFSET, BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE);
-}
-
-void board_init_f(unsigned long bootflag)
-{
- __attribute__((noreturn)) void (*uboot)(void);
- copy_uboot_to_ram();
-
- /* Jump to U-Boot image */
- uboot = (void *)CONFIG_SYS_TEXT_BASE;
- (*uboot)();
- /* Never returns Here */
-}
-
-/* Place Holders */
-void board_init_r(gd_t *id, ulong dest_addr)
-{
- /* Function attribute is no-return */
- /* This Function never executes */
- while (1)
- ;
-}
-
-void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) {}
*/
#include <common.h>
+#include <fdtdec.h>
#include <asm/io.h>
#include <i2c.h>
+#include <lcd.h>
#include <netdev.h>
+#include <spi.h>
#include <asm/arch/cpu.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc.h>
#include <asm/arch/pinmux.h>
+#include <asm/arch/power.h>
#include <asm/arch/sromc.h>
+#include <asm/arch/dp_info.h>
+#include <power/pmic.h>
DECLARE_GLOBAL_DATA_PTR;
-#ifdef CONFIG_SMC911X
-static int smc9115_pre_init(void)
+#ifdef CONFIG_USB_EHCI_EXYNOS
+int board_usb_vbus_init(void)
{
- u32 smc_bw_conf, smc_bc_conf;
- int err;
-
- /* Ethernet needs data bus width of 16 bits */
- smc_bw_conf = SROMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK)
- | SROMC_BYTE_ENABLE(CONFIG_ENV_SROM_BANK);
+ struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
+ samsung_get_base_gpio_part1();
- smc_bc_conf = SROMC_BC_TACS(0x01) | SROMC_BC_TCOS(0x01)
- | SROMC_BC_TACC(0x06) | SROMC_BC_TCOH(0x01)
- | SROMC_BC_TAH(0x0C) | SROMC_BC_TACP(0x09)
- | SROMC_BC_PMC(0x01);
+ /* Enable VBUS power switch */
+ s5p_gpio_direction_output(&gpio1->x2, 6, 1);
- /* Select and configure the SROMC bank */
- err = exynos_pinmux_config(PERIPH_ID_SROMC,
- CONFIG_ENV_SROM_BANK | PINMUX_FLAG_16BIT);
- if (err) {
- debug("SROMC not configured\n");
- return err;
- }
+ /* VBUS turn ON time */
+ mdelay(3);
- s5p_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf);
return 0;
}
#endif
int board_init(void)
{
gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
+#ifdef CONFIG_EXYNOS_SPI
+ spi_init();
+#endif
+#ifdef CONFIG_USB_EHCI_EXYNOS
+ board_usb_vbus_init();
+#endif
return 0;
}
return 0;
}
+#if defined(CONFIG_POWER)
+int power_init_board(void)
+{
+ if (pmic_init(I2C_PMIC))
+ return -1;
+ else
+ return 0;
+}
+#endif
+
void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
PHYS_SDRAM_8_SIZE);
}
+#ifdef CONFIG_OF_CONTROL
+static int decode_sromc(const void *blob, struct fdt_sromc *config)
+{
+ int err;
+ int node;
+
+ node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SROMC);
+ if (node < 0) {
+ debug("Could not find SROMC node\n");
+ return node;
+ }
+
+ config->bank = fdtdec_get_int(blob, node, "bank", 0);
+ config->width = fdtdec_get_int(blob, node, "width", 2);
+
+ err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing,
+ FDT_SROM_TIMING_COUNT);
+ if (err < 0) {
+ debug("Could not decode SROMC configuration\n");
+ return -FDT_ERR_NOTFOUND;
+ }
+
+ return 0;
+}
+#endif
+
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_SMC911X
- if (smc9115_pre_init())
+ u32 smc_bw_conf, smc_bc_conf;
+ struct fdt_sromc config;
+ fdt_addr_t base_addr;
+ int node;
+
+#ifdef CONFIG_OF_CONTROL
+ node = decode_sromc(gd->fdt_blob, &config);
+ if (node < 0) {
+ debug("%s: Could not find sromc configuration\n", __func__);
+ return 0;
+ }
+ node = fdtdec_next_compatible(gd->fdt_blob, node, COMPAT_SMSC_LAN9215);
+ if (node < 0) {
+ debug("%s: Could not find lan9215 configuration\n", __func__);
+ return 0;
+ }
+
+ /* We now have a node, so any problems from now on are errors */
+ base_addr = fdtdec_get_addr(gd->fdt_blob, node, "reg");
+ if (base_addr == FDT_ADDR_T_NONE) {
+ debug("%s: Could not find lan9215 address\n", __func__);
+ return -1;
+ }
+#else
+ /* Non-FDT configuration - bank number and timing parameters*/
+ config.bank = CONFIG_ENV_SROM_BANK;
+ config.width = 2;
+
+ config.timing[FDT_SROM_TACS] = 0x01;
+ config.timing[FDT_SROM_TCOS] = 0x01;
+ config.timing[FDT_SROM_TACC] = 0x06;
+ config.timing[FDT_SROM_TCOH] = 0x01;
+ config.timing[FDT_SROM_TAH] = 0x0C;
+ config.timing[FDT_SROM_TACP] = 0x09;
+ config.timing[FDT_SROM_PMC] = 0x01;
+ base_addr = CONFIG_SMC911X_BASE;
+#endif
+
+ /* Ethernet needs data bus width of 16 bits */
+ if (config.width != 2) {
+ debug("%s: Unsupported bus width %d\n", __func__,
+ config.width);
return -1;
- return smc911x_initialize(0, CONFIG_SMC911X_BASE);
+ }
+ smc_bw_conf = SROMC_DATA16_WIDTH(config.bank)
+ | SROMC_BYTE_ENABLE(config.bank);
+
+ smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS]) |\
+ SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) |\
+ SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) |\
+ SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) |\
+ SROMC_BC_TAH(config.timing[FDT_SROM_TAH]) |\
+ SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) |\
+ SROMC_BC_PMC(config.timing[FDT_SROM_PMC]);
+
+ /* Select and configure the SROMC bank */
+ exynos_pinmux_config(PERIPH_ID_SROMC, config.bank);
+ s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf);
+ return smc911x_initialize(0, base_addr);
#endif
return 0;
}
return 0;
}
-#ifdef CONFIG_SYS_I2C_INIT_BOARD
-static int board_i2c_init(void)
-{
- int i, err;
-
- for (i = 0; i < CONFIG_MAX_I2C_NUM; i++) {
- err = exynos_pinmux_config((PERIPH_ID_I2C0 + i),
- PINMUX_FLAG_NONE);
- if (err) {
- debug("I2C%d not configured\n", (PERIPH_ID_I2C0 + i));
- return err;
- }
- }
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
- return 0;
-}
-#endif
-
#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void)
{
return err;
}
#ifdef CONFIG_SYS_I2C_INIT_BOARD
- err = board_i2c_init();
+ board_i2c_init(gd->fdt_blob);
#endif
return err;
}
#endif
+
+#ifdef CONFIG_LCD
+void cfg_lcd_gpio(void)
+{
+ struct exynos5_gpio_part1 *gpio1 =
+ (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
+
+ /* For Backlight */
+ s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT);
+ s5p_gpio_set_value(&gpio1->b2, 0, 1);
+
+ /* LCD power on */
+ s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT);
+ s5p_gpio_set_value(&gpio1->x1, 5, 1);
+
+ /* Set Hotplug detect for DP */
+ s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3));
+}
+
+vidinfo_t panel_info = {
+ .vl_freq = 60,
+ .vl_col = 2560,
+ .vl_row = 1600,
+ .vl_width = 2560,
+ .vl_height = 1600,
+ .vl_clkp = CONFIG_SYS_LOW,
+ .vl_hsp = CONFIG_SYS_LOW,
+ .vl_vsp = CONFIG_SYS_LOW,
+ .vl_dp = CONFIG_SYS_LOW,
+ .vl_bpix = 4, /* LCD_BPP = 2^4, for output conosle on LCD */
+
+ /* wDP panel timing infomation */
+ .vl_hspw = 32,
+ .vl_hbpd = 80,
+ .vl_hfpd = 48,
+
+ .vl_vspw = 6,
+ .vl_vbpd = 37,
+ .vl_vfpd = 3,
+ .vl_cmd_allow_len = 0xf,
+
+ .win_id = 3,
+ .cfg_gpio = cfg_lcd_gpio,
+ .backlight_on = NULL,
+ .lcd_power_on = NULL,
+ .reset_lcd = NULL,
+ .dual_lcd_enabled = 0,
+
+ .init_delay = 0,
+ .power_on_delay = 0,
+ .reset_delay = 0,
+ .interface_mode = FIMD_RGB_INTERFACE,
+ .dp_enabled = 1,
+};
+
+static struct edp_device_info edp_info = {
+ .disp_info = {
+ .h_res = 2560,
+ .h_sync_width = 32,
+ .h_back_porch = 80,
+ .h_front_porch = 48,
+ .v_res = 1600,
+ .v_sync_width = 6,
+ .v_back_porch = 37,
+ .v_front_porch = 3,
+ .v_sync_rate = 60,
+ },
+ .lt_info = {
+ .lt_status = DP_LT_NONE,
+ },
+ .video_info = {
+ .master_mode = 0,
+ .bist_mode = DP_DISABLE,
+ .bist_pattern = NO_PATTERN,
+ .h_sync_polarity = 0,
+ .v_sync_polarity = 0,
+ .interlaced = 0,
+ .color_space = COLOR_RGB,
+ .dynamic_range = VESA,
+ .ycbcr_coeff = COLOR_YCBCR601,
+ .color_depth = COLOR_8,
+ },
+};
+
+static struct exynos_dp_platform_data dp_platform_data = {
+ .phy_enable = set_dp_phy_ctrl,
+ .edp_dev_info = &edp_info,
+};
+
+void init_panel_info(vidinfo_t *vid)
+{
+ vid->rgb_mode = MODE_RGB_P,
+
+ exynos_set_dp_platform_data(&dp_platform_data);
+}
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include<common.h>
+#include<config.h>
+
+enum boot_mode {
+ BOOT_MODE_MMC = 4,
+ BOOT_MODE_SERIAL = 20,
+ /* Boot based on Operating Mode pin settings */
+ BOOT_MODE_OM = 32,
+ BOOT_MODE_USB, /* Boot using USB download */
+};
+
+ typedef u32 (*spi_copy_func_t)(u32 offset, u32 nblock, u32 dst);
+
+/*
+* Copy U-boot from mmc to RAM:
+* COPY_BL2_FNPTR_ADDR: Address in iRAM, which Contains
+* Pointer to API (Data transfer from mmc to ram)
+*/
+void copy_uboot_to_ram(void)
+{
+ spi_copy_func_t spi_copy;
+ enum boot_mode bootmode;
+ u32 (*copy_bl2)(u32, u32, u32);
+
+ bootmode = readl(EXYNOS5_POWER_BASE) & OM_STAT;
+
+ switch (bootmode) {
+ case BOOT_MODE_SERIAL:
+ spi_copy = *(spi_copy_func_t *)EXYNOS_COPY_SPI_FNPTR_ADDR;
+ spi_copy(SPI_FLASH_UBOOT_POS, CONFIG_BL2_SIZE,
+ CONFIG_SYS_TEXT_BASE);
+ break;
+ case BOOT_MODE_MMC:
+ copy_bl2 = (void *) *(u32 *)COPY_BL2_FNPTR_ADDR;
+ copy_bl2(BL2_START_OFFSET, BL2_SIZE_BLOC_COUNT,
+ CONFIG_SYS_TEXT_BASE);
+ break;
+ default:
+ break;
+ }
+}
+
+void board_init_f(unsigned long bootflag)
+{
+ __attribute__((noreturn)) void (*uboot)(void);
+ copy_uboot_to_ram();
+
+ /* Jump to U-Boot image */
+ uboot = (void *)CONFIG_SYS_TEXT_BASE;
+ (*uboot)();
+ /* Never returns Here */
+}
+
+/* Place Holders */
+void board_init_r(gd_t *id, ulong dest_addr)
+{
+ /* Function attribute is no-return */
+ /* This Function never executes */
+ while (1)
+ ;
+}
+
+void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) {}
#include <asm/arch/cpu.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc.h>
+#include <asm/arch/pinmux.h>
#include <asm/arch/clock.h>
#include <asm/arch/clk.h>
#include <asm/arch/mipi_dsim.h>
int board_init(void)
{
- gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+ gd->bd->bi_boot_params = CONFIG_SYS_SPL_ARGS_ADDR;
check_hw_revision();
printf("HW Revision:\t0x%x\n", board_rev);
int dram_init(void)
{
gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) +
- get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
+ get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE) +
+ get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE) +
+ get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE);
return 0;
}
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+ gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+ gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+ gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
+ gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
}
static unsigned int get_hw_revision(void)
{
struct exynos4_gpio_part2 *gpio =
(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
- int i, err;
+ int err;
/* eMMC_EN: SD_0_CDn: GPK0[2] Output High */
s5p_gpio_direction_output(&gpio->k0, 2, 1);
s5p_gpio_set_pull(&gpio->k0, 2, GPIO_PULL_NONE);
- /*
- * eMMC GPIO:
- * SDR 8-bit@48MHz at MMC0
- * GPK0[0] SD_0_CLK(2)
- * GPK0[1] SD_0_CMD(2)
- * GPK0[2] SD_0_CDn -> Not used
- * GPK0[3:6] SD_0_DATA[0:3](2)
- * GPK1[3:6] SD_0_DATA[0:3](3)
- *
- * DDR 4-bit@26MHz at MMC4
- * GPK0[0] SD_4_CLK(3)
- * GPK0[1] SD_4_CMD(3)
- * GPK0[2] SD_4_CDn -> Not used
- * GPK0[3:6] SD_4_DATA[0:3](3)
- * GPK1[3:6] SD_4_DATA[4:7](4)
- */
- for (i = 0; i < 7; i++) {
- if (i == 2)
- continue;
- /* GPK0[0:6] special function 2 */
- s5p_gpio_cfg_pin(&gpio->k0, i, 0x2);
- /* GPK0[0:6] pull disable */
- s5p_gpio_set_pull(&gpio->k0, i, GPIO_PULL_NONE);
- /* GPK0[0:6] drv 4x */
- s5p_gpio_set_drv(&gpio->k0, i, GPIO_DRV_4X);
- }
-
- for (i = 3; i < 7; i++) {
- /* GPK1[3:6] special function 3 */
- s5p_gpio_cfg_pin(&gpio->k1, i, 0x3);
- /* GPK1[3:6] pull disable */
- s5p_gpio_set_pull(&gpio->k1, i, GPIO_PULL_NONE);
- /* GPK1[3:6] drv 4x */
- s5p_gpio_set_drv(&gpio->k1, i, GPIO_DRV_4X);
- }
-
/*
* MMC device init
* mmc0 : eMMC (8-bit buswidth)
* mmc2 : SD card (4-bit buswidth)
*/
- err = s5p_mmc_init(0, 8);
+ err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
+ if (err)
+ debug("SDMMC0 not configured\n");
+ else
+ err = s5p_mmc_init(0, 8);
/* T-flash detect */
s5p_gpio_cfg_pin(&gpio->x3, 4, 0xf);
* GPX3[4] T-flash detect pin
*/
if (!s5p_gpio_get_value(&gpio->x3, 4)) {
- /*
- * SD card GPIO:
- * GPK2[0] SD_2_CLK(2)
- * GPK2[1] SD_2_CMD(2)
- * GPK2[2] SD_2_CDn -> Not used
- * GPK2[3:6] SD_2_DATA[0:3](2)
- */
- for (i = 0; i < 7; i++) {
- if (i == 2)
- continue;
- /* GPK2[0:6] special function 2 */
- s5p_gpio_cfg_pin(&gpio->k2, i, 0x2);
- /* GPK2[0:6] pull disable */
- s5p_gpio_set_pull(&gpio->k2, i, GPIO_PULL_NONE);
- /* GPK2[0:6] drv 4x */
- s5p_gpio_set_drv(&gpio->k2, i, GPIO_DRV_4X);
- }
- err = s5p_mmc_init(2, 4);
+ err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
+ if (err)
+ debug("SDMMC2 not configured\n");
+ else
+ err = s5p_mmc_init(2, 4);
}
return err;
writel(0, (unsigned int)&pwr->lcd1_configuration);
writel(0, (unsigned int)&pwr->gps_configuration);
writel(0, (unsigned int)&pwr->gps_alive_configuration);
+
+ /* It is necessary to power down core 1 */
+ /* to successfully boot CPU1 in kernel */
+ writel(0, (unsigned int)&pwr->arm_core1_configuration);
}
static void board_uart_init(void)
LIB = $(obj)lib$(BOARD).o
COBJS-y := universal.o onenand.o
-SOBJS := lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
+++ /dev/null
-/*
- * Lowlevel setup for universal board based on EXYNOS4210
- *
- * Copyright (C) 2010 Samsung Electronics
- * Kyungmin Park <kyungmin.park@samsung.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/clock.h>
-
-/*
- * Register usages:
- *
- * r5 has zero always
- * r7 has GPIO part1 base 0x11400000
- * r6 has GPIO part2 base 0x11000000
- */
-
- .globl lowlevel_init
-lowlevel_init:
- mov r11, lr
-
- /* r5 has always zero */
- mov r5, #0
-
- ldr r7, =EXYNOS4_GPIO_PART1_BASE
- ldr r6, =EXYNOS4_GPIO_PART2_BASE
-
- /* System Timer */
- ldr r0, =EXYNOS4_SYSTIMER_BASE
- ldr r1, =0x5000
- str r1, [r0, #0x0]
- ldr r1, =0xffffffff
- str r1, [r0, #0x8]
- ldr r1, =0x49
- str r1, [r0, #0x4]
-
- /* PMIC manual reset */
- /* nPOWER: XEINT_23: GPX2[7] */
- add r0, r6, #0xC40 @ EXYNOS4_GPIO_X2_OFFSET
- ldr r1, [r0, #0x0]
- bic r1, r1, #(0xf << 28) @ 28 = 7 * 4-bit
- orr r1, r1, #(0x1 << 28) @ Output
- str r1, [r0, #0x0]
-
- ldr r1, [r0, #0x4]
- orr r1, r1, #(1 << 7) @ 7 = 7 * 1-bit
- str r1, [r0, #0x4]
-
- /* init system clock */
- bl system_clock_init
-
- /* Disable Watchdog */
- ldr r0, =EXYNOS4_WATCHDOG_BASE @0x10060000
- str r5, [r0]
-
- /* UART */
- bl uart_asm_init
-
- /* PMU init */
- bl system_power_init
-
- bl tzpc_init
-
- mov lr, r11
- mov pc, lr
- nop
- nop
- nop
-
-/*
- * uart_asm_init: Initialize UART's pins
- */
-uart_asm_init:
- /*
- * setup UART0-UART4 GPIOs (part1)
- * GPA1CON[3] = I2C_3_SCL (3)
- * GPA1CON[2] = I2C_3_SDA (3)
- */
- mov r0, r7
- ldr r1, =0x22222222
- str r1, [r0, #0x00] @ EXYNOS4_GPIO_A0_OFFSET
- ldr r1, =0x00223322
- str r1, [r0, #0x20] @ EXYNOS4_GPIO_A1_OFFSET
-
- /* UART_SEL GPY4[7] (part2) at EXYNOS4 */
- add r0, r6, #0x1A0 @ EXYNOS4_GPIO_Y4_OFFSET
- ldr r1, [r0, #0x0]
- bic r1, r1, #(0xf << 28) @ 28 = 7 * 4-bit
- orr r1, r1, #(0x1 << 28)
- str r1, [r0, #0x0]
-
- ldr r1, [r0, #0x8]
- bic r1, r1, #(0x3 << 14) @ 14 = 7 * 2-bit
- orr r1, r1, #(0x3 << 14) @ Pull-up enabled
- str r1, [r0, #0x8]
-
- ldr r1, [r0, #0x4]
- orr r1, r1, #(1 << 7) @ 7 = 7 * 1-bit
- str r1, [r0, #0x4]
-
- mov pc, lr
- nop
- nop
- nop
-
-system_clock_init:
- ldr r0, =EXYNOS4_CLOCK_BASE
-
- /* APLL(1), MPLL(1), CORE(0), HPM(0) */
- ldr r1, =0x0101
- ldr r2, =0x14200 @ CLK_SRC_CPU
- str r1, [r0, r2]
-
- /* wait ?us */
- mov r1, #0x10000
-1: subs r1, r1, #1
- bne 1b
-
- /*
- * CLK_SRC_TOP0
- * MUX_ONENAND_SEL[28] 0: DOUT133, 1: DOUT166
- * MUX_VPLL_SEL[8] 0: FINPLL, 1: FOUTVPLL
- * MUX_EPLL_SEL[4] 0: FINPLL, 1: FOUTEPLL
- */
- ldr r1, =0x10000110
- ldr r2, =0x0C210 @ CLK_SRC_TOP
- str r1, [r0, r2]
-
- /* SATA: SCLKMPLL(0), MMC[0:4]: SCLKMPLL(6) */
- ldr r1, =0x0066666
- ldr r2, =0x0C240 @ CLK_SRC_FSYS
- str r1, [r0, r2]
- /* UART[0:5], PWM: SCLKMPLL(6) */
- ldr r1, =0x6666666
- ldr r2, =0x0C250 @ CLK_SRC_PERIL0_OFFSET
- str r1, [r0, r2]
-
- /* CPU0: CORE, COREM0, COREM1, PERI, ATB, PCLK_DBG, APLL */
- ldr r1, =0x0133730
- ldr r2, =0x14500 @ CLK_DIV_CPU0
- str r1, [r0, r2]
- /* CPU1: COPY, HPM */
- ldr r1, =0x03
- ldr r2, =0x14504 @ CLK_DIV_CPU1
- str r1, [r0, r2]
- /* DMC0: ACP, ACP_PCLK, DPHY, DMC, DMCD, DMCP, COPY2 CORE_TIMER */
- ldr r1, =0x13111113
- ldr r2, =0x10500 @ CLK_DIV_DMC0
- str r1, [r0, r2]
- /* DMC1: PWI, DVSEM, DPM */
- ldr r1, =0x01010100
- ldr r2, =0x10504 @ CLK_DIV_DMC1
- str r1, [r0, r2]
- /* LEFTBUS: GDL, GPL */
- ldr r1, =0x13
- ldr r2, =0x04500 @ CLK_DIV_LEFTBUS
- str r1, [r0, r2]
- /* RIGHHTBUS: GDR, GPR */
- ldr r1, =0x13
- ldr r2, =0x08500 @ CLK_DIV_RIGHTBUS
- str r1, [r0, r2]
- /*
- * CLK_DIV_TOP
- * ONENAND_RATIOD[18:16]: 0 SCLK_ONENAND = MOUTONENAND / (n + 1)
- * ACLK_200, ACLK_100, ACLK_160, ACLK_133,
- */
- ldr r1, =0x00005473
- ldr r2, =0x0C510 @ CLK_DIV_TOP
- str r1, [r0, r2]
- /* MMC[0:1] */
- ldr r1, =0x000f000f /* 800(MPLL) / (15 + 1) */
- ldr r2, =0x0C544 @ CLK_DIV_FSYS1
- str r1, [r0, r2]
- /* MMC[2:3] */
- ldr r1, =0x000f000f /* 800(MPLL) / (15 + 1) */
- ldr r2, =0x0C548 @ CLK_DIV_FSYS2
- str r1, [r0, r2]
- /* MMC4 */
- ldr r1, =0x000f /* 800(MPLL) / (15 + 1) */
- ldr r2, =0x0C54C @ CLK_DIV_FSYS3
- str r1, [r0, r2]
- /* UART[0:5] */
- ldr r1, =0x774777
- ldr r2, =0x0C550 @ CLK_DIV_PERIL0
- str r1, [r0, r2]
- /* SLIMBUS: ???, PWM */
- ldr r1, =0x8
- ldr r2, =0x0C55C @ CLK_DIV_PERIL3
- str r1, [r0, r2]
-
- /* PLL Setting */
- ldr r1, =0x1C20
- ldr r2, =0x14000 @ APLL_LOCK
- str r1, [r0, r2]
- ldr r2, =0x14008 @ MPLL_LOCK
- str r1, [r0, r2]
- ldr r2, =0x0C010 @ EPLL_LOCK
- str r1, [r0, r2]
- ldr r2, =0x0C020 @ VPLL_LOCK
- str r1, [r0, r2]
-
- /* APLL */
- ldr r1, =0x8000001c
- ldr r2, =0x14104 @ APLL_CON1
- str r1, [r0, r2]
- ldr r1, =0x80c80601 @ 800MHz
- ldr r2, =0x14100 @ APLL_CON0
- str r1, [r0, r2]
- /* MPLL */
- ldr r1, =0x8000001C
- ldr r2, =0x1410C @ MPLL_CON1
- str r1, [r0, r2]
- ldr r1, =0x80c80601 @ 800MHz
- ldr r2, =0x14108 @ MPLL_CON0
- str r1, [r0, r2]
- /* EPLL */
- ldr r1, =0x0
- ldr r2, =0x0C114 @ EPLL_CON1
- str r1, [r0, r2]
- ldr r1, =0x80300302 @ 96MHz
- ldr r2, =0x0C110 @ EPLL_CON0
- str r1, [r0, r2]
- /* VPLL */
- ldr r1, =0x11000400
- ldr r2, =0x0C124 @ VPLL_CON1
- str r1, [r0, r2]
- ldr r1, =0x80350302 @ 108MHz
- ldr r2, =0x0C120 @ VPLL_CON0
- str r1, [r0, r2]
-
- /*
- * SMMUJPEG[11], JPEG[6], CSIS1[5] : 0111 1001
- * Turn off all
- */
- ldr r1, =0xFFF80000
- ldr r2, =0x0C920 @ CLK_GATE_IP_CAM
- str r1, [r0, r2]
-
- /* Turn off all */
- ldr r1, =0xFFFFFFC0
- ldr r2, =0x0C924 @ CLK_GATE_IP_VP
- str r1, [r0, r2]
-
- /* Turn off all */
- ldr r1, =0xFFFFFFE0
- ldr r2, =0x0C928 @ CLK_GATE_IP_MFC
- str r1, [r0, r2]
-
- /* Turn off all */
- ldr r1, =0xFFFFFFFC
- ldr r2, =0x0C92C @ CLK_GATE_IP_G3D
- str r1, [r0, r2]
-
- /* Turn off all */
- ldr r1, =0xFFFFFC00
- ldr r2, =0x0C930 @ CLK_GATE_IP_IMAGE
- str r1, [r0, r2]
-
- /* DSIM0[3], MDNIE0[2], MIE0[1] : 0001 */
- ldr r1, =0xFFFFFFF1
- ldr r2, =0x0C934 @ CLK_GATE_IP_LCD0
- str r1, [r0, r2]
-
- /* Turn off all */
- ldr r1, =0xFFFFFFC0
- ldr r2, =0x0C938 @ CLK_GATE_IP_LCD1
- str r1, [r0, r2]
-
- /*
- * SMMUPCIE[18], NFCON[16] : 1111 1010
- * PCIE[14], SATA[10], SDMMC43[9:8] : 1011 1000
- * SDMMC1[6], TSI[4], SATAPHY[3], PCIEPHY[2] : 1010 0011
- */
- ldr r1, =0xFFFAB8A3
- ldr r2, =0x0C940 @ CLK_GATE_IP_FSYS
- str r1, [r0, r2]
-
- /* Turn off all */
- ldr r1, =0xFFFFFFFC
- ldr r2, =0x0C94C @ CLK_GATE_IP_GPS
- str r1, [r0, r2]
-
- /*
- * AC97[27], SPDIF[26], SLIMBUS[25] : 1111 0001
- * I2C2[8] : 1111 1110
- */
- ldr r1, =0xF1FFFEFF
- ldr r2, =0x0C950 @ CLK_GATE_IP_PERIL
- str r1, [r0, r2]
-
- /*
- * KEYIF[16] : 1111 1110
- */
- ldr r1, =0xFFFEFFFF
- ldr r2, =0x0C960 @ CLK_GATE_IP_PERIR
- str r1, [r0, r2]
-
- /* LCD1[5], G3D[3], MFC[2], TV[1] : 1101 0001 */
- ldr r1, =0xFFFFFFD1
- ldr r2, =0x0C970 @ CLK_GATE_BLOCK
- str r1, [r0, r2]
- mov pc, lr
- nop
- nop
- nop
-
-system_power_init:
- ldr r0, =EXYNOS4_POWER_BASE @ 0x10020000
-
- ldr r2, =0x330C @ PS_HOLD_CONTROL
- ldr r1, [r0, r2]
- orr r1, r1, #(0x3 << 8) @ Data High, Output En
- str r1, [r0, r2]
-
- /* Power Down */
- add r2, r0, #0x3000
- str r5, [r2, #0xC20] @ TV_CONFIGURATION
- str r5, [r2, #0xC40] @ MFC_CONFIGURATION
- str r5, [r2, #0xC60] @ G3D_CONFIGURATION
- str r5, [r2, #0xCA0] @ LCD1_CONFIGURATION
- str r5, [r2, #0xCE0] @ GPS_CONFIGURATION
-
- mov pc, lr
- nop
- nop
- nop
-
-tzpc_init:
- ldr r0, =0x10110000
- mov r1, #0x0
- str r1, [r0]
- mov r1, #0xff
- str r1, [r0, #0x0804]
- str r1, [r0, #0x0810]
- str r1, [r0, #0x081C]
- str r1, [r0, #0x0828]
-
- ldr r0, =0x10120000
- mov r1, #0x0
- str r1, [r0]
- mov r1, #0xff
- str r1, [r0, #0x0804]
- str r1, [r0, #0x0810]
- str r1, [r0, #0x081C]
- str r1, [r0, #0x0828]
-
- ldr r0, =0x10130000
- mov r1, #0x0
- str r1, [r0]
- mov r1, #0xff
- str r1, [r0, #0x0804]
- str r1, [r0, #0x0810]
- str r1, [r0, #0x081C]
- str r1, [r0, #0x0828]
-
- ldr r0, =0x10140000
- mov r1, #0x0
- str r1, [r0]
- mov r1, #0xff
- str r1, [r0, #0x0804]
- str r1, [r0, #0x0810]
- str r1, [r0, #0x081C]
- str r1, [r0, #0x0828]
-
- ldr r0, =0x10150000
- mov r1, #0x0
- str r1, [r0]
- mov r1, #0xff
- str r1, [r0, #0x0804]
- str r1, [r0, #0x0810]
- str r1, [r0, #0x081C]
- str r1, [r0, #0x0828]
-
- mov pc, lr
*/
#include <common.h>
+#include <spi.h>
+#include <lcd.h>
#include <asm/io.h>
+#include <asm/gpio.h>
#include <asm/arch/adc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/watchdog.h>
+#include <libtizen.h>
+#include <ld9040.h>
#include <power/pmic.h>
#include <usb/s3c_udc.h>
#include <asm/arch/cpu.h>
return board_rev & 0xFF;
}
-static void check_hw_revision(void);
-
-int board_init(void)
-{
- gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE;
- gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE;
-
- gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210;
- gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
- check_hw_revision();
- printf("HW Revision:\t0x%x\n", board_rev);
-
- return 0;
-}
+static void init_pmic_lcd(void);
int power_init_board(void)
{
if (ret)
return ret;
+ init_pmic_lcd();
+
return 0;
}
#ifdef CONFIG_GENERIC_MMC
int board_mmc_init(bd_t *bis)
{
- int i, err;
+ int err;
switch (get_hwrev()) {
case 0:
}
/*
- * eMMC GPIO:
- * SDR 8-bit@48MHz at MMC0
- * GPK0[0] SD_0_CLK(2)
- * GPK0[1] SD_0_CMD(2)
- * GPK0[2] SD_0_CDn -> Not used
- * GPK0[3:6] SD_0_DATA[0:3](2)
- * GPK1[3:6] SD_0_DATA[0:3](3)
- *
- * DDR 4-bit@26MHz at MMC4
- * GPK0[0] SD_4_CLK(3)
- * GPK0[1] SD_4_CMD(3)
- * GPK0[2] SD_4_CDn -> Not used
- * GPK0[3:6] SD_4_DATA[0:3](3)
- * GPK1[3:6] SD_4_DATA[4:7](4)
+ * MMC device init
+ * mmc0 : eMMC (8-bit buswidth)
+ * mmc2 : SD card (4-bit buswidth)
*/
- for (i = 0; i < 7; i++) {
- if (i == 2)
- continue;
- /* GPK0[0:6] special function 2 */
- s5p_gpio_cfg_pin(&gpio2->k0, i, 0x2);
- /* GPK0[0:6] pull disable */
- s5p_gpio_set_pull(&gpio2->k0, i, GPIO_PULL_NONE);
- /* GPK0[0:6] drv 4x */
- s5p_gpio_set_drv(&gpio2->k0, i, GPIO_DRV_4X);
- }
-
- for (i = 3; i < 7; i++) {
- /* GPK1[3:6] special function 3 */
- s5p_gpio_cfg_pin(&gpio2->k1, i, 0x3);
- /* GPK1[3:6] pull disable */
- s5p_gpio_set_pull(&gpio2->k1, i, GPIO_PULL_NONE);
- /* GPK1[3:6] drv 4x */
- s5p_gpio_set_drv(&gpio2->k1, i, GPIO_DRV_4X);
- }
+ err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
+ if (err)
+ debug("SDMMC0 not configured\n");
+ else
+ err = s5p_mmc_init(0, 8);
/* T-flash detect */
s5p_gpio_cfg_pin(&gpio2->x3, 4, 0xf);
s5p_gpio_set_pull(&gpio2->x3, 4, GPIO_PULL_UP);
- /*
- * MMC device init
- * mmc0 : eMMC (8-bit buswidth)
- * mmc2 : SD card (4-bit buswidth)
- */
- err = s5p_mmc_init(0, 8);
-
/*
* Check the T-flash detect pin
* GPX3[4] T-flash detect pin
*/
if (!s5p_gpio_get_value(&gpio2->x3, 4)) {
- /*
- * SD card GPIO:
- * GPK2[0] SD_2_CLK(2)
- * GPK2[1] SD_2_CMD(2)
- * GPK2[2] SD_2_CDn -> Not used
- * GPK2[3:6] SD_2_DATA[0:3](2)
- */
- for (i = 0; i < 7; i++) {
- if (i == 2)
- continue;
- /* GPK2[0:6] special function 2 */
- s5p_gpio_cfg_pin(&gpio2->k2, i, 0x2);
- /* GPK2[0:6] pull disable */
- s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_NONE);
- /* GPK2[0:6] drv 4x */
- s5p_gpio_set_drv(&gpio2->k2, i, GPIO_DRV_4X);
- }
- err = s5p_mmc_init(2, 4);
+ err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
+ if (err)
+ debug("SDMMC2 not configured\n");
+ else
+ err = s5p_mmc_init(2, 4);
}
return err;
.usb_flags = PHY0_SLEEP,
};
#endif
+
+int board_early_init_f(void)
+{
+ wdt_stop();
+
+ return 0;
+}
+
+#ifdef CONFIG_SOFT_SPI
+static void soft_spi_init(void)
+{
+ gpio_direction_output(CONFIG_SOFT_SPI_GPIO_SCLK,
+ CONFIG_SOFT_SPI_MODE & SPI_CPOL);
+ gpio_direction_output(CONFIG_SOFT_SPI_GPIO_MOSI, 1);
+ gpio_direction_input(CONFIG_SOFT_SPI_GPIO_MISO);
+ gpio_direction_output(CONFIG_SOFT_SPI_GPIO_CS,
+ !(CONFIG_SOFT_SPI_MODE & SPI_CS_HIGH));
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ gpio_set_value(CONFIG_SOFT_SPI_GPIO_CS,
+ !(CONFIG_SOFT_SPI_MODE & SPI_CS_HIGH));
+ SPI_SCL(1);
+ gpio_set_value(CONFIG_SOFT_SPI_GPIO_CS,
+ CONFIG_SOFT_SPI_MODE & SPI_CS_HIGH);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ gpio_set_value(CONFIG_SOFT_SPI_GPIO_CS,
+ !(CONFIG_SOFT_SPI_MODE & SPI_CS_HIGH));
+}
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return bus == 0 && cs == 0;
+}
+
+void universal_spi_scl(int bit)
+{
+ gpio_set_value(CONFIG_SOFT_SPI_GPIO_SCLK, bit);
+}
+
+void universal_spi_sda(int bit)
+{
+ gpio_set_value(CONFIG_SOFT_SPI_GPIO_MOSI, bit);
+}
+
+int universal_spi_read(void)
+{
+ return gpio_get_value(CONFIG_SOFT_SPI_GPIO_MISO);
+}
+#endif
+
+static void init_pmic_lcd(void)
+{
+ unsigned char val;
+ int ret = 0;
+
+ struct pmic *p = pmic_get("MAX8998_PMIC");
+
+ if (!p)
+ return;
+
+ if (pmic_probe(p))
+ return;
+
+ /* LDO7 1.8V */
+ val = 0x02; /* (1800 - 1600) / 100; */
+ ret |= pmic_reg_write(p, MAX8998_REG_LDO7, val);
+
+ /* LDO17 3.0V */
+ val = 0xe; /* (3000 - 1600) / 100; */
+ ret |= pmic_reg_write(p, MAX8998_REG_LDO17, val);
+
+ /* Disable unneeded regulators */
+ /*
+ * ONOFF1
+ * Buck1 ON, Buck2 OFF, Buck3 ON, Buck4 ON
+ * LDO2 ON, LDO3 OFF, LDO4 OFF, LDO5 ON
+ */
+ val = 0xB9;
+ ret |= pmic_reg_write(p, MAX8998_REG_ONOFF1, val);
+
+ /* ONOFF2
+ * LDO6 OFF, LDO7 ON, LDO8 OFF, LDO9 ON,
+ * LDO10 OFF, LDO11 OFF, LDO12 OFF, LDO13 OFF
+ */
+ val = 0x50;
+ ret |= pmic_reg_write(p, MAX8998_REG_ONOFF2, val);
+
+ /* ONOFF3
+ * LDO14 OFF, LDO15 OFF, LGO16 OFF, LDO17 OFF
+ * EPWRHOLD OFF, EBATTMON OFF, ELBCNFG2 OFF, ELBCNFG1 OFF
+ */
+ val = 0x00;
+ ret |= pmic_reg_write(p, MAX8998_REG_ONOFF3, val);
+
+ if (ret)
+ puts("LCD pmic initialisation error!\n");
+}
+
+static void lcd_cfg_gpio(void)
+{
+ unsigned int i, f3_end = 4;
+
+ for (i = 0; i < 8; i++) {
+ /* set GPF0,1,2[0:7] for RGB Interface and Data lines (32bit) */
+ s5p_gpio_cfg_pin(&gpio1->f0, i, GPIO_FUNC(2));
+ s5p_gpio_cfg_pin(&gpio1->f1, i, GPIO_FUNC(2));
+ s5p_gpio_cfg_pin(&gpio1->f2, i, GPIO_FUNC(2));
+ /* pull-up/down disable */
+ s5p_gpio_set_pull(&gpio1->f0, i, GPIO_PULL_NONE);
+ s5p_gpio_set_pull(&gpio1->f1, i, GPIO_PULL_NONE);
+ s5p_gpio_set_pull(&gpio1->f2, i, GPIO_PULL_NONE);
+
+ /* drive strength to max (24bit) */
+ s5p_gpio_set_drv(&gpio1->f0, i, GPIO_DRV_4X);
+ s5p_gpio_set_rate(&gpio1->f0, i, GPIO_DRV_SLOW);
+ s5p_gpio_set_drv(&gpio1->f1, i, GPIO_DRV_4X);
+ s5p_gpio_set_rate(&gpio1->f1, i, GPIO_DRV_SLOW);
+ s5p_gpio_set_drv(&gpio1->f2, i, GPIO_DRV_4X);
+ s5p_gpio_set_rate(&gpio1->f0, i, GPIO_DRV_SLOW);
+ }
+
+ for (i = 0; i < f3_end; i++) {
+ /* set GPF3[0:3] for RGB Interface and Data lines (32bit) */
+ s5p_gpio_cfg_pin(&gpio1->f3, i, GPIO_FUNC(2));
+ /* pull-up/down disable */
+ s5p_gpio_set_pull(&gpio1->f3, i, GPIO_PULL_NONE);
+ /* drive strength to max (24bit) */
+ s5p_gpio_set_drv(&gpio1->f3, i, GPIO_DRV_4X);
+ s5p_gpio_set_rate(&gpio1->f3, i, GPIO_DRV_SLOW);
+ }
+
+ /* gpio pad configuration for LCD reset. */
+ s5p_gpio_cfg_pin(&gpio2->y4, 5, GPIO_OUTPUT);
+
+ spi_init();
+}
+
+static void reset_lcd(void)
+{
+ s5p_gpio_set_value(&gpio2->y4, 5, 1);
+ udelay(10000);
+ s5p_gpio_set_value(&gpio2->y4, 5, 0);
+ udelay(10000);
+ s5p_gpio_set_value(&gpio2->y4, 5, 1);
+ udelay(100);
+}
+
+static void lcd_power_on(void)
+{
+ struct pmic *p = pmic_get("MAX8998_PMIC");
+
+ if (!p)
+ return;
+
+ if (pmic_probe(p))
+ return;
+
+ pmic_set_output(p, MAX8998_REG_ONOFF3, MAX8998_LDO17, LDO_ON);
+ pmic_set_output(p, MAX8998_REG_ONOFF2, MAX8998_LDO7, LDO_ON);
+}
+
+vidinfo_t panel_info = {
+ .vl_freq = 60,
+ .vl_col = 480,
+ .vl_row = 800,
+ .vl_width = 480,
+ .vl_height = 800,
+ .vl_clkp = CONFIG_SYS_HIGH,
+ .vl_hsp = CONFIG_SYS_HIGH,
+ .vl_vsp = CONFIG_SYS_HIGH,
+ .vl_dp = CONFIG_SYS_HIGH,
+
+ .vl_bpix = 5, /* Bits per pixel */
+
+ /* LD9040 LCD Panel */
+ .vl_hspw = 2,
+ .vl_hbpd = 16,
+ .vl_hfpd = 16,
+
+ .vl_vspw = 2,
+ .vl_vbpd = 8,
+ .vl_vfpd = 8,
+ .vl_cmd_allow_len = 0xf,
+
+ .win_id = 0,
+ .cfg_gpio = lcd_cfg_gpio,
+ .backlight_on = NULL,
+ .lcd_power_on = lcd_power_on,
+ .reset_lcd = reset_lcd,
+ .dual_lcd_enabled = 0,
+
+ .init_delay = 0,
+ .power_on_delay = 10000,
+ .reset_delay = 10000,
+ .interface_mode = FIMD_RGB_INTERFACE,
+ .mipi_enabled = 0,
+};
+
+void init_panel_info(vidinfo_t *vid)
+{
+ vid->logo_on = 1;
+ vid->resolution = HD_RESOLUTION;
+ vid->rgb_mode = MODE_RGB_P;
+
+#ifdef CONFIG_TIZEN
+ get_tizen_logo_info(vid);
+#endif
+
+ /* for LD9040. */
+ vid->pclk_name = 1; /* MPLL */
+ vid->sclk_div = 1;
+
+ vid->cfg_ldo = ld9040_cfg_ldo;
+ vid->enable_ldo = ld9040_enable_ldo;
+
+ setenv("lcdinfo", "lcd=ld9040");
+}
+
+int board_init(void)
+{
+ gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE;
+ gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE;
+
+ gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210;
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+#ifdef CONFIG_SOFT_SPI
+ soft_spi_init();
+#endif
+ check_hw_revision();
+ printf("HW Revision:\t0x%x\n", board_rev);
+
+ return 0;
+}
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/imx25-pinmux.h>
+#include <asm/arch/sys_proto.h>
DECLARE_GLOBAL_DATA_PTR;
return 0;
}
+#ifndef CONFIG_SPL_BUILD
int misc_init_r(void)
{
char *eth_addr;
+ struct tam3517_module_info info;
+ int ret;
dieid_num_r();
if (eth_addr)
return 0;
-#ifndef CONFIG_SPL_BUILD
- TAM3517_READ_MAC_FROM_EEPROM;
-#endif
+ TAM3517_READ_EEPROM(&info, ret);
+ if (!ret)
+ TAM3517_READ_MAC_FROM_EEPROM(&info);
return 0;
}
+#endif
/*
* Routine: set_muxconf_regs
static struct panel_config lcd_cfg[] = {
{
- .timing_h = PANEL_TIMING_H(4, 8, 41),
- .timing_v = PANEL_TIMING_V(2, 4, 10),
- .pol_freq = 0x00000000, /* Pol Freq */
- .divisor = 0x0001000d, /* 33Mhz Pixel Clock */
+ .timing_h = PANEL_TIMING_H(40, 5, 2),
+ .timing_v = PANEL_TIMING_V(8, 8, 2),
+ .pol_freq = 0x00003000, /* Pol Freq */
+ .divisor = 0x00010033, /* 9 Mhz Pixel Clock */
.panel_type = 0x01, /* TFT */
.data_lines = 0x03, /* 24 Bit RGB */
.load_mode = 0x02, /* Frame Mode */
return 0;
}
+#ifndef CONFIG_SPL_BUILD
int misc_init_r(void)
{
char *eth_addr;
+ struct tam3517_module_info info;
+ int ret;
+ TAM3517_READ_EEPROM(&info, ret);
dieid_num_r();
- eth_addr = getenv("ethaddr");
- if (eth_addr)
+ if (ret)
return 0;
+ eth_addr = getenv("ethaddr");
+ if (!eth_addr)
+ TAM3517_READ_MAC_FROM_EEPROM(&info);
-#ifndef CONFIG_SPL_BUILD
- TAM3517_READ_MAC_FROM_EEPROM;
-#endif
+ TAM3517_PRINT_SOM_INFO(&info);
return 0;
}
+#endif
/*
* Routine: set_muxconf_regs
/* MII mode defines */
#define MII_MODE_ENABLE 0x0
-#define RGMII_MODE_ENABLE 0xA
+#define RGMII_MODE_ENABLE 0x3A
/* GPIO that controls power to DDR on EVM-SK */
#define GPIO_DDR_VTT_EN 7
gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
+ gpmc_init();
+
return 0;
}
{-1},
};
+static struct module_pin_mux nand_pin_mux[] = {
+ {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
+ {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
+ {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
+ {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
+ {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
+ {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
+ {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
+ {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
+ {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
+ {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
+ {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
+ {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
+ {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
+ {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
+ {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
+ {-1},
+};
+
void enable_uart0_pin_mux(void)
{
configure_module_pin_mux(uart0_pin_mux);
/* In profile #2 i2c1 and spi0 conflict. */
if (profile & ~PROFILE_2)
configure_module_pin_mux(i2c1_pin_mux);
+ /* Profiles 2 & 3 don't have NAND */
+ if (profile & ~(PROFILE_2 | PROFILE_3))
+ configure_module_pin_mux(nand_pin_mux);
else if (profile == PROFILE_2) {
configure_module_pin_mux(mmc1_pin_mux);
configure_module_pin_mux(spi0_pin_mux);
* Description: If we use SPL then there is no x-loader nor config header
* so we have to setup the DDR timings ourself on both banks.
*/
-void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
- u32 *mr)
+void get_board_mem_timings(struct board_sdrc_timings *timings)
{
int pop_mfr, pop_id;
*/
identify_nand_chip(&pop_mfr, &pop_id);
- *mr = MICRON_V_MR_165;
+ timings->mr = MICRON_V_MR_165;
switch (get_board_revision()) {
case REVISION_C4:
if (pop_mfr == NAND_MFR_STMICRO && pop_id == 0xba) {
/* 512MB DDR */
- *mcfg = NUMONYX_V_MCFG_165(512 << 20);
- *ctrla = NUMONYX_V_ACTIMA_165;
- *ctrlb = NUMONYX_V_ACTIMB_165;
- *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+ timings->mcfg = NUMONYX_V_MCFG_165(512 << 20);
+ timings->ctrla = NUMONYX_V_ACTIMA_165;
+ timings->ctrlb = NUMONYX_V_ACTIMB_165;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
break;
} else if (pop_mfr == NAND_MFR_MICRON && pop_id == 0xba) {
/* Beagleboard Rev C4, 512MB Nand/256MB DDR*/
- *mcfg = MICRON_V_MCFG_165(128 << 20);
- *ctrla = MICRON_V_ACTIMA_165;
- *ctrlb = MICRON_V_ACTIMB_165;
- *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+ timings->mcfg = MICRON_V_MCFG_165(128 << 20);
+ timings->ctrla = MICRON_V_ACTIMA_165;
+ timings->ctrlb = MICRON_V_ACTIMB_165;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
break;
} else if (pop_mfr == NAND_MFR_MICRON && pop_id == 0xbc) {
/* Beagleboard Rev C5, 256MB DDR */
- *mcfg = MICRON_V_MCFG_200(256 << 20);
- *ctrla = MICRON_V_ACTIMA_200;
- *ctrlb = MICRON_V_ACTIMB_200;
- *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+ timings->mcfg = MICRON_V_MCFG_200(256 << 20);
+ timings->ctrla = MICRON_V_ACTIMA_200;
+ timings->ctrlb = MICRON_V_ACTIMB_200;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
break;
}
case REVISION_XM_A:
case REVISION_XM_C:
if (pop_mfr == 0) {
/* 256MB DDR */
- *mcfg = MICRON_V_MCFG_200(256 << 20);
- *ctrla = MICRON_V_ACTIMA_200;
- *ctrlb = MICRON_V_ACTIMB_200;
- *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+ timings->mcfg = MICRON_V_MCFG_200(256 << 20);
+ timings->ctrla = MICRON_V_ACTIMA_200;
+ timings->ctrlb = MICRON_V_ACTIMB_200;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
} else {
/* 512MB DDR */
- *mcfg = NUMONYX_V_MCFG_165(512 << 20);
- *ctrla = NUMONYX_V_ACTIMA_165;
- *ctrlb = NUMONYX_V_ACTIMB_165;
- *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+ timings->mcfg = NUMONYX_V_MCFG_165(512 << 20);
+ timings->ctrla = NUMONYX_V_ACTIMA_165;
+ timings->ctrlb = NUMONYX_V_ACTIMB_165;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
}
break;
default:
/* Assume 128MB and Micron/165MHz timings to be safe */
- *mcfg = MICRON_V_MCFG_165(128 << 20);
- *ctrla = MICRON_V_ACTIMA_165;
- *ctrlb = MICRON_V_ACTIMB_165;
- *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+ timings->mcfg = MICRON_V_MCFG_165(128 << 20);
+ timings->ctrla = MICRON_V_ACTIMA_165;
+ timings->ctrlb = MICRON_V_ACTIMB_165;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
}
}
#endif
* provides the timing values back to the function that configures
* the memory.
*/
-void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
- u32 *mr)
+void get_board_mem_timings(struct board_sdrc_timings *timings)
{
int pop_mfr, pop_id;
if (pop_mfr == NAND_MFR_HYNIX && pop_id == 0xbc) {
/* 256MB DDR */
- *mcfg = HYNIX_V_MCFG_200(256 << 20);
- *ctrla = HYNIX_V_ACTIMA_200;
- *ctrlb = HYNIX_V_ACTIMB_200;
+ timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
+ timings->ctrla = HYNIX_V_ACTIMA_200;
+ timings->ctrlb = HYNIX_V_ACTIMB_200;
} else {
/* 128MB DDR */
- *mcfg = MICRON_V_MCFG_165(128 << 20);
- *ctrla = MICRON_V_ACTIMA_165;
- *ctrlb = MICRON_V_ACTIMB_165;
+ timings->mcfg = MICRON_V_MCFG_165(128 << 20);
+ timings->ctrla = MICRON_V_ACTIMA_165;
+ timings->ctrlb = MICRON_V_ACTIMB_165;
}
- *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
- *mr = MICRON_V_MR_165;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+ timings->mr = MICRON_V_MR_165;
}
#endif
* provides the timing values back to the function that configures
* the memory. We have either one or two banks of 128MB DDR.
*/
-void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
- u32 *mr)
+void get_board_mem_timings(struct board_sdrc_timings *timings)
{
/* General SDRC config */
- *mcfg = MICRON_V_MCFG_165(128 << 20);
- *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+ timings->mcfg = MICRON_V_MCFG_165(128 << 20);
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
/* AC timings */
- *ctrla = MICRON_V_ACTIMA_165;
- *ctrlb = MICRON_V_ACTIMB_165;
+ timings->ctrla = MICRON_V_ACTIMA_165;
+ timings->ctrlb = MICRON_V_ACTIMB_165;
- *mr = MICRON_V_MR_165;
+ timings->mr = MICRON_V_MR_165;
}
--- /dev/null
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := woodburn.o
+SOBJS := lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+BOOT_FROM sd
+
+# DDR2 init
+DATA 4 0xB8001010 0x00000304
--- /dev/null
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Copyright (C) 2011, Stefano Babic <sbabic@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/lowlevel_macro.S>
+
+.globl lowlevel_init
+lowlevel_init:
+
+ core_init
+
+ init_aips
+
+ init_max
+
+ init_m3if
+
+ mov pc, lr
--- /dev/null
+/*
+ * Copyright (C) 2012, Stefano Babic <sbabic@denx.de>
+ *
+ * Based on flea3.c and mx35pdk.c
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/mx35_pins.h>
+#include <asm/arch/iomux.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <fsl_pmic.h>
+#include <mc13892.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <linux/types.h>
+#include <asm/gpio.h>
+#include <asm/arch/sys_proto.h>
+#include <netdev.h>
+#include <spl.h>
+
+#define CCM_CCMR_CONFIG 0x003F4208
+
+#define ESDCTL_DDR2_CONFIG 0x007FFC3F
+
+/* For MMC */
+#define GPIO_MMC_CD 7
+#define GPIO_MMC_WP 8
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
+ PHYS_SDRAM_1_SIZE);
+
+ return 0;
+}
+
+static void board_setup_sdram(void)
+{
+ struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
+
+ /* Initialize with default values both CSD0/1 */
+ writel(0x2000, &esdc->esdctl0);
+ writel(0x2000, &esdc->esdctl1);
+
+ mx3_setup_sdram_bank(CSD0_BASE_ADDR, ESDCTL_DDR2_CONFIG,
+ 13, 10, 2, 0x8080);
+}
+
+static void setup_iomux_fec(void)
+{
+ /* setup pins for FEC */
+ mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RDATA0, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TX_ERR, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RX_ERR, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_CRS, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RDATA1, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TDATA1, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RDATA2, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TDATA2, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RDATA3, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TDATA3, MUX_CONFIG_FUNC);
+}
+
+int woodburn_init(void)
+{
+ struct ccm_regs *ccm =
+ (struct ccm_regs *)IMX_CCM_BASE;
+
+ /* initialize PLL and clock configuration */
+ writel(CCM_CCMR_CONFIG, &ccm->ccmr);
+
+ /* Set-up RAM */
+ board_setup_sdram();
+
+ /* enable clocks */
+ writel(readl(&ccm->cgr0) |
+ MXC_CCM_CGR0_EMI_MASK |
+ MXC_CCM_CGR0_EDIO_MASK |
+ MXC_CCM_CGR0_EPIT1_MASK,
+ &ccm->cgr0);
+
+ writel(readl(&ccm->cgr1) |
+ MXC_CCM_CGR1_FEC_MASK |
+ MXC_CCM_CGR1_GPIO1_MASK |
+ MXC_CCM_CGR1_GPIO2_MASK |
+ MXC_CCM_CGR1_GPIO3_MASK |
+ MXC_CCM_CGR1_I2C1_MASK |
+ MXC_CCM_CGR1_I2C2_MASK |
+ MXC_CCM_CGR1_I2C3_MASK,
+ &ccm->cgr1);
+
+ /* Set-up NAND */
+ __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
+
+ /* Set pinmux for the required peripherals */
+ setup_iomux_fec();
+
+ /* setup GPIO1_4 FEC_ENABLE signal */
+ mxc_request_iomux(MX35_PIN_SCKR, MUX_CONFIG_ALT5);
+ gpio_direction_output(4, 1);
+ mxc_request_iomux(MX35_PIN_HCKT, MUX_CONFIG_ALT5);
+ gpio_direction_output(9, 1);
+
+ return 0;
+}
+
+#if defined(CONFIG_SPL_BUILD)
+void board_init_f(ulong dummy)
+{
+ /* Set the stack pointer. */
+ asm volatile("mov sp, %0\n" : : "r"(CONFIG_SPL_STACK));
+
+ /* Initialize MUX and SDRAM */
+ woodburn_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end__ - __bss_start);
+
+ /* Set global data pointer. */
+ gd = &gdata;
+
+ preloader_console_init();
+ timer_init();
+
+ board_init_r(NULL, 0);
+}
+
+void spl_board_init(void)
+{
+}
+
+#endif
+
+
+/* Booting from NOR in external mode */
+int board_early_init_f(void)
+{
+ return woodburn_init();
+}
+
+
+int board_init(void)
+{
+ struct pmic *p;
+ u32 val;
+ int ret;
+
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ ret = pmic_init(I2C_PMIC);
+ if (ret)
+ return ret;
+
+ p = pmic_get("FSL_PMIC");
+
+ /*
+ * Set switchers in Auto in NORMAL mode & STANDBY mode
+ * Setup the switcher mode for SW1 & SW2
+ */
+ pmic_reg_read(p, REG_SW_4, &val);
+ val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
+ (SWMODE_MASK << SWMODE2_SHIFT)));
+ val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
+ (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
+ /* Set SWILIMB */
+ val |= (1 << 22);
+ pmic_reg_write(p, REG_SW_4, val);
+
+ /* Setup the switcher mode for SW3 & SW4 */
+ pmic_reg_read(p, REG_SW_5, &val);
+ val &= ~((SWMODE_MASK << SWMODE4_SHIFT) |
+ (SWMODE_MASK << SWMODE3_SHIFT));
+ val |= (SWMODE_AUTO_AUTO << SWMODE4_SHIFT) |
+ (SWMODE_AUTO_AUTO << SWMODE3_SHIFT);
+ pmic_reg_write(p, REG_SW_5, val);
+
+ /* Set VGEN1 to 3.15V */
+ pmic_reg_read(p, REG_SETTING_0, &val);
+ val &= ~(VGEN1_MASK);
+ val |= VGEN1_3_15;
+ pmic_reg_write(p, REG_SETTING_0, val);
+
+ pmic_reg_read(p, REG_MODE_0, &val);
+ val |= VGEN1EN;
+ pmic_reg_write(p, REG_MODE_0, val);
+ udelay(2000);
+
+ return 0;
+}
+
+#if defined(CONFIG_FSL_ESDHC)
+struct fsl_esdhc_cfg esdhc_cfg = {MMC_SDHC1_BASE_ADDR};
+
+int board_mmc_init(bd_t *bis)
+{
+ /* configure pins for SDHC1 only */
+ mxc_request_iomux(MX35_PIN_SD1_CMD, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_SD1_CLK, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_SD1_DATA0, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_SD1_DATA1, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_SD1_DATA2, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_SD1_DATA3, MUX_CONFIG_FUNC);
+
+ /* MMC Card Detect on GPIO1_7 */
+ mxc_request_iomux(MX35_PIN_SCKT, MUX_CONFIG_ALT5);
+ mxc_iomux_set_input(MUX_IN_GPIO1_IN_7, 0x1);
+ gpio_direction_input(GPIO_MMC_CD);
+
+ mxc_request_iomux(MX35_PIN_FST, MUX_CONFIG_ALT5);
+ mxc_iomux_set_input(MUX_IN_GPIO1_IN_8, 0x1);
+ gpio_direction_output(GPIO_MMC_WP, 0);
+
+ esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
+
+ return fsl_esdhc_initialize(bis, &esdhc_cfg);
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ return !gpio_get_value(GPIO_MMC_CD);
+}
+#endif
+
+u32 get_board_rev(void)
+{
+ int rev = 0;
+
+ return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
+}
imx31_litekit arm arm1136 - logicpd mx31
flea3 arm arm1136 - CarMediaLab mx35
mx35pdk arm arm1136 - freescale mx35
+woodburn arm arm1136 - - mx35
+woodburn_sd arm arm1136 woodburn - mx35 woodburn_sd:IMX_CONFIG=board/woodburn/imximage.cfg
omap2420h4 arm arm1136 - ti omap24xx
tnetv107x_evm arm arm1176 tnetv107xevm ti tnetv107x
rpi_b arm arm1176 rpi_b raspberrypi bcm2835
at91sam9rlek_dataflash arm arm926ejs at91sam9rlek atmel at91 at91sam9rlek:AT91SAM9RL,SYS_USE_DATAFLASH
at91sam9rlek_nandflash arm arm926ejs at91sam9rlek atmel at91 at91sam9rlek:AT91SAM9RL,SYS_USE_NANDFLASH
at91sam9x5ek_nandflash arm arm926ejs at91sam9x5ek atmel at91 at91sam9x5ek:AT91SAM9X5,SYS_USE_NANDFLASH
+at91sam9x5ek_dataflash arm arm926ejs at91sam9x5ek atmel at91 at91sam9x5ek:AT91SAM9X5,SYS_USE_DATAFLASH
at91sam9x5ek_spiflash arm arm926ejs at91sam9x5ek atmel at91 at91sam9x5ek:AT91SAM9X5,SYS_USE_SPIFLASH
at91sam9x5ek_mmc arm arm926ejs at91sam9x5ek atmel at91 at91sam9x5ek:AT91SAM9X5,SYS_USE_MMC
at91sam9xeek_dataflash_cs0 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS0
netspace_max_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:NETSPACE_MAX_V2
netspace_mini_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:NETSPACE_MINI_V2
netspace_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:NETSPACE_V2
+wireless_space arm arm926ejs wireless_space LaCie kirkwood
dreamplug arm arm926ejs - Marvell kirkwood
guruplug arm arm926ejs - Marvell kirkwood
mv88f6281gtw_ge arm arm926ejs - Marvell kirkwood
M5235EVB_Flash32 m68k mcf523x m5235evb freescale - M5235EVB:NORFLASH_PS32BIT,SYS_TEXT_BASE=0xFFC00000
cobra5272 m68k mcf52x2 cobra5272 -
idmr m68k mcf52x2
-eb_cpu5282 m68k mcf52x2 eb_cpu5282 BuS - eb_cpu5282:SYS_TEXT_BASE=0xFF000000
-eb_cpu5282_internal m68k mcf52x2 eb_cpu5282 BuS - eb_cpu5282:SYS_TEXT_BASE=0xF0000000
+eb_cpu5282 m68k mcf52x2 eb_cpu5282 BuS - eb_cpu5282:SYS_TEXT_BASE=0xFF000000,SYS_MONITOR_BASE=0xFF000400
+eb_cpu5282_internal m68k mcf52x2 eb_cpu5282 BuS - eb_cpu5282:SYS_TEXT_BASE=0xF0000000,SYS_MONITOR_BASE=0xF0000418
TASREG m68k mcf52x2 tasreg esd
M5208EVBE m68k mcf52x2 m5208evbe freescale
M5249EVB m68k mcf52x2 m5249evb freescale
MigoR sh sh4 MigoR renesas -
r2dplus sh sh4 r2dplus renesas -
r7780mp sh sh4 r7780mp renesas -
+sh7752evb sh sh4 sh7752evb renesas -
sh7757lcr sh sh4 sh7757lcr renesas -
sh7763rdp sh sh4 sh7763rdp renesas -
sh7785lcr sh sh4 sh7785lcr renesas -
COBJS-$(CONFIG_CMD_CPLBINFO) += cmd_cplbinfo.o
COBJS-$(CONFIG_DATAFLASH_MMC_SELECT) += cmd_dataflash_mmc_mux.o
COBJS-$(CONFIG_CMD_DATE) += cmd_date.o
+COBJS-$(CONFIG_CMD_SOUND) += cmd_sound.o
ifdef CONFIG_4xx
COBJS-$(CONFIG_CMD_SETGETDCR) += cmd_dcr.o
endif
#ifdef CONFIG_NEEDS_MANUAL_RELOC
static int relocated = 0;
- /* relocate boot function table */
if (!relocated) {
int i;
+
+ /* relocate boot function table */
for (i = 0; i < ARRAY_SIZE(boot_os); i++)
if (boot_os[i] != NULL)
boot_os[i] += gd->reloc_off;
+
+ /* relocate names of sub-command table */
+ for (i = 0; i < ARRAY_SIZE(cmd_bootm_sub); i++)
+ cmd_bootm_sub[i].name += gd->reloc_off;
+
relocated = 1;
}
#endif
#include <dataflash.h>
#endif
#include <watchdog.h>
+#include <linux/compiler.h>
+
+DECLARE_GLOBAL_DATA_PTR;
static int mod_mem(cmd_tbl_t *, int, int, int, char * const []);
#endif
+#ifdef CONFIG_CMD_MEMINFO
+__weak void board_show_dram(ulong size)
+{
+ puts("DRAM: ");
+ print_size(size, "\n");
+}
+
+static int do_mem_info(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ board_show_dram(gd->ram_size);
+
+ return 0;
+}
+#endif
+
U_BOOT_CMD(
base, 2, 1, do_mem_base,
"print or set address offset",
"[.b, .w, .l] address value delay(ms)"
);
#endif /* CONFIG_MX_CYCLIC */
+
+#ifdef CONFIG_CMD_MEMINFO
+U_BOOT_CMD(
+ meminfo, 3, 1, do_mem_info,
+ "display memory information",
+ ""
+);
+#endif
int w;
/* Validate arguments */
- if ((argc != 5) || (strlen(argv[3]) != 1))
+ if (argc != 5 && argc != 3)
+ return CMD_RET_USAGE;
+ if (argc == 5 && strlen(argv[3]) != 1)
return CMD_RET_USAGE;
w = cmd_get_data_size(argv[0], 4);
a = get_arg(argv[2], w);
+
+ if (argc == 3) {
+ sprintf(buf, "%lx", a);
+ setenv(argv[1], buf);
+
+ return 0;
+ }
+
b = get_arg(argv[4], w);
switch (argv[3][0]) {
U_BOOT_CMD(
setexpr, 5, 0, do_setexpr,
"set environment variable as the result of eval expression",
- "[.b, .w, .l] name value1 <op> value2\n"
+ "[.b, .w, .l] name [*]value1 <op> [*]value2\n"
" - set environment variable 'name' to the result of the evaluated\n"
" express specified by <op>. <op> can be &, |, ^, +, -, *, /, %\n"
- " size argument is only meaningful if value1 and/or value2 are memory addresses"
+ " size argument is only meaningful if value1 and/or value2 are\n"
+ " memory addresses (*)\n"
+ "setexpr[.b, .w, .l] name *value\n"
+ " - load a memory address into a variable"
);
* Licensed under the GPL-2 or later.
*/
+#include <div64.h>
#include <common.h>
#include <malloc.h>
#include <spi_flash.h>
return 1;
}
+/**
+ * This function takes a byte length and a delta unit of time to compute the
+ * approximate bytes per second
+ *
+ * @param len amount of bytes currently processed
+ * @param start_ms start time of processing in ms
+ * @return bytes per second if OK, 0 on error
+ */
+static ulong bytes_per_second(unsigned int len, ulong start_ms)
+{
+ /* less accurate but avoids overflow */
+ if (len >= ((unsigned int) -1) / 1024)
+ return len / (max(get_timer(start_ms) / 1024, 1));
+ else
+ return 1024 * len / max(get_timer(start_ms), 1);
+}
+
static int do_spi_flash_probe(int argc, char * const argv[])
{
unsigned int bus = CONFIG_SF_DEFAULT_BUS;
const char *end = buf + len;
size_t todo; /* number of bytes to do in this pass */
size_t skipped = 0; /* statistics */
+ const ulong start_time = get_timer(0);
+ size_t scale = 1;
+ const char *start_buf = buf;
+ ulong delta;
+ if (end - buf >= 200)
+ scale = (end - buf) / 100;
cmp_buf = malloc(flash->sector_size);
if (cmp_buf) {
+ ulong last_update = get_timer(0);
+
for (; buf < end && !err_oper; buf += todo, offset += todo) {
todo = min(end - buf, flash->sector_size);
+ if (get_timer(last_update) > 100) {
+ printf(" \rUpdating, %zu%% %lu B/s",
+ 100 - (end - buf) / scale,
+ bytes_per_second(buf - start_buf,
+ start_time));
+ last_update = get_timer(0);
+ }
err_oper = spi_flash_update_block(flash, offset, todo,
buf, cmp_buf, &skipped);
}
err_oper = "malloc";
}
free(cmp_buf);
+ putc('\r');
if (err_oper) {
printf("SPI flash failed in %s step\n", err_oper);
return 1;
}
- printf("%zu bytes written, %zu bytes skipped\n", len - skipped,
- skipped);
+
+ delta = get_timer(start_time);
+ printf("%zu bytes written, %zu bytes skipped", len - skipped,
+ skipped);
+ printf(" in %ld.%lds, speed %ld B/s\n",
+ delta / 1000, delta % 1000, bytes_per_second(len, start_time));
return 0;
}
return 0;
}
+#ifdef CONFIG_CMD_SF_TEST
+enum {
+ STAGE_ERASE,
+ STAGE_CHECK,
+ STAGE_WRITE,
+ STAGE_READ,
+
+ STAGE_COUNT,
+};
+
+static char *stage_name[STAGE_COUNT] = {
+ "erase",
+ "check",
+ "write",
+ "read",
+};
+
+struct test_info {
+ int stage;
+ int bytes;
+ unsigned base_ms;
+ unsigned time_ms[STAGE_COUNT];
+};
+
+static void show_time(struct test_info *test, int stage)
+{
+ uint64_t speed; /* KiB/s */
+ int bps; /* Bits per second */
+
+ speed = (long long)test->bytes * 1000;
+ do_div(speed, test->time_ms[stage] * 1024);
+ bps = speed * 8;
+
+ printf("%d %s: %d ticks, %d KiB/s %d.%03d Mbps\n", stage,
+ stage_name[stage], test->time_ms[stage],
+ (int)speed, bps / 1000, bps % 1000);
+}
+
+static void spi_test_next_stage(struct test_info *test)
+{
+ test->time_ms[test->stage] = get_timer(test->base_ms);
+ show_time(test, test->stage);
+ test->base_ms = get_timer(0);
+ test->stage++;
+}
+
+/**
+ * Run a test on the SPI flash
+ *
+ * @param flash SPI flash to use
+ * @param buf Source buffer for data to write
+ * @param len Size of data to read/write
+ * @param offset Offset within flash to check
+ * @param vbuf Verification buffer
+ * @return 0 if ok, -1 on error
+ */
+static int spi_flash_test(struct spi_flash *flash, char *buf, ulong len,
+ ulong offset, char *vbuf)
+{
+ struct test_info test;
+ int i;
+
+ printf("SPI flash test:\n");
+ memset(&test, '\0', sizeof(test));
+ test.base_ms = get_timer(0);
+ test.bytes = len;
+ if (spi_flash_erase(flash, offset, len)) {
+ printf("Erase failed\n");
+ return -1;
+ }
+ spi_test_next_stage(&test);
+
+ if (spi_flash_read(flash, offset, len, vbuf)) {
+ printf("Check read failed\n");
+ return -1;
+ }
+ for (i = 0; i < len; i++) {
+ if (vbuf[i] != 0xff) {
+ printf("Check failed at %d\n", i);
+ print_buffer(i, vbuf + i, 1, min(len - i, 0x40), 0);
+ return -1;
+ }
+ }
+ spi_test_next_stage(&test);
+
+ if (spi_flash_write(flash, offset, len, buf)) {
+ printf("Write failed\n");
+ return -1;
+ }
+ memset(vbuf, '\0', len);
+ spi_test_next_stage(&test);
+
+ if (spi_flash_read(flash, offset, len, vbuf)) {
+ printf("Read failed\n");
+ return -1;
+ }
+ spi_test_next_stage(&test);
+
+ for (i = 0; i < len; i++) {
+ if (buf[i] != vbuf[i]) {
+ printf("Verify failed at %d, good data:\n", i);
+ print_buffer(i, buf + i, 1, min(len - i, 0x40), 0);
+ printf("Bad data:\n");
+ print_buffer(i, vbuf + i, 1, min(len - i, 0x40), 0);
+ return -1;
+ }
+ }
+ printf("Test passed\n");
+ for (i = 0; i < STAGE_COUNT; i++)
+ show_time(&test, i);
+
+ return 0;
+}
+
+static int do_spi_flash_test(int argc, char * const argv[])
+{
+ unsigned long offset;
+ unsigned long len;
+ char *buf = (char *)CONFIG_SYS_TEXT_BASE;
+ char *endp;
+ char *vbuf;
+ int ret;
+
+ offset = simple_strtoul(argv[1], &endp, 16);
+ if (*argv[1] == 0 || *endp != 0)
+ return -1;
+ len = simple_strtoul(argv[2], &endp, 16);
+ if (*argv[2] == 0 || *endp != 0)
+ return -1;
+
+ vbuf = malloc(len);
+ if (!vbuf) {
+ printf("Cannot allocate memory\n");
+ return 1;
+ }
+ buf = malloc(len);
+ if (!buf) {
+ free(vbuf);
+ printf("Cannot allocate memory\n");
+ return 1;
+ }
+
+ memcpy(buf, (char *)CONFIG_SYS_TEXT_BASE, len);
+ ret = spi_flash_test(flash, buf, len, offset, vbuf);
+ free(vbuf);
+ free(buf);
+ if (ret) {
+ printf("Test failed\n");
+ return 1;
+ }
+
+ return 0;
+}
+#endif /* CONFIG_CMD_SF_TEST */
+
static int do_spi_flash(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
const char *cmd;
ret = do_spi_flash_read_write(argc, argv);
else if (strcmp(cmd, "erase") == 0)
ret = do_spi_flash_erase(argc, argv);
+#ifdef CONFIG_CMD_SF_TEST
+ else if (!strcmp(cmd, "test"))
+ ret = do_spi_flash_test(argc, argv);
+#endif
else
ret = -1;
return CMD_RET_USAGE;
}
+#ifdef CONFIG_CMD_SF_TEST
+#define SF_TEST_HELP "\nsf test offset len " \
+ "- run a very basic destructive test"
+#else
+#define SF_TEST_HELP
+#endif
+
U_BOOT_CMD(
sf, 5, 1, do_spi_flash,
"SPI flash sub-system",
" `+len' round up `len' to block size\n"
"sf update addr offset len - erase and write `len' bytes from memory\n"
" at `addr' to flash at `offset'"
+ SF_TEST_HELP
);
--- /dev/null
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ * Rajeshwari Shinde <rajeshwari.s@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <fdtdec.h>
+#include <sound.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Initilaise sound subsystem */
+static int do_init(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ int ret;
+
+ ret = sound_init(gd->fdt_blob);
+ if (ret) {
+ printf("Initialise Audio driver failed\n");
+ return CMD_RET_FAILURE;
+ }
+
+ return 0;
+}
+
+/* play sound from buffer */
+static int do_play(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ int ret = 0;
+ int msec = 1000;
+ int freq = 400;
+
+ if (argc > 1)
+ msec = simple_strtoul(argv[1], NULL, 10);
+ if (argc > 2)
+ freq = simple_strtoul(argv[2], NULL, 10);
+
+ ret = sound_play(msec, freq);
+ if (ret) {
+ printf("play failed");
+ return CMD_RET_FAILURE;
+ }
+
+ return 0;
+}
+
+static cmd_tbl_t cmd_sound_sub[] = {
+ U_BOOT_CMD_MKENT(init, 0, 1, do_init, "", ""),
+ U_BOOT_CMD_MKENT(play, 2, 1, do_play, "", ""),
+};
+
+/* process sound command */
+static int do_sound(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ cmd_tbl_t *c;
+
+ if (argc < 1)
+ return CMD_RET_USAGE;
+
+ /* Strip off leading 'sound' command argument */
+ argc--;
+ argv++;
+
+ c = find_cmd_tbl(argv[0], &cmd_sound_sub[0], ARRAY_SIZE(cmd_sound_sub));
+
+ if (c)
+ return c->cmd(cmdtp, flag, argc, argv);
+ else
+ return CMD_RET_USAGE;
+}
+
+U_BOOT_CMD(
+ sound, 4, 1, do_sound,
+ "sound sub-system",
+ "init - initialise the sound driver\n"
+ "sound play [len] [freq] - play a sound for len ms at freq hz\n"
+);
#include <command.h>
#include <version.h>
#include <linux/compiler.h>
+#ifdef CONFIG_SYS_COREBOOT
+#include <asm/arch/sysinfo.h>
+#endif
const char __weak version_string[] = U_BOOT_VERSION_STRING;
#ifdef LD_VERSION_STRING
puts(LD_VERSION_STRING "\n");
#endif
-
+#ifdef CONFIG_SYS_COREBOOT
+ printf("coreboot-%s (%s)\n", lib_sysinfo.version, lib_sysinfo.build);
+#endif
return 0;
}
# endif
#endif
+#ifndef CONFIG_LCD_ALIGNMENT
+#define CONFIG_LCD_ALIGNMENT PAGE_SIZE
+#endif
+
+/* By default we scroll by a single line */
+#ifndef CONFIG_CONSOLE_SCROLL_LINES
+#define CONFIG_CONSOLE_SCROLL_LINES 1
+#endif
+
DECLARE_GLOBAL_DATA_PTR;
ulong lcd_setmem (ulong addr);
char lcd_is_enabled = 0;
+static char lcd_flush_dcache; /* 1 to flush dcache after each lcd update */
+
+
#ifdef NOT_USED_SO_FAR
static void lcd_getcolreg(ushort regno,
ushort *red, ushort *green, ushort *blue);
/************************************************************************/
+/* Flush LCD activity to the caches */
+void lcd_sync(void)
+{
+ /*
+ * flush_dcache_range() is declared in common.h but it seems that some
+ * architectures do not actually implement it. Is there a way to find
+ * out whether it exists? For now, ARM is safe.
+ */
+#if defined(CONFIG_ARM) && !defined(CONFIG_SYS_DCACHE_OFF)
+ int line_length;
+
+ if (lcd_flush_dcache)
+ flush_dcache_range((u32)lcd_base,
+ (u32)(lcd_base + lcd_get_size(&line_length)));
+#endif
+}
+
+void lcd_set_flush_dcache(int flush)
+{
+ lcd_flush_dcache = (flush != 0);
+}
+
/*----------------------------------------------------------------------*/
static void console_scrollup(void)
{
- /* Copy up rows ignoring the first one */
- memcpy(CONSOLE_ROW_FIRST, CONSOLE_ROW_SECOND, CONSOLE_SCROLL_SIZE);
+ const int rows = CONFIG_CONSOLE_SCROLL_LINES;
- /* Clear the last one */
- memset(CONSOLE_ROW_LAST, COLOR_MASK(lcd_color_bg), CONSOLE_ROW_SIZE);
+ /* Copy up rows ignoring those that will be overwritten */
+ memcpy(CONSOLE_ROW_FIRST,
+ lcd_console_address + CONSOLE_ROW_SIZE * rows,
+ CONSOLE_SIZE - CONSOLE_ROW_SIZE * rows);
+
+ /* Clear the last rows */
+ memset(lcd_console_address + CONSOLE_SIZE - CONSOLE_ROW_SIZE * rows,
+ COLOR_MASK(lcd_color_bg),
+ CONSOLE_ROW_SIZE * rows);
+
+ lcd_sync();
+ console_row -= rows;
}
/*----------------------------------------------------------------------*/
if (console_row >= CONSOLE_ROWS) {
/* Scroll everything up */
console_scrollup();
- --console_row;
+ } else {
+ lcd_sync();
}
}
while (*s) {
lcd_putc(*s++);
}
+ lcd_sync();
}
/*----------------------------------------------------------------------*/
/* ** GENERIC Initialization Routines */
/************************************************************************/
+int lcd_get_size(int *line_length)
+{
+ *line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8;
+ return *line_length * panel_info.vl_row;
+}
+
int drv_lcd_init (void)
{
struct stdio_dev lcddev;
lcd_base = (void *)(gd->fb_base);
- lcd_line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8;
+ lcd_get_size(&lcd_line_length);
lcd_init(lcd_base); /* LCD initialization */
}
/*----------------------------------------------------------------------*/
-static
-int do_lcd_clear(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
-{
- lcd_clear();
- return 0;
-}
-
void lcd_clear(void)
{
#if LCD_BPP == LCD_MONOCHROME
console_col = 0;
console_row = 0;
+ lcd_sync();
+}
+
+static int do_lcd_clear(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ lcd_clear();
+ return 0;
}
U_BOOT_CMD(
ulong lcd_setmem(ulong addr)
{
ulong size;
- int line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8;
+ int line_length;
debug("LCD panel info: %d x %d, %d bit/pix\n", panel_info.vl_col,
panel_info.vl_row, NBITS(panel_info.vl_bpix));
- size = line_length * panel_info.vl_row;
+ size = lcd_get_size(&line_length);
- /* Round up to nearest full page */
- size = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
+ /* Round up to nearest full page, or MMU section if defined */
+ size = ALIGN(size, CONFIG_LCD_ALIGNMENT);
+ addr = ALIGN(addr - CONFIG_LCD_ALIGNMENT + 1, CONFIG_LCD_ALIGNMENT);
/* Allocate pages for the frame buffer. */
addr -= size;
}
WATCHDOG_RESET();
+ lcd_sync();
}
#else
static inline void bitmap_plot(int x, int y) {}
}
/* We support displaying 8bpp BMPs on 16bpp LCDs */
- if (bpix != bmp_bpix && (bmp_bpix != 8 || bpix != 16 || bpix != 32)) {
+ if (bpix != bmp_bpix && !(bmp_bpix == 8 && bpix == 16)) {
printf ("Error: %d bit/pixel mode, but BMP has %d bit/pixel\n",
bpix,
le16_to_cpu(bmp->header.bit_count));
break;
};
+ lcd_sync();
return 0;
}
#endif
puts (tab_seq+(col&07));
col += 8 - (col&07);
} else {
- ++col; /* echo input */
- putc (c);
+ char buf[2];
+
+ /*
+ * Echo input using puts() to force am
+ * LCD flush if we are using an LCD
+ */
+ ++col;
+ buf[0] = c;
+ buf[1] = '\0';
+ puts(buf);
}
*p++ = c;
++n;
return &usb_dev[dev_index - 1];
}
+/*
+ * Free the newly created device node.
+ * Called in error cases where configuring a newly attached
+ * device fails for some reason.
+ */
+void usb_free_device(void)
+{
+ dev_index--;
+ USB_PRINTF("Freeing device node: %d\n", dev_index);
+ memset(&usb_dev[dev_index], 0, sizeof(struct usb_device));
+ usb_dev[dev_index].devnum = -1;
+}
/*
* By the time we get here, the device has gotten a new device ID
/* Run it through the hoops (find a driver, etc) */
if (usb_new_device(usb)) {
/* Woops, disable the port */
+ usb_free_device();
+ dev->children[port] = NULL;
USB_HUB_PRINTF("hub: disabling port %d\n", port + 1);
usb_clear_port_feature(dev, port + 1, USB_PORT_FEAT_ENABLE);
}
for (i = 0; i < dev->maxchild; i++) {
ALLOC_CACHE_ALIGN_BUFFER(struct usb_port_status, portsts, 1);
unsigned short portstatus, portchange;
+ int ret;
+ ulong start = get_timer(0);
+
+ /*
+ * Wait for (whichever finishes first)
+ * - A maximum of 10 seconds
+ * This is a purely observational value driven by connecting
+ * a few broken pen drives and taking the max * 1.5 approach
+ * - connection_change and connection state to report same
+ * state
+ */
+ do {
+ ret = usb_get_port_status(dev, i + 1, portsts);
+ if (ret < 0) {
+ USB_HUB_PRINTF("get_port_status failed\n");
+ break;
+ }
+
+ portstatus = le16_to_cpu(portsts->wPortStatus);
+ portchange = le16_to_cpu(portsts->wPortChange);
+
+ if ((portchange & USB_PORT_STAT_C_CONNECTION) ==
+ (portstatus & USB_PORT_STAT_CONNECTION))
+ break;
+
+ mdelay(100);
+ } while (get_timer(start) < CONFIG_SYS_HZ * 10);
- if (usb_get_port_status(dev, i + 1, portsts) < 0) {
- USB_HUB_PRINTF("get_port_status failed\n");
+ if (ret < 0)
continue;
- }
- portstatus = le16_to_cpu(portsts->wPortStatus);
- portchange = le16_to_cpu(portsts->wPortChange);
USB_HUB_PRINTF("Port %d Status %X Change %X\n",
i + 1, portstatus, portchange);
return 0;
}
usb_request_sense(srb, ss);
+ /*
+ * Check the Key Code Qualifier, if it matches
+ * "Not Ready - medium not present"
+ * (the sense Key equals 0x2 and the ASC is 0x3a)
+ * return immediately as the medium being absent won't change
+ * unless there is a user action.
+ */
+ if ((srb->sense_buf[2] == 0x02) &&
+ (srb->sense_buf[12] == 0x3a))
+ return -1;
mdelay(100);
} while (retries--);
mode), which causes the effect of this failure to be much lower (in terms
of frequency deviation), avoiding system failure, or at least decreasing
the likelihood of system failure.
+
+1.2 CONFIG_SYS_MAIN_PWR_ON: Trigger MAIN_PWR_ON upon startup.
+ This option should be enabled for boards having a SYS_ON_OFF_CTL signal
+ connected to GPIO1[23] and triggering the MAIN_PWR_ON signal like in the
+ reference designs.
--- /dev/null
+========================================
+Renesas R0P7752C00000RZ board
+========================================
+
+This board specification:
+=========================
+
+The R0P7752C00000RZ(board config name:sh7752evb) has the following device:
+
+ - SH7752 (SH-4A)
+ - DDR3-SDRAM 512MB
+ - SPI ROM 8MB
+ - Gigabit Ethernet controllers
+ - eMMC 4GB
+
+
+Configuration for This board:
+=============================
+
+You can select the configuration as follows:
+
+ - make sh7752evb_config
+
+
+This board specific command:
+============================
+
+This board has the following its specific command:
+
+ - write_mac
+
+
+1. write_mac
+
+You can write MAC address to SPI ROM.
+
+ Usage 1) Write MAC address
+
+ write_mac [GETHERC ch0] [GETHERC ch1]
+
+ For example)
+ => write_mac 74:90:50:00:33:9e 74:90:50:00:33:9f
+ *) We have to input the command as a single line
+ (without carriage return)
+ *) We have to reset after input the command.
+
+ Usage 2) Show current data
+
+ write_mac
+
+ For example)
+ => write_mac
+ GETHERC ch0 = 74:90:50:00:33:9e
+ GETHERC ch1 = 74:90:50:00:33:9f
+
+
+Update SPI ROM:
+============================
+
+1. Copy u-boot image to RAM area.
+2. Probe SPI device.
+ => sf probe 0
+ SF: Detected MX25L6405D with page size 64KiB, total 8 MiB
+3. Erase SPI ROM.
+ => sf erase 0 80000
+4. Write u-boot image to SPI ROM.
+ => sf write 0x48000000 0 80000
Storage USB Commands:
- usb scan: scans the USB for storage devices.The USB must be
running for this command (usb start)
-- usb device [dev]: show or set current USB staorage device
+- usb device [dev]: show or set current USB storage device
- usb part [dev]: print partition table of one or all USB storage
devices
- usb read addr blk# cnt:
--- /dev/null
+Watchdog driver general info
+
+CONFIG_HW_WATCHDOG
+ This enables hw_watchdog_reset to be called during various loops,
+ including waiting for a character on a serial port. But it
+ does not also call hw_watchdog_init. Boards which want this
+ enabled must call this function in their board file. This split
+ is useful because some rom's enable the watchdog when downloading
+ new code, so it must be serviced, but the board would rather it
+ was off. And, it cannot always be turned off once on.
+
+CONFIG_WATCHDOG_TIMEOUT_MSECS
+ Can be used to change the timeout for i.mx31/35/5x/6x.
+ If not given, will default to maximum timeout. This would
+ be 128000 msec for i.mx31/35/5x/6x.
+
+CONFIG_AT91SAM9_WATCHDOG
+ Available for AT91SAM9 to service the watchdog.
+
+CONFIG_FTWDT010_WATCHDOG
+ Available for FTWDT010 to service the watchdog.
+
+CONFIG_FTWDT010_HW_TIMEOUT
+ Can be used to change the timeout for FTWDT010.
+
+CONFIG_IMX_WATCHDOG
+ Available for i.mx31/35/5x/6x to service the watchdog. This is not
+ automatically set because some boards (vision2) still need to define
+ their own hw_watchdog_reset routine.
--- /dev/null
+Exynos ISP SPI Subsystem
+
+The device node for ISP SPI subsytem.
+Since Peripheral id in EXYNOS is decoded based on Interrupts, currently
+ISP SPI have no individual interrupts hence we add ad dummy interrupt node
+which will have a value beyond the maximum number of interrupts exynos5 can
+support.
+
+Required properties :
+ - compatible : Should be "samsung,exynos-spi" for spi.
+ - reg : Base adrress of the the subsystem.
+ - interrupts : A value which is beyond the maximum number of interrupts
+exynos5 can support.
+
+Example:
+spi@131a0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "samsung,exynos-spi";
+ reg = <0x131a0000 0x30>;
+ interrupts = <0 129 0>;
+};
--- /dev/null
+Exynos Sound Subsystem
+
+The device node for sound subsytem which contains codec and i2s block
+that is a part of Exynos5250
+
+Required properties :
+ - compatible : Should be "samsung,exynos-sound" for sound
+ - samsung,i2s-epll-clock-frequency : epll clock output frequency in Hz
+ - samsung,i2s-sampling-rate : sampling rate, default is 48000
+ - samsung,i2s-bits-per-sample : sample width, defalut is 16 bit
+ - samsung,i2s-channels : nummber of channels, default is 2
+ - samsung,i2s-lr-clk-framesize : lr clock frame size
+ - samsung,i2s-bit-clk-framesize : bit clock frame size
+ - samsung,codec-type : sound codec type
+
+Example:
+
+sound@12d60000 {
+ compatible = "samsung,exynos-sound"
+ samsung,i2s-epll-clock-frequency = <192000000>;
+ samsung,i2s-sampling-rate = <48000>;
+ samsung,i2s-bits-per-sample = <16>;
+ samsung,i2s-channels = <2>;
+ samsung,i2s-lr-clk-framesize = <256>;
+ samsung,i2s-bit-clk-framesize = <32>;
+ samsung,codec-type = "wm8994";
+};
--- /dev/null
+Tegra SoC PWFM controller
+
+Required properties:
+- compatible: should be one of:
+ - "nvidia,tegra20-pwm"
+ - "nvidia,tegra30-pwm"
+- reg: physical base address and length of the controller's registers
+- #pwm-cells: On Tegra the number of cells used to specify a PWM is 2. The
+ first cell specifies the per-chip index of the PWM to use and the second
+ cell is the period in nanoseconds.
+
+Example:
+
+ pwm: pwm@7000a000 {
+ compatible = "nvidia,tegra20-pwm";
+ reg = <0x7000a000 0x100>;
+ #pwm-cells = <2>;
+ };
--- /dev/null
+videomode bindings
+==================
+
+(from http://lists.freedesktop.org/archives/dri-devel/2012-July/024875.html)
+
+Required properties:
+ - xres, yres: Display resolution
+ - left-margin, right-margin, hsync-len: Horizontal Display timing
+ parameters in pixels
+ - upper-margin, lower-margin, vsync-len: Vertical display timing
+ parameters in lines
+ - clock: display clock in Hz
+
+Optional properties:
+ - width-mm, height-mm: Display dimensions in mm
+ - hsync-active-high (bool): Hsync pulse is active high
+ - vsync-active-high (bool): Vsync pulse is active high
+ - interlaced (bool): This is an interlaced mode
+ - doublescan (bool): This is a doublescan mode
+
+There are different ways of describing a display mode. The devicetree
+representation corresponds to the one used by the Linux Framebuffer
+framework described here in Documentation/fb/framebuffer.txt. This
+representation has been chosen because it's the only format which does
+not allow for inconsistent parameters. Unlike the Framebuffer framework
+the devicetree has the clock in Hz instead of ps.
+
+Example:
+
+ display@0 {
+ /* 1920x1080p24 */
+ clock = <52000000>;
+ xres = <1920>;
+ yres = <1080>;
+ left-margin = <25>;
+ right-margin = <25>;
+ hsync-len = <25>;
+ lower-margin = <2>;
+ upper-margin = <2>;
+ vsync-len = <2>;
+ hsync-active-high;
+ };
--- /dev/null
+Display Controller
+------------------
+
+(there isn't yet a generic binding in Linux, so this describes what is in
+U-Boot, and may change based on Linux activity)
+
+The device node for a display device is as described in the document
+"Open Firmware Recommended Practice : Universal Serial Bus" with the
+following modifications and additions :
+
+Required properties :
+ - compatible : Should be "nvidia,tegra20-dc"
+
+Required subnode 'rgb' is as follows:
+
+Required properties (rgb) :
+ - nvidia,panel : phandle of LCD panel information
+
+
+The panel node describes the panel itself. This has the properties listed in
+displaymode.txt as well as:
+
+Required properties (panel) :
+ - nvidia,bits-per-pixel: number of bits per pixel (depth)
+ - nvidia,pwm : pwm to use to set display contrast (see tegra20-pwm.txt)
+ - nvidia,panel-timings: 4 cells containing required timings in ms:
+ * delay before asserting panel_vdd
+ * delay between panel_vdd-rise and data-rise
+ * delay between data-rise and backlight_vdd-rise
+ * delay between backlight_vdd and pwm-rise
+ * delay between pwm-rise and backlight_en-rise
+
+Optional GPIO properies all have (phandle, GPIO number, flags):
+ - nvidia,backlight-enable-gpios: backlight enable GPIO
+ - nvidia,lvds-shutdown-gpios: LVDS power shutdown GPIO
+ - nvidia,backlight-vdd-gpios: backlight power GPIO
+ - nvidia,panel-vdd-gpios: panel power GPIO
+
+Example:
+
+host1x {
+ compatible = "nvidia,tegra20-host1x", "simple-bus";
+ reg = <0x50000000 0x00024000>;
+ interrupts = <0 65 0x04 /* mpcore syncpt */
+ 0 67 0x04>; /* mpcore general */
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "okay";
+
+ ranges = <0x54000000 0x54000000 0x04000000>;
+
+ dc@54200000 {
+ compatible = "nvidia,tegra20-dc";
+ reg = <0x54200000 0x00040000>;
+ interrupts = <0 73 0x04>;
+ status = "okay";
+
+ rgb {
+ status = "okay";
+ nvidia,panel = <&lcd_panel>;
+ };
+ };
+};
+
+lcd_panel: panel {
+ /* Seaboard has 1366x768 */
+ clock = <70600000>;
+ xres = <1366>;
+ yres = <768>;
+ left-margin = <58>;
+ right-margin = <58>;
+ hsync-len = <58>;
+ lower-margin = <4>;
+ upper-margin = <4>;
+ vsync-len = <4>;
+ hsync-active-high;
+ nvidia,bits-per-pixel = <16>;
+ nvidia,pwm = <&pwm 2 0>;
+ nvidia,backlight-enable-gpios = <&gpio 28 0>; /* PD4 */
+ nvidia,lvds-shutdown-gpios = <&gpio 10 0>; /* PB2 */
+ nvidia,backlight-vdd-gpios = <&gpio 176 0>; /* PW0 */
+ nvidia,panel-vdd-gpios = <&gpio 22 0>; /* PC6 */
+ nvidia,panel-timings = <400 4 203 17 15>;
+};
[1] = GPIO2_BASE_ADDR,
[2] = GPIO3_BASE_ADDR,
#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
- defined(CONFIG_MX53) || defined(CONFIG_MX6Q)
+ defined(CONFIG_MX53) || defined(CONFIG_MX6)
[3] = GPIO4_BASE_ADDR,
#endif
-#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6Q)
+#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6)
[4] = GPIO5_BASE_ADDR,
[5] = GPIO6_BASE_ADDR,
#endif
-#if defined(CONFIG_MX53) || defined(CONFIG_MX6Q)
+#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
[6] = GPIO7_BASE_ADDR,
#endif
};
return gpio & 0x1f;
}
-static inline int gpio_valid(int gpio)
+int gpio_is_valid(int gpio)
{
- if (gpio < 0)
- return -1;
- if (gpio < 192)
- return 0;
- return -1;
+ return (gpio >= 0) && (gpio < 192);
}
static int check_gpio(int gpio)
{
- if (gpio_valid(gpio) < 0) {
+ if (!gpio_is_valid(gpio)) {
printf("ERROR : check_gpio: invalid GPIO %d\n", gpio);
return -1;
}
struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned gpio)
{
- int bank = gpio / GPIO_PER_BANK;
- bank *= sizeof(struct s5p_gpio_bank);
+ int bank;
+ unsigned g = gpio - s5p_gpio_part_max(gpio);
+ bank = g / GPIO_PER_BANK;
+ bank *= sizeof(struct s5p_gpio_bank);
return (struct s5p_gpio_bank *) (s5p_gpio_base(gpio) + bank);
}
#define I2C_TIMEOUT 1000
-static void wait_for_bb(void);
+static int wait_for_bb(void);
static u16 wait_for_pin(void);
static void flush_fifo(void);
u16 w;
/* wait until bus not busy */
- wait_for_bb();
+ if (wait_for_bb())
+ return 1;
/* one byte only */
writew(alen, &i2c_base->cnt);
return res;
/* wait until bus not busy */
- wait_for_bb();
+ if (wait_for_bb())
+ return res;
/* try to read one byte */
writew(1, &i2c_base->cnt);
res = 1;
writew(0xff, &i2c_base->stat);
writew (readw (&i2c_base->con) | I2C_CON_STP, &i2c_base->con);
- wait_for_bb ();
+
+ if (wait_for_bb())
+ res = 1;
+
break;
}
if (status & I2C_STAT_ARDY) {
}
/* wait until bus not busy */
- wait_for_bb();
+ if (wait_for_bb())
+ return 1;
/* start address phase - will write regoffset + len bytes data */
/* TODO consider case when !CONFIG_OMAP243X/34XX/44XX */
return i2c_error;
}
-static void wait_for_bb(void)
+static int wait_for_bb(void)
{
int timeout = I2C_TIMEOUT;
u16 stat;
if (timeout <= 0) {
printf("timed out in wait_for_bb: I2C_STAT=%x\n",
readw(&i2c_base->stat));
+ return 1;
}
writew(0xFFFF, &i2c_base->stat); /* clear delayed stuff*/
+ return 0;
}
static u16 wait_for_pin(void)
*/
#include <common.h>
+#include <fdtdec.h>
#if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
#include <asm/arch/clk.h>
#include <asm/arch/cpu.h>
+#include <asm/arch/pinmux.h>
#else
#include <asm/arch/s3c24x0_cpu.h>
#endif
#define I2C_TIMEOUT 1 /* 1 second */
-static unsigned int g_current_bus; /* Stores Current I2C Bus */
+/*
+ * For SPL boot some boards need i2c before SDRAM is initialised so force
+ * variables to live in SRAM
+ */
+static unsigned int g_current_bus __attribute__((section(".data")));
+#ifdef CONFIG_OF_CONTROL
+static int i2c_busses __attribute__((section(".data")));
+static struct s3c24x0_i2c_bus i2c_bus[CONFIG_MAX_I2C_NUM]
+ __attribute__((section(".data")));
+#endif
#if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
static int GetI2CSDA(void)
(i2c, I2C_WRITE, chip << 1, &xaddr[4 - alen], alen, buffer,
len) != 0);
}
+
+#ifdef CONFIG_OF_CONTROL
+void board_i2c_init(const void *blob)
+{
+ int node_list[CONFIG_MAX_I2C_NUM];
+ int count, i;
+
+ count = fdtdec_find_aliases_for_id(blob, "i2c",
+ COMPAT_SAMSUNG_S3C2440_I2C, node_list,
+ CONFIG_MAX_I2C_NUM);
+
+ for (i = 0; i < count; i++) {
+ struct s3c24x0_i2c_bus *bus;
+ int node = node_list[i];
+
+ if (node <= 0)
+ continue;
+ bus = &i2c_bus[i];
+ bus->regs = (struct s3c24x0_i2c *)
+ fdtdec_get_addr(blob, node, "reg");
+ bus->id = pinmux_decode_periph_id(blob, node);
+ bus->node = node;
+ bus->bus_num = i2c_busses++;
+ exynos_pinmux_config(bus->id, 0);
+ }
+}
+
+static struct s3c24x0_i2c_bus *get_bus(unsigned int bus_idx)
+{
+ if (bus_idx < i2c_busses)
+ return &i2c_bus[bus_idx];
+
+ debug("Undefined bus: %d\n", bus_idx);
+ return NULL;
+}
+
+int i2c_get_bus_num_fdt(int node)
+{
+ int i;
+
+ for (i = 0; i < i2c_busses; i++) {
+ if (node == i2c_bus[i].node)
+ return i;
+ }
+
+ debug("%s: Can't find any matched I2C bus\n", __func__);
+ return -1;
+}
+
+int i2c_reset_port_fdt(const void *blob, int node)
+{
+ struct s3c24x0_i2c_bus *i2c;
+ int bus;
+
+ bus = i2c_get_bus_num_fdt(node);
+ if (bus < 0) {
+ debug("could not get bus for node %d\n", node);
+ return -1;
+ }
+
+ i2c = get_bus(bus);
+ if (!i2c) {
+ debug("get_bus() failed for node node %d\n", node);
+ return -1;
+ }
+
+ i2c_ch_init(i2c->regs, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+ return 0;
+}
+#endif
+
#endif /* CONFIG_HARD_I2C */
u32 iicds;
u32 iiclc;
};
+
+struct s3c24x0_i2c_bus {
+ int node; /* device tree node */
+ int bus_num; /* i2c bus number */
+ struct s3c24x0_i2c *regs;
+ int id;
+};
#endif /* _S3C24X0_I2C_H */
struct kbc_tegra *kbc; /* tegra keyboard controller */
unsigned char inited; /* 1 if keyboard has been inited */
unsigned char first_scan; /* 1 if this is our first key scan */
+ unsigned char created; /* 1 if driver has been created */
/*
* After init we must wait a short time before polling the keyboard.
*/
static int init_tegra_keyboard(void)
{
+ /* check if already created */
+ if (config.created)
+ return 0;
+
#ifdef CONFIG_OF_CONTROL
int node;
config_kbc_gpio(config.kbc);
tegra_kbc_open();
+ config.created = 1;
debug("%s: Tegra keyboard ready\n", __func__);
return 0;
int drv_keyboard_init(void)
{
struct stdio_dev dev;
+ char *stdinname = getenv("stdin");
+ int error;
if (input_init(&config.input, 0)) {
debug("%s: Cannot set up input\n", __func__);
dev.start = init_tegra_keyboard;
/* Register the device. init_tegra_keyboard() will be called soon */
- return input_stdio_register(&dev);
+ error = input_stdio_register(&dev);
+ if (error)
+ return error;
+#ifdef CONFIG_CONSOLE_MUX
+ error = iomux_doenv(stdin, stdinname);
+ if (error)
+ return error;
+#endif
+ return 0;
}
return -1;
}
- mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
+ mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC;
if (caps & ESDHC_HOSTCAPBLT_HSS)
mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
mmc->getcd = tegra_mmc_getcd;
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
+ mmc->host_caps = 0;
if (bus_width == 8)
- mmc->host_caps = MMC_MODE_8BIT;
- else
- mmc->host_caps = MMC_MODE_4BIT;
+ mmc->host_caps |= MMC_MODE_8BIT;
+ if (bus_width >= 4)
+ mmc->host_caps |= MMC_MODE_4BIT;
mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_HC;
/*
AMD_CMD_ERASE_START);
flash_unlock_seq (info, sect);
flash_write_cmd (info, sect, 0,
- AMD_CMD_ERASE_SECTOR);
+ info->cmd_erase_sector);
break;
#ifdef CONFIG_FLASH_CFI_LEGACY
case CFI_CMDSET_AMD_LEGACY:
printf(info->chipwidth == FLASH_CFI_16BIT ? "%04X" : "%02X",
info->device_id2);
}
+ if ((info->vendor == CFI_CMDSET_AMD_STANDARD) && (info->legacy_unlock))
+ printf("\n Advanced Sector Protection (PPB) enabled");
printf ("\n Erase timeout: %ld ms, write timeout: %ld ms\n",
info->erase_blk_tout,
info->write_tout);
return flash_write_cfiword (info, wp, cword);
}
+static inline int manufact_match(flash_info_t *info, u32 manu)
+{
+ return info->manufacturer_id == ((manu & FLASH_VENDMASK) >> 16);
+}
+
/*-----------------------------------------------------------------------
*/
#ifdef CONFIG_SYS_FLASH_PROTECTION
static int cfi_protect_bugfix(flash_info_t *info, long sector, int prot)
{
- if (info->manufacturer_id == ((INTEL_MANUFACT & FLASH_VENDMASK) >> 16)
+ if (manufact_match(info, INTEL_MANUFACT)
&& info->device_id == NUMONYX_256MBIT) {
/*
* see errata called
case CFI_CMDSET_AMD_EXTENDED:
case CFI_CMDSET_AMD_STANDARD:
/* U-Boot only checks the first byte */
- if (info->manufacturer_id ==
- ((ATM_MANUFACT & FLASH_VENDMASK) >> 16)) {
+ if (manufact_match(info, ATM_MANUFACT)) {
if (prot) {
flash_unlock_seq (info, 0);
flash_write_cmd (info, 0,
0, ATM_CMD_UNLOCK_SECT);
}
}
- if (info->manufacturer_id ==
- ((AMD_MANUFACT & FLASH_VENDMASK) >> 16)) {
+ if (info->legacy_unlock) {
int flag = disable_interrupts();
int lock_flag;
static int cmdset_amd_init(flash_info_t *info, struct cfi_qry *qry)
{
info->cmd_reset = AMD_CMD_RESET;
+ info->cmd_erase_sector = AMD_CMD_ERASE_SECTOR;
cmdset_amd_read_jedec_ids(info);
flash_write_cmd(info, 0, info->cfi_offset, FLASH_CMD_CFI);
#ifdef CONFIG_SYS_FLASH_PROTECTION
- if (info->ext_addr && info->manufacturer_id ==
- ((AMD_MANUFACT & FLASH_VENDMASK) >> 16)) {
- ushort spus;
-
- /* read sector protect/unprotect scheme */
- spus = flash_read_uchar(info, info->ext_addr + 9);
- if (spus == 0x8)
+ if (info->ext_addr) {
+ /* read sector protect/unprotect scheme (at 0x49) */
+ if (flash_read_uchar(info, info->ext_addr + 9) == 0x8)
info->legacy_unlock = 1;
}
#endif
}
}
+static void flash_fixup_sst(flash_info_t *info, struct cfi_qry *qry)
+{
+ /*
+ * SST, for many recent nor parallel flashes, says they are
+ * CFI-conformant. This is not true, since qry struct.
+ * reports a std. AMD command set (0x0002), while SST allows to
+ * erase two different sector sizes for the same memory.
+ * 64KB sector (SST call it block) needs 0x30 to be erased.
+ * 4KB sector (SST call it sector) needs 0x50 to be erased.
+ * Since CFI query detect the 4KB number of sectors, users expects
+ * a sector granularity of 4KB, and it is here set.
+ */
+ if (info->device_id == 0x5D23 || /* SST39VF3201B */
+ info->device_id == 0x5C23) { /* SST39VF3202B */
+ /* set sector granularity to 4KB */
+ info->cmd_erase_sector=0x50;
+ }
+}
+
/*
* The following code cannot be run from FLASH!
*
case 0x0020:
flash_fixup_stm(info, &qry);
break;
+ case 0x00bf: /* SST */
+ flash_fixup_sst(info, &qry);
+ break;
}
debug ("manufacturer is %d\n", info->vendor);
FLASH_OFFSET_PROTECT,
FLASH_STATUS_PROTECT);
break;
+ case CFI_CMDSET_AMD_EXTENDED:
+ case CFI_CMDSET_AMD_STANDARD:
+ if (!info->legacy_unlock) {
+ /* default: not protected */
+ info->protect[sect_cnt] = 0;
+ break;
+ }
+
+ /* Read protection (PPB) from sector */
+ flash_write_cmd(info, 0, 0,
+ info->cmd_reset);
+ flash_unlock_seq(info, 0);
+ flash_write_cmd(info, 0,
+ info->addr_unlock1,
+ FLASH_CMD_READ_ID);
+ info->protect[sect_cnt] =
+ flash_isset(
+ info, sect_cnt,
+ FLASH_OFFSET_PROTECT,
+ FLASH_STATUS_PROTECT);
+ break;
default:
/* default: not protected */
info->protect[sect_cnt] = 0;
NORMAL_DRIVERS=y
endif
+COBJS-$(CONFIG_SPL_NAND_AM33XX_BCH) += am335x_spl_bch.o
COBJS-$(CONFIG_SPL_NAND_SIMPLE) += nand_spl_simple.o
COBJS-$(CONFIG_SPL_NAND_LOAD) += nand_spl_load.o
COBJS-$(CONFIG_SPL_NAND_ECC) += nand_ecc.o
--- /dev/null
+/*
+ * (C) Copyright 2012
+ * Konstantin Kozhevnikov, Cogent Embedded
+ *
+ * based on nand_spl_simple code
+ *
+ * (C) Copyright 2006-2008
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <common.h>
+#include <nand.h>
+#include <asm/io.h>
+#include <linux/mtd/nand_ecc.h>
+
+static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
+static nand_info_t mtd;
+static struct nand_chip nand_chip;
+
+#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
+ CONFIG_SYS_NAND_ECCSIZE)
+#define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
+
+
+/*
+ * NAND command for large page NAND devices (2k)
+ */
+static int nand_command(int block, int page, uint32_t offs,
+ u8 cmd)
+{
+ struct nand_chip *this = mtd.priv;
+ int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
+ void (*hwctrl)(struct mtd_info *mtd, int cmd,
+ unsigned int ctrl) = this->cmd_ctrl;
+
+ while (!this->dev_ready(&mtd))
+ ;
+
+ /* Emulate NAND_CMD_READOOB */
+ if (cmd == NAND_CMD_READOOB) {
+ offs += CONFIG_SYS_NAND_PAGE_SIZE;
+ cmd = NAND_CMD_READ0;
+ }
+
+ /* Begin command latch cycle */
+ hwctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
+
+ if (cmd == NAND_CMD_RESET) {
+ hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+ while (!this->dev_ready(&mtd))
+ ;
+ return 0;
+ }
+
+ /* Shift the offset from byte addressing to word addressing. */
+ if (this->options & NAND_BUSWIDTH_16)
+ offs >>= 1;
+
+ /* Set ALE and clear CLE to start address cycle */
+ /* Column address */
+ hwctrl(&mtd, offs & 0xff,
+ NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
+ hwctrl(&mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
+ /* Row address */
+ hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */
+ hwctrl(&mtd, ((page_addr >> 8) & 0xff),
+ NAND_CTRL_ALE); /* A[27:20] */
+#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
+ /* One more address cycle for devices > 128MiB */
+ hwctrl(&mtd, (page_addr >> 16) & 0x0f,
+ NAND_CTRL_ALE); /* A[31:28] */
+#endif
+ hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+
+ if (cmd == NAND_CMD_READ0) {
+ /* Latch in address */
+ hwctrl(&mtd, NAND_CMD_READSTART,
+ NAND_CTRL_CLE | NAND_CTRL_CHANGE);
+ hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+
+ /*
+ * Wait a while for the data to be ready
+ */
+ while (!this->dev_ready(&mtd))
+ ;
+ } else if (cmd == NAND_CMD_RNDOUT) {
+ hwctrl(&mtd, NAND_CMD_RNDOUTSTART, NAND_CTRL_CLE |
+ NAND_CTRL_CHANGE);
+ hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+ }
+
+ return 0;
+}
+
+static int nand_is_bad_block(int block)
+{
+ struct nand_chip *this = mtd.priv;
+
+ nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS,
+ NAND_CMD_READOOB);
+
+ /*
+ * Read one byte (or two if it's a 16 bit chip).
+ */
+ if (this->options & NAND_BUSWIDTH_16) {
+ if (readw(this->IO_ADDR_R) != 0xffff)
+ return 1;
+ } else {
+ if (readb(this->IO_ADDR_R) != 0xff)
+ return 1;
+ }
+
+ return 0;
+}
+
+static int nand_read_page(int block, int page, void *dst)
+{
+ struct nand_chip *this = mtd.priv;
+ u_char ecc_calc[ECCTOTAL];
+ u_char ecc_code[ECCTOTAL];
+ u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
+ int i;
+ int eccsize = CONFIG_SYS_NAND_ECCSIZE;
+ int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
+ int eccsteps = ECCSTEPS;
+ uint8_t *p = dst;
+ uint32_t data_pos = 0;
+ uint8_t *oob = &oob_data[0] + nand_ecc_pos[0];
+ uint32_t oob_pos = eccsize * eccsteps + nand_ecc_pos[0];
+
+ nand_command(block, page, 0, NAND_CMD_READ0);
+
+ for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+ this->ecc.hwctl(&mtd, NAND_ECC_READ);
+ nand_command(block, page, data_pos, NAND_CMD_RNDOUT);
+
+ this->read_buf(&mtd, p, eccsize);
+
+ nand_command(block, page, oob_pos, NAND_CMD_RNDOUT);
+
+ this->read_buf(&mtd, oob, eccbytes);
+ this->ecc.calculate(&mtd, p, &ecc_calc[i]);
+
+ data_pos += eccsize;
+ oob_pos += eccbytes;
+ oob += eccbytes;
+ }
+
+ /* Pick the ECC bytes out of the oob data */
+ for (i = 0; i < ECCTOTAL; i++)
+ ecc_code[i] = oob_data[nand_ecc_pos[i]];
+
+ eccsteps = ECCSTEPS;
+ p = dst;
+
+ for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+ /* No chance to do something with the possible error message
+ * from correct_data(). We just hope that all possible errors
+ * are corrected by this routine.
+ */
+ this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]);
+ }
+
+ return 0;
+}
+
+int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
+{
+ unsigned int block, lastblock;
+ unsigned int page;
+
+ /*
+ * offs has to be aligned to a page address!
+ */
+ block = offs / CONFIG_SYS_NAND_BLOCK_SIZE;
+ lastblock = (offs + size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE;
+ page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE;
+
+ while (block <= lastblock) {
+ if (!nand_is_bad_block(block)) {
+ /*
+ * Skip bad blocks
+ */
+ while (page < CONFIG_SYS_NAND_PAGE_COUNT) {
+ nand_read_page(block, page, dst);
+ dst += CONFIG_SYS_NAND_PAGE_SIZE;
+ page++;
+ }
+
+ page = 0;
+ } else {
+ lastblock++;
+ }
+
+ block++;
+ }
+
+ return 0;
+}
+
+/* nand_init() - initialize data to make nand usable by SPL */
+void nand_init(void)
+{
+ /*
+ * Init board specific nand support
+ */
+ mtd.priv = &nand_chip;
+ nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W =
+ (void __iomem *)CONFIG_SYS_NAND_BASE;
+ board_nand_init(&nand_chip);
+
+ if (nand_chip.select_chip)
+ nand_chip.select_chip(&mtd, 0);
+
+ /* NAND chip may require reset after power-on */
+ nand_command(0, 0, 0, NAND_CMD_RESET);
+}
+
+/* Unselect after operation */
+void nand_deselect(void)
+{
+ if (nand_chip.select_chip)
+ nand_chip.select_chip(&mtd, -1);
+}
timing = IFC_FIR_OP_RBCD;
out_be32(&ifc->ifc_nand.nand_fir0,
- (IFC_FIR_OP_CMD0 << IFC_NAND_FIR0_OP0_SHIFT) |
+ (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
(IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
(timing << IFC_NAND_FIR0_OP2_SHIFT));
out_be32(&ifc->ifc_nand.nand_fcr0,
/* READID */
out_be32(&ifc->ifc_nand.nand_fir0,
- (IFC_FIR_OP_CMD0 << IFC_NAND_FIR0_OP0_SHIFT) |
+ (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
(IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
(IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT));
out_be32(&ifc->ifc_nand.nand_fcr0,
{
struct mxs_gpmi_regs *gpmi_regs =
(struct mxs_gpmi_regs *)MXS_GPMI_BASE;
+ struct mxs_bch_regs *bch_regs =
+ (struct mxs_bch_regs *)MXS_BCH_BASE;
int i = 0, j;
info->desc = malloc(sizeof(struct mxs_dma_desc *) *
/* Reset the GPMI block. */
mxs_reset_block(&gpmi_regs->hw_gpmi_ctrl0_reg);
+ mxs_reset_block(&bch_regs->hw_bch_ctrl_reg);
/*
* Choose NAND mode, set IRQ polarity, disable write protection and
#include <linux/mtd/nand_ecc.h>
#include <linux/compiler.h>
#include <nand.h>
+#ifdef CONFIG_AM33XX
+#include <asm/arch/elm.h>
+#endif
static uint8_t cs;
static __maybe_unused struct nand_ecclayout hw_nand_oob =
}
}
+/*
+ * BCH8 support (needs ELM and thus AM33xx-only)
+ */
+#ifdef CONFIG_AM33XX
+struct nand_bch_priv {
+ uint8_t mode;
+ uint8_t type;
+ uint8_t nibbles;
+};
+
+/* bch types */
+#define ECC_BCH4 0
+#define ECC_BCH8 1
+#define ECC_BCH16 2
+
+/* BCH nibbles for diff bch levels */
+#define NAND_ECC_HW_BCH ((uint8_t)(NAND_ECC_HW_OOB_FIRST) + 1)
+#define ECC_BCH4_NIBBLES 13
+#define ECC_BCH8_NIBBLES 26
+#define ECC_BCH16_NIBBLES 52
+
+static struct nand_ecclayout hw_bch8_nand_oob = GPMC_NAND_HW_BCH8_ECC_LAYOUT;
+
+static struct nand_bch_priv bch_priv = {
+ .mode = NAND_ECC_HW_BCH,
+ .type = ECC_BCH8,
+ .nibbles = ECC_BCH8_NIBBLES
+};
+
+/*
+ * omap_read_bch8_result - Read BCH result for BCH8 level
+ *
+ * @mtd: MTD device structure
+ * @big_endian: When set read register 3 first
+ * @ecc_code: Read syndrome from BCH result registers
+ */
+static void omap_read_bch8_result(struct mtd_info *mtd, uint8_t big_endian,
+ uint8_t *ecc_code)
+{
+ uint32_t *ptr;
+ int8_t i = 0, j;
+
+ if (big_endian) {
+ ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[3];
+ ecc_code[i++] = readl(ptr) & 0xFF;
+ ptr--;
+ for (j = 0; j < 3; j++) {
+ ecc_code[i++] = (readl(ptr) >> 24) & 0xFF;
+ ecc_code[i++] = (readl(ptr) >> 16) & 0xFF;
+ ecc_code[i++] = (readl(ptr) >> 8) & 0xFF;
+ ecc_code[i++] = readl(ptr) & 0xFF;
+ ptr--;
+ }
+ } else {
+ ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[0];
+ for (j = 0; j < 3; j++) {
+ ecc_code[i++] = readl(ptr) & 0xFF;
+ ecc_code[i++] = (readl(ptr) >> 8) & 0xFF;
+ ecc_code[i++] = (readl(ptr) >> 16) & 0xFF;
+ ecc_code[i++] = (readl(ptr) >> 24) & 0xFF;
+ ptr++;
+ }
+ ecc_code[i++] = readl(ptr) & 0xFF;
+ ecc_code[i++] = 0; /* 14th byte is always zero */
+ }
+}
+
+/*
+ * omap_ecc_disable - Disable H/W ECC calculation
+ *
+ * @mtd: MTD device structure
+ *
+ */
+static void omap_ecc_disable(struct mtd_info *mtd)
+{
+ writel((readl(&gpmc_cfg->ecc_config) & ~0x1),
+ &gpmc_cfg->ecc_config);
+}
+
+/*
+ * omap_rotate_ecc_bch - Rotate the syndrome bytes
+ *
+ * @mtd: MTD device structure
+ * @calc_ecc: ECC read from ECC registers
+ * @syndrome: Rotated syndrome will be retuned in this array
+ *
+ */
+static void omap_rotate_ecc_bch(struct mtd_info *mtd, uint8_t *calc_ecc,
+ uint8_t *syndrome)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct nand_bch_priv *bch = chip->priv;
+ uint8_t n_bytes = 0;
+ int8_t i, j;
+
+ switch (bch->type) {
+ case ECC_BCH4:
+ n_bytes = 8;
+ break;
+
+ case ECC_BCH16:
+ n_bytes = 28;
+ break;
+
+ case ECC_BCH8:
+ default:
+ n_bytes = 13;
+ break;
+ }
+
+ for (i = 0, j = (n_bytes-1); i < n_bytes; i++, j--)
+ syndrome[i] = calc_ecc[j];
+}
+
+/*
+ * omap_calculate_ecc_bch - Read BCH ECC result
+ *
+ * @mtd: MTD structure
+ * @dat: unused
+ * @ecc_code: ecc_code buffer
+ */
+static int omap_calculate_ecc_bch(struct mtd_info *mtd, const uint8_t *dat,
+ uint8_t *ecc_code)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct nand_bch_priv *bch = chip->priv;
+ uint8_t big_endian = 1;
+ int8_t ret = 0;
+
+ if (bch->type == ECC_BCH8)
+ omap_read_bch8_result(mtd, big_endian, ecc_code);
+ else /* BCH4 and BCH16 currently not supported */
+ ret = -1;
+
+ /*
+ * Stop reading anymore ECC vals and clear old results
+ * enable will be called if more reads are required
+ */
+ omap_ecc_disable(mtd);
+
+ return ret;
+}
+
+/*
+ * omap_fix_errors_bch - Correct bch error in the data
+ *
+ * @mtd: MTD device structure
+ * @data: Data read from flash
+ * @error_count:Number of errors in data
+ * @error_loc: Locations of errors in the data
+ *
+ */
+static void omap_fix_errors_bch(struct mtd_info *mtd, uint8_t *data,
+ uint32_t error_count, uint32_t *error_loc)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct nand_bch_priv *bch = chip->priv;
+ uint8_t count = 0;
+ uint32_t error_byte_pos;
+ uint32_t error_bit_mask;
+ uint32_t last_bit = (bch->nibbles * 4) - 1;
+
+ /* Flip all bits as specified by the error location array. */
+ /* FOR( each found error location flip the bit ) */
+ for (count = 0; count < error_count; count++) {
+ if (error_loc[count] > last_bit) {
+ /* Remove the ECC spare bits from correction. */
+ error_loc[count] -= (last_bit + 1);
+ /* Offset bit in data region */
+ error_byte_pos = ((512 * 8) -
+ (error_loc[count]) - 1) / 8;
+ /* Error Bit mask */
+ error_bit_mask = 0x1 << (error_loc[count] % 8);
+ /* Toggle the error bit to make the correction. */
+ data[error_byte_pos] ^= error_bit_mask;
+ }
+ }
+}
+
+/*
+ * omap_correct_data_bch - Compares the ecc read from nand spare area
+ * with ECC registers values and corrects one bit error if it has occured
+ *
+ * @mtd: MTD device structure
+ * @dat: page data
+ * @read_ecc: ecc read from nand flash (ignored)
+ * @calc_ecc: ecc read from ECC registers
+ *
+ * @return 0 if data is OK or corrected, else returns -1
+ */
+static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat,
+ uint8_t *read_ecc, uint8_t *calc_ecc)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct nand_bch_priv *bch = chip->priv;
+ uint8_t syndrome[28];
+ uint32_t error_count = 0;
+ uint32_t error_loc[8];
+ uint32_t i, ecc_flag;
+
+ ecc_flag = 0;
+ for (i = 0; i < chip->ecc.bytes; i++)
+ if (read_ecc[i] != 0xff)
+ ecc_flag = 1;
+
+ if (!ecc_flag)
+ return 0;
+
+ elm_reset();
+ elm_config((enum bch_level)(bch->type));
+
+ /*
+ * while reading ECC result we read it in big endian.
+ * Hence while loading to ELM we have rotate to get the right endian.
+ */
+ omap_rotate_ecc_bch(mtd, calc_ecc, syndrome);
+
+ /* use elm module to check for errors */
+ if (elm_check_error(syndrome, bch->nibbles, &error_count,
+ error_loc) != 0) {
+ printf("ECC: uncorrectable.\n");
+ return -1;
+ }
+
+ /* correct bch error */
+ if (error_count > 0)
+ omap_fix_errors_bch(mtd, dat, error_count, error_loc);
+
+ return 0;
+}
+/*
+ * omap_hwecc_init_bch - Initialize the BCH Hardware ECC for NAND flash in
+ * GPMC controller
+ * @mtd: MTD device structure
+ * @mode: Read/Write mode
+ */
+static void omap_hwecc_init_bch(struct nand_chip *chip, int32_t mode)
+{
+ uint32_t val, dev_width = (chip->options & NAND_BUSWIDTH_16) >> 1;
+ uint32_t unused_length = 0;
+ struct nand_bch_priv *bch = chip->priv;
+
+ switch (bch->nibbles) {
+ case ECC_BCH4_NIBBLES:
+ unused_length = 3;
+ break;
+ case ECC_BCH8_NIBBLES:
+ unused_length = 2;
+ break;
+ case ECC_BCH16_NIBBLES:
+ unused_length = 0;
+ break;
+ }
+
+ /* Clear the ecc result registers, select ecc reg as 1 */
+ writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
+
+ switch (mode) {
+ case NAND_ECC_WRITE:
+ /* eccsize1 config */
+ val = ((unused_length + bch->nibbles) << 22);
+ break;
+
+ case NAND_ECC_READ:
+ default:
+ /* by default eccsize0 selected for ecc1resultsize */
+ /* eccsize0 config */
+ val = (bch->nibbles << 12);
+ /* eccsize1 config */
+ val |= (unused_length << 22);
+ break;
+ }
+ /* ecc size configuration */
+ writel(val, &gpmc_cfg->ecc_size_config);
+ /* by default 512bytes sector page is selected */
+ /* set bch mode */
+ val = (1 << 16);
+ /* bch4 / bch8 / bch16 */
+ val |= (bch->type << 12);
+ /* set wrap mode to 1 */
+ val |= (1 << 8);
+ val |= (dev_width << 7);
+ val |= (cs << 1);
+ writel(val, &gpmc_cfg->ecc_config);
+}
+
+/*
+ * omap_enable_ecc_bch- This function enables the bch h/w ecc functionality
+ * @mtd: MTD device structure
+ * @mode: Read/Write mode
+ *
+ */
+static void omap_enable_ecc_bch(struct mtd_info *mtd, int32_t mode)
+{
+ struct nand_chip *chip = mtd->priv;
+
+ omap_hwecc_init_bch(chip, mode);
+ /* enable ecc */
+ writel((readl(&gpmc_cfg->ecc_config) | 0x1), &gpmc_cfg->ecc_config);
+}
+
+/**
+ * omap_read_page_bch - hardware ecc based page read function
+ * @mtd: mtd info structure
+ * @chip: nand chip info structure
+ * @buf: buffer to store read data
+ * @page: page number to read
+ *
+ */
+static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
+ uint8_t *buf, int page)
+{
+ int i, eccsize = chip->ecc.size;
+ int eccbytes = chip->ecc.bytes;
+ int eccsteps = chip->ecc.steps;
+ uint8_t *p = buf;
+ uint8_t *ecc_calc = chip->buffers->ecccalc;
+ uint8_t *ecc_code = chip->buffers->ecccode;
+ uint32_t *eccpos = chip->ecc.layout->eccpos;
+ uint8_t *oob = chip->oob_poi;
+ uint32_t data_pos;
+ uint32_t oob_pos;
+
+ data_pos = 0;
+ /* oob area start */
+ oob_pos = (eccsize * eccsteps) + chip->ecc.layout->eccpos[0];
+ oob += chip->ecc.layout->eccpos[0];
+
+ for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize,
+ oob += eccbytes) {
+ chip->ecc.hwctl(mtd, NAND_ECC_READ);
+ /* read data */
+ chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_pos, page);
+ chip->read_buf(mtd, p, eccsize);
+
+ /* read respective ecc from oob area */
+ chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, page);
+ chip->read_buf(mtd, oob, eccbytes);
+ /* read syndrome */
+ chip->ecc.calculate(mtd, p, &ecc_calc[i]);
+
+ data_pos += eccsize;
+ oob_pos += eccbytes;
+ }
+
+ for (i = 0; i < chip->ecc.total; i++)
+ ecc_code[i] = chip->oob_poi[eccpos[i]];
+
+ eccsteps = chip->ecc.steps;
+ p = buf;
+
+ for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+ int stat;
+
+ stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
+ if (stat < 0)
+ mtd->ecc_stats.failed++;
+ else
+ mtd->ecc_stats.corrected += stat;
+ }
+ return 0;
+}
+#endif /* CONFIG_AM33XX */
+
#ifndef CONFIG_SPL_BUILD
/*
* omap_nand_switch_ecc - switch the ECC operation b/w h/w ecc and s/w ecc.
nand->ecc.calculate = NULL;
/* Setup the ecc configurations again */
- if (hardware) {
+ if (hardware == 1) {
nand->ecc.mode = NAND_ECC_HW;
nand->ecc.layout = &hw_nand_oob;
nand->ecc.size = 512;
nand->ecc.calculate = omap_calculate_ecc;
omap_hwecc_init(nand);
printf("HW ECC selected\n");
+#ifdef CONFIG_AM33XX
+ } else if (hardware == 2) {
+ nand->ecc.mode = NAND_ECC_HW;
+ nand->ecc.layout = &hw_bch8_nand_oob;
+ nand->ecc.size = 512;
+ nand->ecc.bytes = 14;
+ nand->ecc.read_page = omap_read_page_bch;
+ nand->ecc.hwctl = omap_enable_ecc_bch;
+ nand->ecc.correct = omap_correct_data_bch;
+ nand->ecc.calculate = omap_calculate_ecc_bch;
+ omap_hwecc_init_bch(nand, NAND_ECC_READ);
+ printf("HW BCH8 selected\n");
+#endif
} else {
nand->ecc.mode = NAND_ECC_SOFT;
/* Use mtd default settings */
nand->options |= NAND_BUSWIDTH_16;
nand->chip_delay = 100;
+
+#ifdef CONFIG_AM33XX
+ /* required in case of BCH */
+ elm_init();
+
+ /* BCH info that will be correct for SPL or overridden otherwise. */
+ nand->priv = &bch_priv;
+#endif
+
/* Default ECC mode */
+#ifdef CONFIG_AM33XX
+ nand->ecc.mode = NAND_ECC_HW;
+ nand->ecc.layout = &hw_bch8_nand_oob;
+ nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
+ nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
+ nand->ecc.hwctl = omap_enable_ecc_bch;
+ nand->ecc.correct = omap_correct_data_bch;
+ nand->ecc.calculate = omap_calculate_ecc_bch;
+ nand->ecc.read_page = omap_read_page_bch;
+ omap_hwecc_init_bch(nand, NAND_ECC_READ);
+#else
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_NAND_SOFTECC)
nand->ecc.mode = NAND_ECC_SOFT;
#else
nand->ecc.calculate = omap_calculate_ecc;
omap_hwecc_init(nand);
#endif
+#endif
#ifdef CONFIG_SPL_BUILD
if (nand->options & NAND_BUSWIDTH_16)
SUPPORTED_100baseT_Full |
SUPPORTED_1000baseT_Full);
- phydev = phy_connect(priv->bus, 0, dev, slave->data->phy_if);
+ phydev = phy_connect(priv->bus,
+ CONFIG_PHY_ADDR,
+ dev,
+ slave->data->phy_if);
phydev->supported &= supported;
phydev->advertising = phydev->supported;
E1000_WRITE_REG(hw, TXDCTL, ctrl);
}
+ /* Set the receive descriptor write back policy */
+
+ if (hw->mac_type >= e1000_82571) {
+ ctrl = E1000_READ_REG(hw, RXDCTL);
+ ctrl =
+ (ctrl & ~E1000_RXDCTL_WTHRESH) |
+ E1000_RXDCTL_FULL_RX_DESC_WB;
+ E1000_WRITE_REG(hw, RXDCTL, ctrl);
+ }
+
switch (hw->mac_type) {
default:
break;
#define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */
#define E1000_RXDCTL_WTHRESH 0x003F0000 /* RXDCTL Writeback Threshold */
#define E1000_RXDCTL_GRAN 0x01000000 /* RXDCTL Granularity */
+#define E1000_RXDCTL_FULL_RX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
/* Transmit Descriptor Control */
#define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */
.shutdown = &genphy_shutdown,
};
+static struct phy_driver M88E1118R_driver = {
+ .name = "Marvell 88E1118R",
+ .uid = 0x1410e40,
+ .mask = 0xffffff0,
+ .features = PHY_GBIT_FEATURES,
+ .config = &m88e1118_config,
+ .startup = &m88e1118_startup,
+ .shutdown = &genphy_shutdown,
+};
+
static struct phy_driver M88E1121R_driver = {
.name = "Marvell 88E1121R",
.uid = 0x1410cb0,
phy_register(&M88E1145_driver);
phy_register(&M88E1121R_driver);
phy_register(&M88E1118_driver);
+ phy_register(&M88E1118R_driver);
phy_register(&M88E1111S_driver);
phy_register(&M88E1011S_driver);
#include <netdev.h>
#include "mv88e61xx.h"
+/*
+ * Uncomment either of the following line for local debug control;
+ * otherwise global debug control will apply.
+ */
+
+/* #undef DEBUG */
+/* #define DEBUG */
+
#ifdef CONFIG_MV88E61XX_MULTICHIP_ADRMODE
/* Chip Address mode
* The Switch support two modes of operation
return 0;
}
-static void mv88e61xx_wr_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 data)
+static void mv88e61xx_switch_write(char *name, u32 phy_adr,
+ u32 reg_ofs, u16 data)
{
u16 mii_dev_addr;
15));
}
-static void mv88e61xx_rd_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 * data)
+static void mv88e61xx_switch_read(char *name, u32 phy_adr,
+ u32 reg_ofs, u16 *data)
{
u16 mii_dev_addr;
}
#endif /* CONFIG_MV88E61XX_MULTICHIP_ADRMODE */
-static void mv88e61xx_port_vlan_config(struct mv88e61xx_config *swconfig,
- u32 max_prtnum, u32 ports_ofs)
-{
- u32 prt;
- u16 reg;
- char *name = swconfig->name;
- u32 cpu_port = swconfig->cpuport;
- u32 port_mask = swconfig->ports_enabled;
- enum mv88e61xx_cfg_vlan vlancfg = swconfig->vlancfg;
-
- /* be sure all ports are disabled */
- for (prt = 0; prt < max_prtnum; prt++) {
- RD_PHY(name, ports_ofs + prt, MV88E61XX_PRT_CTRL_REG, ®);
- reg &= ~0x3;
- WR_PHY(name, ports_ofs + prt, MV88E61XX_PRT_CTRL_REG, reg);
-
- if (!(cpu_port & (1 << prt)))
- continue;
- /* Set CPU port VID to 0x1 */
- RD_PHY(name, (ports_ofs + prt), MV88E61XX_PRT_VID_REG, ®);
- reg &= ~0xfff;
- reg |= 0x1;
- WR_PHY(name, (ports_ofs + prt), MV88E61XX_PRT_VID_REG, reg);
- }
-
- /* Setting Port default priority for all ports to zero */
- for (prt = 0; prt < max_prtnum; prt++) {
- RD_PHY(name, ports_ofs + prt, MV88E61XX_PRT_VID_REG, ®);
- reg &= ~0xc000;
- WR_PHY(name, ports_ofs + prt, MV88E61XX_PRT_VID_REG, reg);
- }
- /* Setting VID and VID map for all ports except CPU port */
- for (prt = 0; prt < max_prtnum; prt++) {
- /* only for enabled ports */
- if ((1 << prt) & port_mask) {
- /* skip CPU port */
- if ((1 << prt) & cpu_port) {
- /*
- * Set Vlan map table for cpu_port to see
- * all ports
- */
- RD_PHY(name, (ports_ofs + prt),
- MV88E61XX_PRT_VMAP_REG, ®);
- reg &= ~((1 << max_prtnum) - 1);
- reg |= port_mask & ~(1 << prt);
- WR_PHY(name, (ports_ofs + prt),
- MV88E61XX_PRT_VMAP_REG, reg);
- } else {
-
- /*
- * set Ports VLAN Mapping.
- * port prt <--> cpu_port VLAN #prt+1.
- */
- RD_PHY(name, ports_ofs + prt,
- MV88E61XX_PRT_VID_REG, ®);
- reg &= ~0x0fff;
- reg |= (prt + 1);
- WR_PHY(name, ports_ofs + prt,
- MV88E61XX_PRT_VID_REG, reg);
-
- RD_PHY(name, ports_ofs + prt,
- MV88E61XX_PRT_VMAP_REG, ®);
- if (vlancfg == MV88E61XX_VLANCFG_DEFAULT) {
- /*
- * all any port can send frames to all other ports
- * ref: sec 3.2.1.1 of datasheet
- */
- reg |= 0x03f;
- reg &= ~(1 << prt);
- } else if (vlancfg == MV88E61XX_VLANCFG_ROUTER) {
- /*
- * all other ports can send frames to CPU port only
- * ref: sec 3.2.1.2 of datasheet
- */
- reg &= ~((1 << max_prtnum) - 1);
- reg |= cpu_port;
- }
- WR_PHY(name, ports_ofs + prt,
- MV88E61XX_PRT_VMAP_REG, reg);
- }
- }
- }
+/*
+ * Convenience macros for switch device/port reads/writes
+ * These macros output valid 'mv88e61xx' U_BOOT_CMDs
+ */
- /*
- * enable only appropriate ports to forwarding mode
- * and disable the others
- */
- for (prt = 0; prt < max_prtnum; prt++) {
- if ((1 << prt) & port_mask) {
- RD_PHY(name, ports_ofs + prt,
- MV88E61XX_PRT_CTRL_REG, ®);
- reg |= 0x3;
- WR_PHY(name, ports_ofs + prt,
- MV88E61XX_PRT_CTRL_REG, reg);
- } else {
- /* Disable port */
- RD_PHY(name, ports_ofs + prt,
- MV88E61XX_PRT_CTRL_REG, ®);
- reg &= ~0x3;
- WR_PHY(name, ports_ofs + prt,
- MV88E61XX_PRT_CTRL_REG, reg);
- }
- }
+#ifndef DEBUG
+#define WR_SWITCH_REG wr_switch_reg
+#define RD_SWITCH_REG rd_switch_reg
+#define WR_SWITCH_PORT_REG(n, p, r, d) \
+ WR_SWITCH_REG(n, (MV88E61XX_PRT_OFST+p), r, d)
+#define RD_SWITCH_PORT_REG(n, p, r, d) \
+ RD_SWITCH_REG(n, (MV88E61XX_PRT_OFST+p), r, d)
+#else
+static void WR_SWITCH_REG(char *name, u32 dev_adr, u32 reg_ofs, u16 data)
+{
+ printf("mv88e61xx %s dev %02x reg %02x write %04x\n",
+ name, dev_adr, reg_ofs, data);
+ wr_switch_reg(name, dev_adr, reg_ofs, data);
}
+static void RD_SWITCH_REG(char *name, u32 dev_adr, u32 reg_ofs, u16 *data)
+{
+ rd_switch_reg(name, dev_adr, reg_ofs, data);
+ printf("mv88e61xx %s dev %02x reg %02x read %04x\n",
+ name, dev_adr, reg_ofs, *data);
+}
+static void WR_SWITCH_PORT_REG(char *name, u32 prt_adr, u32 reg_ofs,
+ u16 data)
+{
+ printf("mv88e61xx %s port %02x reg %02x write %04x\n",
+ name, prt_adr, reg_ofs, data);
+ wr_switch_reg(name, (MV88E61XX_PRT_OFST+prt_adr), reg_ofs, data);
+}
+static void RD_SWITCH_PORT_REG(char *name, u32 prt_adr, u32 reg_ofs,
+ u16 *data)
+{
+ rd_switch_reg(name, (MV88E61XX_PRT_OFST+prt_adr), reg_ofs, data);
+ printf("mv88e61xx %s port %02x reg %02x read %04x\n",
+ name, prt_adr, reg_ofs, *data);
+}
+#endif
+
+/*
+ * Local functions to read/write registers on the switch PHYs.
+ * NOTE! This goes through switch, not direct miiphy, writes and reads!
+ */
/*
* Make sure SMIBusy bit cleared before another
u16 reg = 0;
u32 timeout = MV88E61XX_PHY_TIMEOUT;
do {
- RD_PHY(name, MV88E61XX_GLB2REG_DEVADR,
+ rd_switch_reg(name, MV88E61XX_GLB2REG_DEVADR,
MV88E61XX_PHY_CMD, ®);
if (timeout-- == 0) {
printf("SMI busy timeout\n");
return 0;
}
+static inline int mv88e61xx_switch_miiphy_write(char *name, u32 phy,
+ u32 reg, u16 data)
+{
+ /* write switch data reg then cmd reg then check completion */
+ wr_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA,
+ data);
+ wr_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_CMD,
+ (MV88E61XX_PHY_WRITE_CMD | (phy << 5) | reg));
+ return mv88e61xx_busychk(name);
+}
+
+static inline int mv88e61xx_switch_miiphy_read(char *name, u32 phy,
+ u32 reg, u16 *data)
+{
+ /* write switch cmd reg, check for completion */
+ wr_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_CMD,
+ (MV88E61XX_PHY_READ_CMD | (phy << 5) | reg));
+ if (mv88e61xx_busychk(name))
+ return -1;
+ /* read switch data reg and return success */
+ rd_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, data);
+ return 0;
+}
+
+/*
+ * Convenience macros for switch PHY reads/writes
+ */
+
+#ifndef DEBUG
+#define WR_SWITCH_PHY_REG mv88e61xx_switch_miiphy_write
+#define RD_SWITCH_PHY_REG mv88e61xx_switch_miiphy_read
+#else
+static inline int WR_SWITCH_PHY_REG(char *name, u32 phy_adr,
+ u32 reg_ofs, u16 data)
+{
+ int r = mv88e61xx_switch_miiphy_write(name, phy_adr, reg_ofs, data);
+ if (r)
+ printf("** ERROR writing mv88e61xx %s phy %02x reg %02x\n",
+ name, phy_adr, reg_ofs);
+ else
+ printf("mv88e61xx %s phy %02x reg %02x write %04x\n",
+ name, phy_adr, reg_ofs, data);
+ return r;
+}
+static inline int RD_SWITCH_PHY_REG(char *name, u32 phy_adr,
+ u32 reg_ofs, u16 *data)
+{
+ int r = mv88e61xx_switch_miiphy_read(name, phy_adr, reg_ofs, data);
+ if (r)
+ printf("** ERROR reading mv88e61xx %s phy %02x reg %02x\n",
+ name, phy_adr, reg_ofs);
+ else
+ printf("mv88e61xx %s phy %02x reg %02x read %04x\n",
+ name, phy_adr, reg_ofs, *data);
+ return r;
+}
+#endif
+
+static void mv88e61xx_port_vlan_config(struct mv88e61xx_config *swconfig)
+{
+ u32 prt;
+ u16 reg;
+ char *name = swconfig->name;
+ u32 port_mask = swconfig->ports_enabled;
+
+ /* apply internal vlan config */
+ for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) {
+ /* only for enabled ports */
+ if ((1 << prt) & port_mask) {
+ /* take vlan map from swconfig */
+ u8 vlanmap = swconfig->vlancfg[prt];
+ /* remove disabled ports from vlan map */
+ vlanmap &= swconfig->ports_enabled;
+ /* apply vlan map to port */
+ RD_SWITCH_PORT_REG(name, prt,
+ MV88E61XX_PRT_VMAP_REG, ®);
+ reg &= ~((1 << MV88E61XX_MAX_PORTS_NUM) - 1);
+ reg |= vlanmap;
+ WR_SWITCH_PORT_REG(name, prt,
+ MV88E61XX_PRT_VMAP_REG, reg);
+ }
+ }
+}
+
/*
* Power up the specified port and reset PHY
*/
-static int mv88361xx_powerup(struct mv88e61xx_config *swconfig, u32 prt)
+static int mv88361xx_powerup(struct mv88e61xx_config *swconfig, u32 phy)
{
char *name = swconfig->name;
- /* Write Copper Specific control reg1 (0x14) for-
+ /* Write Copper Specific control reg1 (0x10) for-
* Enable Phy power up
* Energy Detect on (sense&Xmit NLP Periodically
* reset other settings default
*/
- WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, 0x3360);
- WR_PHY(name, MV88E61XX_GLB2REG_DEVADR,
- MV88E61XX_PHY_CMD, (0x9410 | (prt << 5)));
-
- if (mv88e61xx_busychk(name))
+ if (WR_SWITCH_PHY_REG(name, phy, 0x10, 0x3360))
return -1;
/* Write PHY ctrl reg (0x0) to apply
* Phy reset (set bit 15 low)
* reset other default values
*/
- WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, 0x1140);
- WR_PHY(name, MV88E61XX_GLB2REG_DEVADR,
- MV88E61XX_PHY_CMD, (0x9400 | (prt << 5)));
-
- if (mv88e61xx_busychk(name))
+ if (WR_SWITCH_PHY_REG(name, phy, 0x00, 0x9140))
return -1;
return 0;
* to setup PHY LEDs default configuration to detect 10/100/1000Mb/s
* Link status
*/
-static int mv88361xx_led_init(struct mv88e61xx_config *swconfig, u32 prt)
+static int mv88361xx_led_init(struct mv88e61xx_config *swconfig, u32 phy)
{
char *name = swconfig->name;
- u16 reg;
if (swconfig->led_init != MV88E61XX_LED_INIT_EN)
return 0;
/* set page address to 3 */
- reg = 3;
- WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, reg);
- WR_PHY(name, MV88E61XX_GLB2REG_DEVADR,
- MV88E61XX_PHY_CMD, (1 << MV88E61XX_BUSY_OFST |
- 1 << MV88E61XX_MODE_OFST |
- 1 << MV88E61XX_OP_OFST |
- prt << MV88E61XX_ADDR_OFST | 22));
-
- if (mv88e61xx_busychk(name))
+ if (WR_SWITCH_PHY_REG(name, phy, 0x16, 0x0003))
return -1;
- /* set LED Func Ctrl reg */
- reg = 1; /* LED[0] On-Link, Blink-Activity, Off-NoLink */
- WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, reg);
- WR_PHY(name, MV88E61XX_GLB2REG_DEVADR,
- MV88E61XX_PHY_CMD, (1 << MV88E61XX_BUSY_OFST |
- 1 << MV88E61XX_MODE_OFST |
- 1 << MV88E61XX_OP_OFST |
- prt << MV88E61XX_ADDR_OFST | 16));
-
- if (mv88e61xx_busychk(name))
+ /*
+ * set LED Func Ctrl reg
+ * value 0x0001 = LED[0] On-Link, Blink-Activity, Off-NoLink
+ */
+ if (WR_SWITCH_PHY_REG(name, phy, 0x10, 0x0001))
return -1;
/* set page address to 0 */
- reg = 0;
- WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, reg);
- WR_PHY(name, MV88E61XX_GLB2REG_DEVADR,
- MV88E61XX_PHY_CMD, (1 << MV88E61XX_BUSY_OFST |
- 1 << MV88E61XX_MODE_OFST |
- 1 << MV88E61XX_OP_OFST |
- prt << MV88E61XX_ADDR_OFST | 22));
-
- if (mv88e61xx_busychk(name))
+ if (WR_SWITCH_PHY_REG(name, phy, 0x16, 0x0000))
return -1;
return 0;
* This is optional settings may be needed on some boards
* for PHY<->magnetics h/w tuning
*/
-static int mv88361xx_reverse_mdipn(struct mv88e61xx_config *swconfig, u32 prt)
+static int mv88361xx_reverse_mdipn(struct mv88e61xx_config *swconfig, u32 phy)
{
char *name = swconfig->name;
- u16 reg;
if (swconfig->mdip != MV88E61XX_MDIP_REVERSE)
return 0;
- reg = 0x0f; /*Reverse MDIP/N[3:0] bits */
- WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, reg);
- WR_PHY(name, MV88E61XX_GLB2REG_DEVADR,
- MV88E61XX_PHY_CMD, (1 << MV88E61XX_BUSY_OFST |
- 1 << MV88E61XX_MODE_OFST |
- 1 << MV88E61XX_OP_OFST |
- prt << MV88E61XX_ADDR_OFST | 20));
-
- if (mv88e61xx_busychk(name))
+ /*Reverse MDIP/N[3:0] bits */
+ if (WR_SWITCH_PHY_REG(name, phy, 0x14, 0x000f))
return -1;
return 0;
u16 reg;
char *idstr;
char *name = swconfig->name;
+ int time;
if (miiphy_set_current_dev(name)) {
printf("%s failed\n", __FUNCTION__);
printf("Invalid cpu port config, using default port5\n");
}
- RD_PHY(name, MV88E61XX_PRT_OFST, MII_PHYSID2, ®);
+ RD_SWITCH_PORT_REG(name, 0, MII_PHYSID2, ®);
switch (reg &= 0xfff0) {
case 0x1610:
idstr = "88E6161";
break;
}
- /* Port based VLANs configuration */
- if ((swconfig->vlancfg == MV88E61XX_VLANCFG_DEFAULT)
- || (swconfig->vlancfg == MV88E61XX_VLANCFG_ROUTER))
- mv88e61xx_port_vlan_config(swconfig, MV88E61XX_MAX_PORTS_NUM,
- MV88E61XX_PRT_OFST);
- else {
- printf("Unsupported mode %s failed\n", __FUNCTION__);
- return -1;
+ /* be sure all ports are disabled */
+ for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) {
+ RD_SWITCH_PORT_REG(name, prt, MV88E61XX_PRT_CTRL_REG, ®);
+ reg &= ~0x3;
+ WR_SWITCH_PORT_REG(name, prt, MV88E61XX_PRT_CTRL_REG, reg);
}
+ /* wait 2 ms for queues to drain */
+ udelay(2000);
+
+ /* reset switch */
+ RD_SWITCH_REG(name, MV88E61XX_GLBREG_DEVADR, MV88E61XX_SGCR, ®);
+ reg |= 0x8000;
+ WR_SWITCH_REG(name, MV88E61XX_GLBREG_DEVADR, MV88E61XX_SGCR, reg);
+
+ /* wait up to 1 second for switch reset complete */
+ for (time = 1000; time; time--) {
+ RD_SWITCH_REG(name, MV88E61XX_GLBREG_DEVADR, MV88E61XX_SGSR,
+ ®);
+ if ((reg & 0xc800) == 0xc800)
+ break;
+ udelay(1000);
+ }
+ if (!time)
+ return -1;
+
+ /* Port based VLANs configuration */
+ mv88e61xx_port_vlan_config(swconfig);
+
if (swconfig->rgmii_delay == MV88E61XX_RGMII_DELAY_EN) {
/*
* Enable RGMII delay on Tx and Rx for CPU port
* Ref: sec 9.5 of chip datasheet-02
*/
- WR_PHY(name, MV88E61XX_PRT_OFST + 5,
- MV88E61XX_RGMII_TIMECTRL_REG, 0x18);
- WR_PHY(name, MV88E61XX_PRT_OFST + 4,
- MV88E61XX_RGMII_TIMECTRL_REG, 0xc1e7);
+ /*Force port link down */
+ WR_SWITCH_PORT_REG(name, 5, MV88E61XX_PCS_CTRL_REG, 0x10);
+ /* configure port RGMII delay */
+ WR_SWITCH_PORT_REG(name, 4,
+ MV88E61XX_RGMII_TIMECTRL_REG, 0x81e7);
+ RD_SWITCH_PORT_REG(name, 5,
+ MV88E61XX_RGMII_TIMECTRL_REG, ®);
+ WR_SWITCH_PORT_REG(name, 5,
+ MV88E61XX_RGMII_TIMECTRL_REG, reg | 0x18);
+ WR_SWITCH_PORT_REG(name, 4,
+ MV88E61XX_RGMII_TIMECTRL_REG, 0xc1e7);
+ /* Force port to RGMII FDX 1000Base then up */
+ WR_SWITCH_PORT_REG(name, 5, MV88E61XX_PCS_CTRL_REG, 0x1e);
+ WR_SWITCH_PORT_REG(name, 5, MV88E61XX_PCS_CTRL_REG, 0x3e);
}
for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) {
- if (!((1 << prt) & swconfig->cpuport)) {
- if (mv88361xx_led_init(swconfig, prt))
+ /* configure port's PHY */
+ if (!((1 << prt) & swconfig->cpuport)) {
+ /* port 4 has phy 6, not 4 */
+ int phy = (prt == 4) ? 6 : prt;
+ if (mv88361xx_powerup(swconfig, phy))
return -1;
- if (mv88361xx_reverse_mdipn(swconfig, prt))
+ if (mv88361xx_reverse_mdipn(swconfig, phy))
return -1;
- if (mv88361xx_powerup(swconfig, prt))
+ if (mv88361xx_led_init(swconfig, phy))
return -1;
}
+ /* set port VID to port+1 except for cpu port */
+ if (!((1 << prt) & swconfig->cpuport)) {
+ RD_SWITCH_PORT_REG(name, prt,
+ MV88E61XX_PRT_VID_REG, ®);
+ WR_SWITCH_PORT_REG(name, prt,
+ MV88E61XX_PRT_VID_REG,
+ (reg & ~1023) | (prt+1));
+ }
+
/*Program port state */
- RD_PHY(name, MV88E61XX_PRT_OFST + prt,
- MV88E61XX_PRT_CTRL_REG, ®);
- WR_PHY(name, MV88E61XX_PRT_OFST + prt,
- MV88E61XX_PRT_CTRL_REG,
- reg | (swconfig->portstate & 0x03));
+ RD_SWITCH_PORT_REG(name, prt,
+ MV88E61XX_PRT_CTRL_REG, ®);
+ WR_SWITCH_PORT_REG(name, prt,
+ MV88E61XX_PRT_CTRL_REG,
+ reg | (swconfig->portstate & 0x03));
+
}
printf("%s Initialized on %s\n", idstr, name);
return 0;
}
+
+#ifdef CONFIG_MV88E61XX_CMD
+static int
+do_switch(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ char *name, *endp;
+ int write = 0;
+ enum { dev, prt, phy } target = dev;
+ u32 addrlo, addrhi, addr;
+ u32 reglo, reghi, reg;
+ u16 data, rdata;
+
+ if (argc < 7)
+ return -1;
+
+ name = argv[1];
+
+ if (strcmp(argv[2], "phy") == 0)
+ target = phy;
+ else if (strcmp(argv[2], "port") == 0)
+ target = prt;
+ else if (strcmp(argv[2], "dev") != 0)
+ return 1;
+
+ addrlo = simple_strtoul(argv[3], &endp, 16);
+
+ if (!*endp) {
+ addrhi = addrlo;
+ } else {
+ while (*endp < '0' || *endp > '9')
+ endp++;
+ addrhi = simple_strtoul(endp, NULL, 16);
+ }
+
+ reglo = simple_strtoul(argv[5], &endp, 16);
+ if (!*endp) {
+ reghi = reglo;
+ } else {
+ while (*endp < '0' || *endp > '9')
+ endp++;
+ reghi = simple_strtoul(endp, NULL, 16);
+ }
+
+ if (strcmp(argv[6], "write") == 0)
+ write = 1;
+ else if (strcmp(argv[6], "read") != 0)
+ return 1;
+
+ data = simple_strtoul(argv[7], NULL, 16);
+
+ for (addr = addrlo; addr <= addrhi; addr++) {
+ for (reg = reglo; reg <= reghi; reg++) {
+ if (write) {
+ if (target == phy)
+ mv88e61xx_switch_miiphy_write(
+ name, addr, reg, data);
+ else if (target == prt)
+ wr_switch_reg(name,
+ addr+MV88E61XX_PRT_OFST,
+ reg, data);
+ else
+ wr_switch_reg(name, addr, reg, data);
+ } else {
+ if (target == phy)
+ mv88e61xx_switch_miiphy_read(
+ name, addr, reg, &rdata);
+ else if (target == prt)
+ rd_switch_reg(name,
+ addr+MV88E61XX_PRT_OFST,
+ reg, &rdata);
+ else
+ rd_switch_reg(name, addr, reg, &rdata);
+ printf("%s %s %s %02x %s %02x %s %04x\n",
+ argv[0], argv[1], argv[2], addr,
+ argv[4], reg, argv[6], rdata);
+ if (write && argc == 7 && rdata != data)
+ return 1;
+ }
+ }
+ }
+ return 0;
+}
+
+U_BOOT_CMD(mv88e61xx, 8, 0, do_switch,
+ "Read or write mv88e61xx switch registers",
+ "<ethdevice> dev|port|phy <addr> reg <reg> write <data>\n"
+ "<ethdevice> dev|port|phy <addr> reg <reg> read [<data>]\n"
+ " - read/write switch device, port or phy at (addr,reg)\n"
+ " addr=0..0x1C for dev, 0..5 for port or phy.\n"
+ " reg=0..0x1F.\n"
+ " data=0..0xFFFF (tested if present against actual read).\n"
+ " All numeric parameters are assumed to be hex.\n"
+ " <addr> and <<reg> arguments can be ranges (x..y)"
+);
+#endif /* CONFIG_MV88E61XX_CMD */
#include <miiphy.h>
#define MV88E61XX_CPU_PORT 0x5
-#define MV88E61XX_MAX_PORTS_NUM 0x6
#define MV88E61XX_PHY_TIMEOUT 100000
-#define MV88E61XX_PRT_STS_REG 0x1
+/* port dev-addr (= port + 0x10) */
+#define MV88E61XX_PRT_OFST 0x10
+/* port registers */
+#define MV88E61XX_PCS_CTRL_REG 0x1
#define MV88E61XX_PRT_CTRL_REG 0x4
#define MV88E61XX_PRT_VMAP_REG 0x6
#define MV88E61XX_PRT_VID_REG 0x7
+#define MV88E61XX_RGMII_TIMECTRL_REG 0x1A
-#define MV88E61XX_PRT_OFST 0x10
+/* global registers dev-addr */
+#define MV88E61XX_GLBREG_DEVADR 0x1B
+/* global registers */
+#define MV88E61XX_SGSR 0x00
+#define MV88E61XX_SGCR 0x04
+
+/* global 2 registers dev-addr */
+#define MV88E61XX_GLB2REG_DEVADR 0x1C
+/* global 2 registers */
#define MV88E61XX_PHY_CMD 0x18
#define MV88E61XX_PHY_DATA 0x19
-#define MV88E61XX_RGMII_TIMECTRL_REG 0x1A
-#define MV88E61XX_GLB2REG_DEVADR 0x1C
+/* global 2 phy commands */
+#define MV88E61XX_PHY_WRITE_CMD 0x9400
+#define MV88E61XX_PHY_READ_CMD 0x9800
#define MV88E61XX_BUSY_OFST 15
#define MV88E61XX_MODE_OFST 12
-#define MV88E61XX_OP_OFST 10
+#define MV88E61XX_OP_OFST 10
#define MV88E61XX_ADDR_OFST 5
#ifdef CONFIG_MV88E61XX_MULTICHIP_ADRMODE
static int mv88e61xx_busychk_multic(char *name, u32 devaddr);
-static void mv88e61xx_wr_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 data);
-static void mv88e61xx_rd_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 * data);
-#define WR_PHY mv88e61xx_wr_phy
-#define RD_PHY mv88e61xx_rd_phy
+static void mv88e61xx_switch_write(char *name, u32 phy_adr,
+ u32 reg_ofs, u16 data);
+static void mv88e61xx_switch_read(char *name, u32 phy_adr,
+ u32 reg_ofs, u16 *data);
+#define wr_switch_reg mv88e61xx_switch_write
+#define rd_switch_reg mv88e61xx_switch_read
#else
-#define WR_PHY miiphy_write
-#define RD_PHY miiphy_read
+/* switch appears a s simple PHY and can thus use miiphy */
+#define wr_switch_reg miiphy_write
+#define rd_switch_reg miiphy_read
#endif /* CONFIG_MV88E61XX_MULTICHIP_ADRMODE */
#endif /* _MV88E61XX_H */
printf(SHETHER_NAME ": 100Base/");
#if defined(SH_ETH_TYPE_GETHER)
sh_eth_write(eth, GECMR_100B, GECMR);
-#elif defined(CONFIG_CPU_SH7757)
+#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
sh_eth_write(eth, 1, RTRATE);
#elif defined(CONFIG_CPU_SH7724)
val = ECMR_RTM;
printf(SHETHER_NAME ": 10Base/");
#if defined(SH_ETH_TYPE_GETHER)
sh_eth_write(eth, GECMR_10B, GECMR);
-#elif defined(CONFIG_CPU_SH7757)
+#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
sh_eth_write(eth, 0, RTRATE);
#endif
}
#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
#define SH_ETH_TYPE_GETHER
#define BASE_IO_ADDR 0xfee00000
-#elif defined(CONFIG_CPU_SH7757)
+#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
#if defined(CONFIG_SH_ETHER_USE_GETHER)
#define SH_ETH_TYPE_GETHER
#define BASE_IO_ADDR 0xfee00000
/* GECMR */
enum GECMR_BIT {
-#if defined(CONFIG_CPU_SH7757)
+#if defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
GECMR_1000B = 0x20, GECMR_100B = 0x01, GECMR_10B = 0x00,
#else
GECMR_1000B = 0x01, GECMR_100B = 0x04, GECMR_10B = 0x00,
COBJS-$(CONFIG_POWER_MAX8998) += pmic_max8998.o
COBJS-$(CONFIG_POWER_MAX8997) += pmic_max8997.o
COBJS-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o
+COBJS-$(CONFIG_POWER_MAX77686) += pmic_max77686.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
--- /dev/null
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ * Rajeshwari Shinde <rajeshwari.s@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <power/max77686_pmic.h>
+#include <errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int pmic_init(unsigned char bus)
+{
+ static const char name[] = "MAX77686_PMIC";
+ struct pmic *p = pmic_alloc();
+
+ if (!p) {
+ printf("%s: POWER allocation error!\n", __func__);
+ return -ENOMEM;
+ }
+
+#ifdef CONFIG_OF_CONTROL
+ const void *blob = gd->fdt_blob;
+ int node, parent;
+
+ node = fdtdec_next_compatible(blob, 0, COMPAT_MAXIM_MAX77686_PMIC);
+ if (node < 0) {
+ debug("PMIC: No node for PMIC Chip in device tree\n");
+ debug("node = %d\n", node);
+ return -1;
+ }
+
+ parent = fdt_parent_offset(blob, node);
+ if (parent < 0) {
+ debug("%s: Cannot find node parent\n", __func__);
+ return -1;
+ }
+
+ p->bus = i2c_get_bus_num_fdt(parent);
+ if (p->bus < 0) {
+ debug("%s: Cannot find I2C bus\n", __func__);
+ return -1;
+ }
+ p->hw.i2c.addr = fdtdec_get_int(blob, node, "reg", 9);
+#else
+ p->bus = bus;
+ p->hw.i2c.addr = MAX77686_I2C_ADDR;
+#endif
+
+ p->name = name;
+ p->interface = PMIC_I2C;
+ p->number_of_regs = PMIC_NUM_OF_REGS;
+ p->hw.i2c.tx_num = 1;
+
+ puts("Board PMIC init\n");
+
+ return 0;
+}
#include <fsl_pmic.h>
#include <errno.h>
+#if defined(CONFIG_PMIC_FSL_MC13892)
+#define FSL_PMIC_I2C_LENGTH 3
+#elif defined(CONFIG_PMIC_FSL_MC34704)
+#define FSL_PMIC_I2C_LENGTH 1
+#endif
+
#if defined(CONFIG_POWER_SPI)
static u32 pmic_spi_prepare_tx(u32 reg, u32 *val, u32 write)
{
#elif defined(CONFIG_POWER_I2C)
p->interface = PMIC_I2C;
p->hw.i2c.addr = CONFIG_SYS_FSL_PMIC_I2C_ADDR;
- p->hw.i2c.tx_num = 3;
+ p->hw.i2c.tx_num = FSL_PMIC_I2C_LENGTH;
p->bus = bus;
#else
#error "You must select CONFIG_POWER_SPI or CONFIG_PMIC_I2C"
ret = twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, vsel_val,
vsel_reg);
if (ret != 0) {
- printf("Could could not write vsel to reg %02x (%d)\n",
+ printf("Could not write vsel to reg %02x (%d)\n",
vsel_reg, ret);
return;
}
ret = twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, dev_grp_sel,
dev_grp);
if (ret != 0)
- printf("Could could not write grp_sel to reg %02x (%d)\n",
+ printf("Could not write grp_sel to reg %02x (%d)\n",
dev_grp, ret);
}
return;
}
-void twl6035_mmc1_poweron_ldo(void)
+int twl6035_mmc1_poweron_ldo(void)
{
u8 val = 0;
/* set LDO9 TWL6035 to 3V */
val = 0x2b; /* (3 -.9)*28 +1 */
- palmas_write_u8(0x48, LDO9_VOLTAGE, val);
+
+ if (palmas_write_u8(0x48, LDO9_VOLTAGE, val)) {
+ printf("twl6035: could not set LDO9 voltage.\n");
+ return 1;
+ }
/* TURN ON LDO9 */
val = LDO_ON | LDO_MODE_SLEEP | LDO_MODE_ACTIVE;
- palmas_write_u8(0x48, LDO9_CTRL, val);
- return;
+
+ if (palmas_write_u8(0x48, LDO9_CTRL, val)) {
+ printf("twl6035: could not turn on LDO9.\n");
+ return 1;
+ }
+
+ return 0;
}
void NS16550_init(NS16550_t com_port, int baud_divisor)
{
+#if (!defined(CONFIG_SYS_NS16550_BROKEN_TEMT))
while (!(serial_in(&com_port->lsr) & UART_LSR_TEMT))
;
+#endif
serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier);
#if (defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)) || \
*/
#include <common.h>
-
+#include <linux/compiler.h>
+#include <serial.h>
#include <asm/arch/s3c6400.h>
DECLARE_GLOBAL_DATA_PTR;
#elif defined(CONFIG_H8S2678)
# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
# define H8300_SCI_DR(ch) (*(volatile char *)(P1DR + h8300_sci_pins[ch].port))
-#elif defined(CONFIG_CPU_SH7757)
+#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
# define SCSPTR0 0xfe4b0020
# define SCSPTR1 0xfe4b0020
# define SCSPTR2 0xfe4b0020
--- /dev/null
+#
+# Copyright (C) 2012 Samsung Electronics
+# R. Chandrasekar <rcsekar@samsung.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB := $(obj)libsound.o
+
+COBJS-$(CONFIG_SOUND) += sound.o
+COBJS-$(CONFIG_I2S) += samsung-i2s.o
+COBJS-$(CONFIG_SOUND_WM8994) += wm8994.o
+
+COBJS := $(COBJS-y)
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+all: $(LIB)
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
--- /dev/null
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ * R. Chandrasekar <rcsekar@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/clk.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/i2s-regs.h>
+#include <asm/io.h>
+#include <common.h>
+#include <sound.h>
+#include <i2s.h>
+
+#define FIC_TX2COUNT(x) (((x) >> 24) & 0xf)
+#define FIC_TX1COUNT(x) (((x) >> 16) & 0xf)
+#define FIC_TXCOUNT(x) (((x) >> 8) & 0xf)
+#define FIC_RXCOUNT(x) (((x) >> 0) & 0xf)
+#define FICS_TXCOUNT(x) (((x) >> 8) & 0x7f)
+
+#define TIMEOUT_I2S_TX 100 /* i2s transfer timeout */
+
+/*
+ * Sets the frame size for I2S LR clock
+ *
+ * @param i2s_reg i2s regiter address
+ * @param rfs Frame Size
+ */
+static void i2s_set_lr_framesize(struct i2s_reg *i2s_reg, unsigned int rfs)
+{
+ unsigned int mod = readl(&i2s_reg->mod);
+
+ mod &= ~MOD_RCLK_MASK;
+
+ switch (rfs) {
+ case 768:
+ mod |= MOD_RCLK_768FS;
+ break;
+ case 512:
+ mod |= MOD_RCLK_512FS;
+ break;
+ case 384:
+ mod |= MOD_RCLK_384FS;
+ break;
+ default:
+ mod |= MOD_RCLK_256FS;
+ break;
+ }
+
+ writel(mod, &i2s_reg->mod);
+}
+
+/*
+ * Sets the i2s transfer control
+ *
+ * @param i2s_reg i2s regiter address
+ * @param on 1 enable tx , 0 disable tx transfer
+ */
+static void i2s_txctrl(struct i2s_reg *i2s_reg, int on)
+{
+ unsigned int con = readl(&i2s_reg->con);
+ unsigned int mod = readl(&i2s_reg->mod) & ~MOD_MASK;
+
+ if (on) {
+ con |= CON_ACTIVE;
+ con &= ~CON_TXCH_PAUSE;
+
+ } else {
+
+ con |= CON_TXCH_PAUSE;
+ con &= ~CON_ACTIVE;
+ }
+
+ writel(mod, &i2s_reg->mod);
+ writel(con, &i2s_reg->con);
+}
+
+/*
+ * set the bit clock frame size (in multiples of LRCLK)
+ *
+ * @param i2s_reg i2s regiter address
+ * @param bfs bit Frame Size
+ */
+static void i2s_set_bitclk_framesize(struct i2s_reg *i2s_reg, unsigned bfs)
+{
+ unsigned int mod = readl(&i2s_reg->mod);
+
+ mod &= ~MOD_BCLK_MASK;
+
+ switch (bfs) {
+ case 48:
+ mod |= MOD_BCLK_48FS;
+ break;
+ case 32:
+ mod |= MOD_BCLK_32FS;
+ break;
+ case 24:
+ mod |= MOD_BCLK_24FS;
+ break;
+ case 16:
+ mod |= MOD_BCLK_16FS;
+ break;
+ default:
+ return;
+ }
+ writel(mod, &i2s_reg->mod);
+}
+
+/*
+ * flushes the i2stx fifo
+ *
+ * @param i2s_reg i2s regiter address
+ * @param flush Tx fifo flush command (0x00 - do not flush
+ * 0x80 - flush tx fifo)
+ */
+void i2s_fifo(struct i2s_reg *i2s_reg, unsigned int flush)
+{
+ /* Flush the FIFO */
+ setbits_le32(&i2s_reg->fic, flush);
+ clrbits_le32(&i2s_reg->fic, flush);
+}
+
+/*
+ * Set System Clock direction
+ *
+ * @param i2s_reg i2s regiter address
+ * @param dir Clock direction
+ *
+ * @return int value 0 for success, -1 in case of error
+ */
+int i2s_set_sysclk_dir(struct i2s_reg *i2s_reg, int dir)
+{
+ unsigned int mod = readl(&i2s_reg->mod);
+
+ if (dir == SND_SOC_CLOCK_IN)
+ mod |= MOD_CDCLKCON;
+ else
+ mod &= ~MOD_CDCLKCON;
+
+ writel(mod, &i2s_reg->mod);
+
+ return 0;
+}
+
+/*
+ * Sets I2S Clcok format
+ *
+ * @param fmt i2s clock properties
+ * @param i2s_reg i2s regiter address
+ *
+ * @return int value 0 for success, -1 in case of error
+ */
+int i2s_set_fmt(struct i2s_reg *i2s_reg, unsigned int fmt)
+{
+ unsigned int mod = readl(&i2s_reg->mod);
+ unsigned int tmp = 0;
+ unsigned int ret = 0;
+
+ /* Format is priority */
+ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+ case SND_SOC_DAIFMT_RIGHT_J:
+ tmp |= MOD_LR_RLOW;
+ tmp |= MOD_SDF_MSB;
+ break;
+ case SND_SOC_DAIFMT_LEFT_J:
+ tmp |= MOD_LR_RLOW;
+ tmp |= MOD_SDF_LSB;
+ break;
+ case SND_SOC_DAIFMT_I2S:
+ tmp |= MOD_SDF_IIS;
+ break;
+ default:
+ debug("%s: Invalid format priority [0x%x]\n", __func__,
+ (fmt & SND_SOC_DAIFMT_FORMAT_MASK));
+ return -1;
+ }
+
+ /*
+ * INV flag is relative to the FORMAT flag - if set it simply
+ * flips the polarity specified by the Standard
+ */
+ switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+ case SND_SOC_DAIFMT_NB_NF:
+ break;
+ case SND_SOC_DAIFMT_NB_IF:
+ if (tmp & MOD_LR_RLOW)
+ tmp &= ~MOD_LR_RLOW;
+ else
+ tmp |= MOD_LR_RLOW;
+ break;
+ default:
+ debug("%s: Invalid clock ploarity input [0x%x]\n", __func__,
+ (fmt & SND_SOC_DAIFMT_INV_MASK));
+ return -1;
+ }
+
+ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+ case SND_SOC_DAIFMT_CBS_CFS:
+ tmp |= MOD_SLAVE;
+ break;
+ case SND_SOC_DAIFMT_CBM_CFM:
+ /* Set default source clock in Master mode */
+ ret = i2s_set_sysclk_dir(i2s_reg, SND_SOC_CLOCK_OUT);
+ if (ret != 0) {
+ debug("%s:set i2s clock direction failed\n", __func__);
+ return -1;
+ }
+ break;
+ default:
+ debug("%s: Invalid master selection [0x%x]\n", __func__,
+ (fmt & SND_SOC_DAIFMT_MASTER_MASK));
+ return -1;
+ }
+
+ mod &= ~(MOD_SDF_MASK | MOD_LR_RLOW | MOD_SLAVE);
+ mod |= tmp;
+ writel(mod, &i2s_reg->mod);
+
+ return 0;
+}
+
+/*
+ * Sets the sample width in bits
+ *
+ * @param blc samplewidth (size of sample in bits)
+ * @param i2s_reg i2s regiter address
+ *
+ * @return int value 0 for success, -1 in case of error
+ */
+int i2s_set_samplesize(struct i2s_reg *i2s_reg, unsigned int blc)
+{
+ unsigned int mod = readl(&i2s_reg->mod);
+
+ mod &= ~MOD_BLCP_MASK;
+ mod &= ~MOD_BLC_MASK;
+
+ switch (blc) {
+ case 8:
+ mod |= MOD_BLCP_8BIT;
+ mod |= MOD_BLC_8BIT;
+ break;
+ case 16:
+ mod |= MOD_BLCP_16BIT;
+ mod |= MOD_BLC_16BIT;
+ break;
+ case 24:
+ mod |= MOD_BLCP_24BIT;
+ mod |= MOD_BLC_24BIT;
+ break;
+ default:
+ debug("%s: Invalid sample size input [0x%x]\n",
+ __func__, blc);
+ return -1;
+ }
+ writel(mod, &i2s_reg->mod);
+
+ return 0;
+}
+
+int i2s_transfer_tx_data(struct i2stx_info *pi2s_tx, unsigned int *data,
+ unsigned long data_size)
+{
+ int i;
+ int start;
+ struct i2s_reg *i2s_reg =
+ (struct i2s_reg *)pi2s_tx->base_address;
+
+ if (data_size < FIFO_LENGTH) {
+ debug("%s : Invalid data size\n", __func__);
+ return -1; /* invalid pcm data size */
+ }
+
+ /* fill the tx buffer before stating the tx transmit */
+ for (i = 0; i < FIFO_LENGTH; i++)
+ writel(*data++, &i2s_reg->txd);
+
+ data_size -= FIFO_LENGTH;
+ i2s_txctrl(i2s_reg, I2S_TX_ON);
+
+ while (data_size > 0) {
+ start = get_timer(0);
+ if (!(CON_TXFIFO_FULL & (readl(&i2s_reg->con)))) {
+ writel(*data++, &i2s_reg->txd);
+ data_size--;
+ } else {
+ if (get_timer(start) > TIMEOUT_I2S_TX) {
+ i2s_txctrl(i2s_reg, I2S_TX_OFF);
+ debug("%s: I2S Transfer Timeout\n", __func__);
+ return -1;
+ }
+ }
+ }
+ i2s_txctrl(i2s_reg, I2S_TX_OFF);
+
+ return 0;
+}
+
+int i2s_tx_init(struct i2stx_info *pi2s_tx)
+{
+ int ret;
+ struct i2s_reg *i2s_reg =
+ (struct i2s_reg *)pi2s_tx->base_address;
+
+ /* Initialize GPIO for I2s */
+ exynos_pinmux_config(PERIPH_ID_I2S1, 0);
+
+ /* Set EPLL Clock */
+ ret = set_epll_clk(pi2s_tx->audio_pll_clk);
+ if (ret != 0) {
+ debug("%s: epll clock set rate falied\n", __func__);
+ return -1;
+ }
+
+ /* Select Clk Source for Audio1 */
+ set_i2s_clk_source();
+
+ /* Set Prescaler to get MCLK */
+ set_i2s_clk_prescaler(pi2s_tx->audio_pll_clk,
+ (pi2s_tx->samplingrate * (pi2s_tx->rfs)));
+
+ /* Configure I2s format */
+ ret = i2s_set_fmt(i2s_reg, (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
+ SND_SOC_DAIFMT_CBM_CFM));
+ if (ret == 0) {
+ i2s_set_lr_framesize(i2s_reg, pi2s_tx->rfs);
+ ret = i2s_set_samplesize(i2s_reg, pi2s_tx->bitspersample);
+ if (ret != 0) {
+ debug("%s:set sample rate failed\n", __func__);
+ return -1;
+ }
+
+ i2s_set_bitclk_framesize(i2s_reg, pi2s_tx->bfs);
+ /* disable i2s transfer flag and flush the fifo */
+ i2s_txctrl(i2s_reg, I2S_TX_OFF);
+ i2s_fifo(i2s_reg, FIC_TXFLUSH);
+ } else {
+ debug("%s: failed\n", __func__);
+ }
+
+ return ret;
+}
--- /dev/null
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ * R. Chandrasekar <rcsekar@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <malloc.h>
+#include <common.h>
+#include <asm/io.h>
+#include <libfdt.h>
+#include <fdtdec.h>
+#include <i2c.h>
+#include <i2s.h>
+#include <sound.h>
+#include <asm/arch/sound.h>
+#include "wm8994.h"
+
+/* defines */
+#define SOUND_400_HZ 400
+#define SOUND_BITS_IN_BYTE 8
+
+static struct i2stx_info g_i2stx_pri;
+
+/*
+ * get_sound_i2s_values gets values for i2s parameters
+ *
+ * @param i2stx_info i2s transmitter transfer param structure
+ * @param blob FDT blob if enabled else NULL
+ */
+static int get_sound_i2s_values(struct i2stx_info *i2s, const void *blob)
+{
+#ifdef CONFIG_OF_CONTROL
+ int node;
+ int error = 0;
+ int base;
+
+ node = fdtdec_next_compatible(blob, 0,
+ COMPAT_SAMSUNG_EXYNOS5_SOUND);
+ if (node <= 0) {
+ debug("EXYNOS_SOUND: No node for sound in device tree\n");
+ return -1;
+ }
+
+ /*
+ * Get the pre-defined sound specific values from FDT.
+ * All of these are expected to be correct otherwise
+ * wrong register values in i2s setup parameters
+ * may result in no sound play.
+ */
+ base = fdtdec_get_addr(blob, node, "reg");
+ if (base == FDT_ADDR_T_NONE) {
+ debug("%s: Missing i2s base\n", __func__);
+ return -1;
+ }
+ i2s->base_address = base;
+
+ i2s->audio_pll_clk = fdtdec_get_int(blob,
+ node, "samsung,i2s-epll-clock-frequency", -1);
+ error |= i2s->audio_pll_clk;
+ debug("audio_pll_clk = %d\n", i2s->audio_pll_clk);
+ i2s->samplingrate = fdtdec_get_int(blob,
+ node, "samsung,i2s-sampling-rate", -1);
+ error |= i2s->samplingrate;
+ debug("samplingrate = %d\n", i2s->samplingrate);
+ i2s->bitspersample = fdtdec_get_int(blob,
+ node, "samsung,i2s-bits-per-sample", -1);
+ error |= i2s->bitspersample;
+ debug("bitspersample = %d\n", i2s->bitspersample);
+ i2s->channels = fdtdec_get_int(blob,
+ node, "samsung,i2s-channels", -1);
+ error |= i2s->channels;
+ debug("channels = %d\n", i2s->channels);
+ i2s->rfs = fdtdec_get_int(blob,
+ node, "samsung,i2s-lr-clk-framesize", -1);
+ error |= i2s->rfs;
+ debug("rfs = %d\n", i2s->rfs);
+ i2s->bfs = fdtdec_get_int(blob,
+ node, "samsung,i2s-bit-clk-framesize", -1);
+ error |= i2s->bfs;
+ debug("bfs = %d\n", i2s->bfs);
+ if (error == -1) {
+ debug("fail to get sound i2s node properties\n");
+ return -1;
+ }
+#else
+ i2s->base_address = samsung_get_base_i2s();
+ i2s->audio_pll_clk = I2S_PLL_CLK;
+ i2s->samplingrate = I2S_SAMPLING_RATE;
+ i2s->bitspersample = I2S_BITS_PER_SAMPLE;
+ i2s->channels = I2S_CHANNELS;
+ i2s->rfs = I2S_RFS;
+ i2s->bfs = I2S_BFS;
+#endif
+ return 0;
+}
+
+/*
+ * Init codec
+ *
+ * @param blob FDT blob
+ * @param pi2s_tx i2s parameters required by codec
+ * @return int value, 0 for success
+ */
+static int codec_init(const void *blob, struct i2stx_info *pi2s_tx)
+{
+ int ret;
+ const char *codectype;
+#ifdef CONFIG_OF_CONTROL
+ int node;
+
+ /* Get the node from FDT for sound */
+ node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SOUND);
+ if (node <= 0) {
+ debug("EXYNOS_SOUND: No node for sound in device tree\n");
+ debug("node = %d\n", node);
+ return -1;
+ }
+
+ /*
+ * Get the pre-defined sound codec specific values from FDT.
+ * All of these are expected to be correct otherwise sound
+ * can not be played
+ */
+ codectype = fdt_getprop(blob, node, "samsung,codec-type", NULL);
+ debug("device = %s\n", codectype);
+#else
+ codectype = AUDIO_CODEC;
+#endif
+ if (!strcmp(codectype, "wm8994")) {
+ /* Check the codec type and initialise the same */
+ ret = wm8994_init(blob, WM8994_AIF2,
+ pi2s_tx->samplingrate,
+ (pi2s_tx->samplingrate * (pi2s_tx->rfs)),
+ pi2s_tx->bitspersample, pi2s_tx->channels);
+ } else {
+ debug("%s: Unknown code type %s\n", __func__,
+ codectype);
+ return -1;
+ }
+ if (ret) {
+ debug("%s: Codec init failed\n", __func__);
+ return -1;
+ }
+
+ return 0;
+}
+
+int sound_init(const void *blob)
+{
+ int ret;
+ struct i2stx_info *pi2s_tx = &g_i2stx_pri;
+
+ /* Get the I2S Values */
+ if (get_sound_i2s_values(pi2s_tx, blob) < 0) {
+ debug(" FDT I2S values failed\n");
+ return -1;
+ }
+
+ if (codec_init(blob, pi2s_tx) < 0) {
+ debug(" Codec init failed\n");
+ return -1;
+ }
+
+ ret = i2s_tx_init(pi2s_tx);
+ if (ret) {
+ debug("%s: Failed to init i2c transmit: ret=%d\n", __func__,
+ ret);
+ return ret;
+ }
+
+
+ return ret;
+}
+
+/*
+ * Generates square wave sound data for 1 second
+ *
+ * @param data data buffer pointer
+ * @param size size of the buffer
+ * @param freq frequency of the wave
+ */
+static void sound_prepare_buffer(unsigned short *data, int size, uint32_t freq)
+{
+ const int sample = 48000;
+ const unsigned short amplitude = 16000; /* between 1 and 32767 */
+ const int period = freq ? sample / freq : 0;
+ const int half = period / 2;
+
+ assert(freq);
+
+ /* Make sure we don't overflow our buffer */
+ if (size % 2)
+ size--;
+
+ while (size) {
+ int i;
+ for (i = 0; size && i < half; i++) {
+ size -= 2;
+ *data++ = amplitude;
+ *data++ = amplitude;
+ }
+ for (i = 0; size && i < period - half; i++) {
+ size -= 2;
+ *data++ = -amplitude;
+ *data++ = -amplitude;
+ }
+ }
+}
+
+int sound_play(uint32_t msec, uint32_t frequency)
+{
+ unsigned int *data;
+ unsigned long data_size;
+ unsigned int ret = 0;
+
+ /*Buffer length computation */
+ data_size = g_i2stx_pri.samplingrate * g_i2stx_pri.channels;
+ data_size *= (g_i2stx_pri.bitspersample / SOUND_BITS_IN_BYTE);
+ data = malloc(data_size);
+
+ if (data == NULL) {
+ debug("%s: malloc failed\n", __func__);
+ return -1;
+ }
+
+ sound_prepare_buffer((unsigned short *)data,
+ data_size / sizeof(unsigned short), frequency);
+
+ while (msec >= 1000) {
+ ret = i2s_transfer_tx_data(&g_i2stx_pri, data,
+ (data_size / sizeof(int)));
+ msec -= 1000;
+ }
+ if (msec) {
+ unsigned long size =
+ (data_size * msec) / (sizeof(int) * 1000);
+
+ ret = i2s_transfer_tx_data(&g_i2stx_pri, data, size);
+ }
+
+ free(data);
+
+ return ret;
+}
--- /dev/null
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ * R. Chandrasekar <rcsekar@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <asm/arch/clk.h>
+#include <asm/arch/cpu.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <common.h>
+#include <div64.h>
+#include <fdtdec.h>
+#include <i2c.h>
+#include <i2s.h>
+#include <sound.h>
+#include <asm/arch/sound.h>
+#include "wm8994.h"
+#include "wm8994_registers.h"
+
+/* defines for wm8994 system clock selection */
+#define SEL_MCLK1 0x00
+#define SEL_MCLK2 0x08
+#define SEL_FLL1 0x10
+#define SEL_FLL2 0x18
+
+/* fll config to configure fll */
+struct wm8994_fll_config {
+ int src; /* Source */
+ int in; /* Input frequency in Hz */
+ int out; /* output frequency in Hz */
+};
+
+/* codec private data */
+struct wm8994_priv {
+ enum wm8994_type type; /* codec type of wolfson */
+ int revision; /* Revision */
+ int sysclk[WM8994_MAX_AIF]; /* System clock frequency in Hz */
+ int mclk[WM8994_MAX_AIF]; /* master clock frequency in Hz */
+ int aifclk[WM8994_MAX_AIF]; /* audio interface clock in Hz */
+ struct wm8994_fll_config fll[2]; /* fll config to configure fll */
+};
+
+/* wm 8994 supported sampling rate values */
+static unsigned int src_rate[] = {
+ 8000, 11025, 12000, 16000, 22050, 24000,
+ 32000, 44100, 48000, 88200, 96000
+};
+
+/* op clock divisions */
+static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
+
+/* lr clock frame size ratio */
+static int fs_ratios[] = {
+ 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
+};
+
+/* bit clock divisors */
+static int bclk_divs[] = {
+ 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
+ 640, 880, 960, 1280, 1760, 1920
+};
+
+static struct wm8994_priv g_wm8994_info;
+static unsigned char g_wm8994_i2c_dev_addr;
+static struct sound_codec_info g_codec_info;
+
+/*
+ * Initialise I2C for wm 8994
+ *
+ * @param bus no i2c bus number in which wm8994 is connected
+ */
+static void wm8994_i2c_init(int bus_no)
+{
+ i2c_set_bus_num(bus_no);
+}
+
+/*
+ * Writes value to a device register through i2c
+ *
+ * @param reg reg number to be write
+ * @param data data to be writen to the above registor
+ *
+ * @return int value 1 for change, 0 for no change or negative error code.
+ */
+static int wm8994_i2c_write(unsigned int reg, unsigned short data)
+{
+ unsigned char val[2];
+
+ val[0] = (unsigned char)((data >> 8) & 0xff);
+ val[1] = (unsigned char)(data & 0xff);
+ debug("Write Addr : 0x%04X, Data : 0x%04X\n", reg, data);
+
+ return i2c_write(g_wm8994_i2c_dev_addr, reg, 2, val, 2);
+}
+
+/*
+ * Read a value from a device register through i2c
+ *
+ * @param reg reg number to be read
+ * @param data address of read data to be stored
+ *
+ * @return int value 0 for success, -1 in case of error.
+ */
+static unsigned int wm8994_i2c_read(unsigned int reg , unsigned short *data)
+{
+ unsigned char val[2];
+ int ret;
+
+ ret = i2c_read(g_wm8994_i2c_dev_addr, reg, 2, val, 2);
+ if (ret != 0) {
+ debug("%s: Error while reading register %#04x\n",
+ __func__, reg);
+ return -1;
+ }
+
+ *data = val[0];
+ *data <<= 8;
+ *data |= val[1];
+
+ return 0;
+}
+
+/*
+ * update device register bits through i2c
+ *
+ * @param reg codec register
+ * @param mask register mask
+ * @param value new value
+ *
+ * @return int value 1 if change in the register value,
+ * 0 for no change or negative error code.
+ */
+static int wm8994_update_bits(unsigned int reg, unsigned short mask,
+ unsigned short value)
+{
+ int change , ret = 0;
+ unsigned short old, new;
+
+ if (wm8994_i2c_read(reg, &old) != 0)
+ return -1;
+ new = (old & ~mask) | (value & mask);
+ change = (old != new) ? 1 : 0;
+ if (change)
+ ret = wm8994_i2c_write(reg, new);
+ if (ret < 0)
+ return ret;
+
+ return change;
+}
+
+/*
+ * Sets i2s set format
+ *
+ * @param aif_id Interface ID
+ * @param fmt i2S format
+ *
+ * @return -1 for error and 0 Success.
+ */
+int wm8994_set_fmt(int aif_id, unsigned int fmt)
+{
+ int ms_reg;
+ int aif_reg;
+ int ms = 0;
+ int aif = 0;
+ int aif_clk = 0;
+ int error = 0;
+
+ switch (aif_id) {
+ case 1:
+ ms_reg = WM8994_AIF1_MASTER_SLAVE;
+ aif_reg = WM8994_AIF1_CONTROL_1;
+ aif_clk = WM8994_AIF1_CLOCKING_1;
+ break;
+ case 2:
+ ms_reg = WM8994_AIF2_MASTER_SLAVE;
+ aif_reg = WM8994_AIF2_CONTROL_1;
+ aif_clk = WM8994_AIF2_CLOCKING_1;
+ break;
+ default:
+ debug("%s: Invalid audio interface selection\n", __func__);
+ return -1;
+ }
+
+ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+ case SND_SOC_DAIFMT_CBS_CFS:
+ break;
+ case SND_SOC_DAIFMT_CBM_CFM:
+ ms = WM8994_AIF1_MSTR;
+ break;
+ default:
+ debug("%s: Invalid i2s master selection\n", __func__);
+ return -1;
+ }
+
+ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+ case SND_SOC_DAIFMT_DSP_B:
+ aif |= WM8994_AIF1_LRCLK_INV;
+ case SND_SOC_DAIFMT_DSP_A:
+ aif |= 0x18;
+ break;
+ case SND_SOC_DAIFMT_I2S:
+ aif |= 0x10;
+ break;
+ case SND_SOC_DAIFMT_RIGHT_J:
+ break;
+ case SND_SOC_DAIFMT_LEFT_J:
+ aif |= 0x8;
+ break;
+ default:
+ debug("%s: Invalid i2s format selection\n", __func__);
+ return -1;
+ }
+
+ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+ case SND_SOC_DAIFMT_DSP_A:
+ case SND_SOC_DAIFMT_DSP_B:
+ /* frame inversion not valid for DSP modes */
+ switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+ case SND_SOC_DAIFMT_NB_NF:
+ break;
+ case SND_SOC_DAIFMT_IB_NF:
+ aif |= WM8994_AIF1_BCLK_INV;
+ break;
+ default:
+ debug("%s: Invalid i2s frame inverse selection\n",
+ __func__);
+ return -1;
+ }
+ break;
+
+ case SND_SOC_DAIFMT_I2S:
+ case SND_SOC_DAIFMT_RIGHT_J:
+ case SND_SOC_DAIFMT_LEFT_J:
+ switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+ case SND_SOC_DAIFMT_NB_NF:
+ break;
+ case SND_SOC_DAIFMT_IB_IF:
+ aif |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
+ break;
+ case SND_SOC_DAIFMT_IB_NF:
+ aif |= WM8994_AIF1_BCLK_INV;
+ break;
+ case SND_SOC_DAIFMT_NB_IF:
+ aif |= WM8994_AIF1_LRCLK_INV;
+ break;
+ default:
+ debug("%s: Invalid i2s clock polarity selection\n",
+ __func__);
+ return -1;
+ }
+ break;
+ default:
+ debug("%s: Invalid i2s format selection\n", __func__);
+ return -1;
+ }
+
+ error = wm8994_update_bits(aif_reg, WM8994_AIF1_BCLK_INV |
+ WM8994_AIF1_LRCLK_INV_MASK | WM8994_AIF1_FMT_MASK, aif);
+
+ error |= wm8994_update_bits(ms_reg, WM8994_AIF1_MSTR_MASK, ms);
+ error |= wm8994_update_bits(aif_clk, WM8994_AIF1CLK_ENA_MASK,
+ WM8994_AIF1CLK_ENA);
+ if (error < 0) {
+ debug("%s: codec register access error\n", __func__);
+ return -1;
+ }
+
+ return 0;
+}
+
+/*
+ * Sets hw params FOR WM8994
+ *
+ * @param wm8994 wm8994 information pointer
+ * @param aif_id Audio interface ID
+ * @param sampling_rate Sampling rate
+ * @param bits_per_sample Bits per sample
+ * @param Channels Channels in the given audio input
+ *
+ * @return -1 for error and 0 Success.
+ */
+static int wm8994_hw_params(struct wm8994_priv *wm8994, int aif_id,
+ unsigned int sampling_rate, unsigned int bits_per_sample,
+ unsigned int channels)
+{
+ int aif1_reg;
+ int aif2_reg;
+ int bclk_reg;
+ int bclk = 0;
+ int rate_reg;
+ int aif1 = 0;
+ int aif2 = 0;
+ int rate_val = 0;
+ int id = aif_id - 1;
+ int i, cur_val, best_val, bclk_rate, best;
+ unsigned short reg_data;
+ int ret = 0;
+
+ switch (aif_id) {
+ case 1:
+ aif1_reg = WM8994_AIF1_CONTROL_1;
+ aif2_reg = WM8994_AIF1_CONTROL_2;
+ bclk_reg = WM8994_AIF1_BCLK;
+ rate_reg = WM8994_AIF1_RATE;
+ break;
+ case 2:
+ aif1_reg = WM8994_AIF2_CONTROL_1;
+ aif2_reg = WM8994_AIF2_CONTROL_2;
+ bclk_reg = WM8994_AIF2_BCLK;
+ rate_reg = WM8994_AIF2_RATE;
+ break;
+ default:
+ return -1;
+ }
+
+ bclk_rate = sampling_rate * 32;
+ switch (bits_per_sample) {
+ case 16:
+ bclk_rate *= 16;
+ break;
+ case 20:
+ bclk_rate *= 20;
+ aif1 |= 0x20;
+ break;
+ case 24:
+ bclk_rate *= 24;
+ aif1 |= 0x40;
+ break;
+ case 32:
+ bclk_rate *= 32;
+ aif1 |= 0x60;
+ break;
+ default:
+ return -1;
+ }
+
+ /* Try to find an appropriate sample rate; look for an exact match. */
+ for (i = 0; i < ARRAY_SIZE(src_rate); i++)
+ if (src_rate[i] == sampling_rate)
+ break;
+
+ if (i == ARRAY_SIZE(src_rate)) {
+ debug("%s: Could not get the best matching samplingrate\n",
+ __func__);
+ return -1;
+ }
+
+ rate_val |= i << WM8994_AIF1_SR_SHIFT;
+
+ /* AIFCLK/fs ratio; look for a close match in either direction */
+ best = 0;
+ best_val = abs((fs_ratios[0] * sampling_rate)
+ - wm8994->aifclk[id]);
+
+ for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
+ cur_val = abs((fs_ratios[i] * sampling_rate)
+ - wm8994->aifclk[id]);
+ if (cur_val >= best_val)
+ continue;
+ best = i;
+ best_val = cur_val;
+ }
+
+ rate_val |= best;
+
+ /*
+ * We may not get quite the right frequency if using
+ * approximate clocks so look for the closest match that is
+ * higher than the target (we need to ensure that there enough
+ * BCLKs to clock out the samples).
+ */
+ best = 0;
+ for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
+ cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
+ if (cur_val < 0) /* BCLK table is sorted */
+ break;
+ best = i;
+ }
+
+ if (i == ARRAY_SIZE(bclk_divs)) {
+ debug("%s: Could not get the best matching bclk division\n",
+ __func__);
+ return -1;
+ }
+
+ bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
+ bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
+
+ if (wm8994_i2c_read(aif1_reg, ®_data) != 0) {
+ debug("%s: AIF1 register read Failed\n", __func__);
+ return -1;
+ }
+
+ if ((channels == 1) && ((reg_data & 0x18) == 0x18))
+ aif2 |= WM8994_AIF1_MONO;
+
+ if (wm8994->aifclk[id] == 0) {
+ debug("%s:Audio interface clock not set\n", __func__);
+ return -1;
+ }
+
+ ret = wm8994_update_bits(aif1_reg, WM8994_AIF1_WL_MASK, aif1);
+ ret |= wm8994_update_bits(aif2_reg, WM8994_AIF1_MONO, aif2);
+ ret |= wm8994_update_bits(bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
+ ret |= wm8994_update_bits(rate_reg, WM8994_AIF1_SR_MASK |
+ WM8994_AIF1CLK_RATE_MASK, rate_val);
+
+ debug("rate vale = %x , bclk val= %x\n", rate_val, bclk);
+
+ if (ret < 0) {
+ debug("%s: codec register access error\n", __func__);
+ return -1;
+ }
+
+ return 0;
+}
+
+/*
+ * Configures Audio interface Clock
+ *
+ * @param wm8994 wm8994 information pointer
+ * @param aif Audio Interface ID
+ *
+ * @return -1 for error and 0 Success.
+ */
+static int configure_aif_clock(struct wm8994_priv *wm8994, int aif)
+{
+ int rate;
+ int reg1 = 0;
+ int offset;
+ int ret;
+
+ /* AIF(1/0) register adress offset calculated */
+ if (aif)
+ offset = 4;
+ else
+ offset = 0;
+
+ switch (wm8994->sysclk[aif]) {
+ case WM8994_SYSCLK_MCLK1:
+ reg1 |= SEL_MCLK1;
+ rate = wm8994->mclk[0];
+ break;
+
+ case WM8994_SYSCLK_MCLK2:
+ reg1 |= SEL_MCLK2;
+ rate = wm8994->mclk[1];
+ break;
+
+ case WM8994_SYSCLK_FLL1:
+ reg1 |= SEL_FLL1;
+ rate = wm8994->fll[0].out;
+ break;
+
+ case WM8994_SYSCLK_FLL2:
+ reg1 |= SEL_FLL2;
+ rate = wm8994->fll[1].out;
+ break;
+
+ default:
+ debug("%s: Invalid input clock selection [%d]\n",
+ __func__, wm8994->sysclk[aif]);
+ return -1;
+ }
+
+ /* if input clock frequenct is more than 135Mhz then divide */
+ if (rate >= WM8994_MAX_INPUT_CLK_FREQ) {
+ rate /= 2;
+ reg1 |= WM8994_AIF1CLK_DIV;
+ }
+
+ wm8994->aifclk[aif] = rate;
+
+ ret = wm8994_update_bits(WM8994_AIF1_CLOCKING_1 + offset,
+ WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
+ reg1);
+
+ ret |= wm8994_update_bits(WM8994_CLOCKING_1,
+ WM8994_SYSCLK_SRC | WM8994_AIF2DSPCLK_ENA_MASK |
+ WM8994_SYSDSPCLK_ENA_MASK, WM8994_SYSCLK_SRC |
+ WM8994_AIF2DSPCLK_ENA | WM8994_SYSDSPCLK_ENA);
+
+ if (ret < 0) {
+ debug("%s: codec register access error\n", __func__);
+ return -1;
+ }
+
+ return 0;
+}
+
+/*
+ * Configures Audio interface for the given frequency
+ *
+ * @param wm8994 wm8994 information
+ * @param aif_id Audio Interface
+ * @param clk_id Input Clock ID
+ * @param freq Sampling frequency in Hz
+ *
+ * @return -1 for error and 0 success.
+ */
+static int wm8994_set_sysclk(struct wm8994_priv *wm8994, int aif_id,
+ int clk_id, unsigned int freq)
+{
+ int i;
+ int ret = 0;
+
+ wm8994->sysclk[aif_id - 1] = clk_id;
+
+ switch (clk_id) {
+ case WM8994_SYSCLK_MCLK1:
+ wm8994->mclk[0] = freq;
+ if (aif_id == 2) {
+ ret = wm8994_update_bits(WM8994_AIF1_CLOCKING_2 ,
+ WM8994_AIF2DAC_DIV_MASK , 0);
+ }
+ break;
+
+ case WM8994_SYSCLK_MCLK2:
+ /* TODO: Set GPIO AF */
+ wm8994->mclk[1] = freq;
+ break;
+
+ case WM8994_SYSCLK_FLL1:
+ case WM8994_SYSCLK_FLL2:
+ break;
+
+ case WM8994_SYSCLK_OPCLK:
+ /*
+ * Special case - a division (times 10) is given and
+ * no effect on main clocking.
+ */
+ if (freq) {
+ for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
+ if (opclk_divs[i] == freq)
+ break;
+ if (i == ARRAY_SIZE(opclk_divs)) {
+ debug("%s frequency divisor not found\n",
+ __func__);
+ return -1;
+ }
+ ret = wm8994_update_bits(WM8994_CLOCKING_2,
+ WM8994_OPCLK_DIV_MASK, i);
+ ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_2,
+ WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
+ } else {
+ ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_2,
+ WM8994_OPCLK_ENA, 0);
+ }
+
+ default:
+ debug("%s Invalid input clock selection [%d]\n",
+ __func__, clk_id);
+ return -1;
+ }
+
+ ret |= configure_aif_clock(wm8994, aif_id - 1);
+
+ if (ret < 0) {
+ debug("%s: codec register access error\n", __func__);
+ return -1;
+ }
+
+ return 0;
+}
+
+/*
+ * Initializes Volume for AIF2 to HP path
+ *
+ * @returns -1 for error and 0 Success.
+ *
+ */
+static int wm8994_init_volume_aif2_dac1(void)
+{
+ int ret;
+
+ /* Unmute AIF2DAC */
+ ret = wm8994_update_bits(WM8994_AIF2_DAC_FILTERS_1,
+ WM8994_AIF2DAC_MUTE_MASK, 0);
+
+
+ ret |= wm8994_update_bits(WM8994_AIF2_DAC_LEFT_VOLUME,
+ WM8994_AIF2DAC_VU_MASK | WM8994_AIF2DACL_VOL_MASK,
+ WM8994_AIF2DAC_VU | 0xff);
+
+ ret |= wm8994_update_bits(WM8994_AIF2_DAC_RIGHT_VOLUME,
+ WM8994_AIF2DAC_VU_MASK | WM8994_AIF2DACR_VOL_MASK,
+ WM8994_AIF2DAC_VU | 0xff);
+
+
+ ret |= wm8994_update_bits(WM8994_DAC1_LEFT_VOLUME,
+ WM8994_DAC1_VU_MASK | WM8994_DAC1L_VOL_MASK |
+ WM8994_DAC1L_MUTE_MASK, WM8994_DAC1_VU | 0xc0);
+
+ ret |= wm8994_update_bits(WM8994_DAC1_RIGHT_VOLUME,
+ WM8994_DAC1_VU_MASK | WM8994_DAC1R_VOL_MASK |
+ WM8994_DAC1R_MUTE_MASK, WM8994_DAC1_VU | 0xc0);
+ /* Head Phone Volume */
+ ret |= wm8994_i2c_write(WM8994_LEFT_OUTPUT_VOLUME, 0x12D);
+ ret |= wm8994_i2c_write(WM8994_RIGHT_OUTPUT_VOLUME, 0x12D);
+
+ if (ret < 0) {
+ debug("%s: codec register access error\n", __func__);
+ return -1;
+ }
+
+ return 0;
+}
+
+/*
+ * Intialise wm8994 codec device
+ *
+ * @param wm8994 wm8994 information
+ *
+ * @returns -1 for error and 0 Success.
+ */
+static int wm8994_device_init(struct wm8994_priv *wm8994)
+{
+ const char *devname;
+ unsigned short reg_data;
+ int ret;
+
+ wm8994_i2c_write(WM8994_SOFTWARE_RESET, WM8994_SW_RESET);/* Reset */
+
+ ret = wm8994_i2c_read(WM8994_SOFTWARE_RESET, ®_data);
+ if (ret < 0) {
+ debug("Failed to read ID register\n");
+ goto err;
+ }
+
+ if (reg_data == WM8994_ID) {
+ devname = "WM8994";
+ debug("Device registered as type %d\n", wm8994->type);
+ wm8994->type = WM8994;
+ } else {
+ debug("Device is not a WM8994, ID is %x\n", ret);
+ ret = -1;
+ goto err;
+ }
+
+ ret = wm8994_i2c_read(WM8994_CHIP_REVISION, ®_data);
+ if (ret < 0) {
+ debug("Failed to read revision register: %d\n", ret);
+ goto err;
+ }
+ wm8994->revision = reg_data;
+ debug("%s revision %c\n", devname, 'A' + wm8994->revision);
+
+ /* VMID Selection */
+ ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_1,
+ WM8994_VMID_SEL_MASK | WM8994_BIAS_ENA_MASK, 0x3);
+
+ /* Charge Pump Enable */
+ ret |= wm8994_update_bits(WM8994_CHARGE_PUMP_1, WM8994_CP_ENA_MASK,
+ WM8994_CP_ENA);
+
+ /* Head Phone Power Enable */
+ ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_1,
+ WM8994_HPOUT1L_ENA_MASK, WM8994_HPOUT1L_ENA);
+
+ ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_1,
+ WM8994_HPOUT1R_ENA_MASK, WM8994_HPOUT1R_ENA);
+
+ /* Power enable for AIF2 and DAC1 */
+ ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_5,
+ WM8994_AIF2DACL_ENA_MASK | WM8994_AIF2DACR_ENA_MASK |
+ WM8994_DAC1L_ENA_MASK | WM8994_DAC1R_ENA_MASK,
+ WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA | WM8994_DAC1L_ENA |
+ WM8994_DAC1R_ENA);
+
+ /* Head Phone Initialisation */
+ ret |= wm8994_update_bits(WM8994_ANALOGUE_HP_1,
+ WM8994_HPOUT1L_DLY_MASK | WM8994_HPOUT1R_DLY_MASK,
+ WM8994_HPOUT1L_DLY | WM8994_HPOUT1R_DLY);
+
+ ret |= wm8994_update_bits(WM8994_DC_SERVO_1,
+ WM8994_DCS_ENA_CHAN_0_MASK |
+ WM8994_DCS_ENA_CHAN_1_MASK , WM8994_DCS_ENA_CHAN_0 |
+ WM8994_DCS_ENA_CHAN_1);
+
+ ret |= wm8994_update_bits(WM8994_ANALOGUE_HP_1,
+ WM8994_HPOUT1L_DLY_MASK |
+ WM8994_HPOUT1R_DLY_MASK | WM8994_HPOUT1L_OUTP_MASK |
+ WM8994_HPOUT1R_OUTP_MASK |
+ WM8994_HPOUT1L_RMV_SHORT_MASK |
+ WM8994_HPOUT1R_RMV_SHORT_MASK, WM8994_HPOUT1L_DLY |
+ WM8994_HPOUT1R_DLY | WM8994_HPOUT1L_OUTP |
+ WM8994_HPOUT1R_OUTP | WM8994_HPOUT1L_RMV_SHORT |
+ WM8994_HPOUT1R_RMV_SHORT);
+
+ /* MIXER Config DAC1 to HP */
+ ret |= wm8994_update_bits(WM8994_OUTPUT_MIXER_1,
+ WM8994_DAC1L_TO_HPOUT1L_MASK, WM8994_DAC1L_TO_HPOUT1L);
+
+ ret |= wm8994_update_bits(WM8994_OUTPUT_MIXER_2,
+ WM8994_DAC1R_TO_HPOUT1R_MASK, WM8994_DAC1R_TO_HPOUT1R);
+
+ /* Routing AIF2 to DAC1 */
+ ret |= wm8994_update_bits(WM8994_DAC1_LEFT_MIXER_ROUTING,
+ WM8994_AIF2DACL_TO_DAC1L_MASK,
+ WM8994_AIF2DACL_TO_DAC1L);
+
+ ret |= wm8994_update_bits(WM8994_DAC1_RIGHT_MIXER_ROUTING,
+ WM8994_AIF2DACR_TO_DAC1R_MASK,
+ WM8994_AIF2DACR_TO_DAC1R);
+
+ /* GPIO Settings for AIF2 */
+ /* B CLK */
+ ret |= wm8994_update_bits(WM8994_GPIO_3, WM8994_GPIO_DIR_MASK |
+ WM8994_GPIO_FUNCTION_MASK ,
+ WM8994_GPIO_DIR_OUTPUT |
+ WM8994_GPIO_FUNCTION_I2S_CLK);
+
+ /* LR CLK */
+ ret |= wm8994_update_bits(WM8994_GPIO_4, WM8994_GPIO_DIR_MASK |
+ WM8994_GPIO_FUNCTION_MASK,
+ WM8994_GPIO_DIR_OUTPUT |
+ WM8994_GPIO_FUNCTION_I2S_CLK);
+
+ /* DATA */
+ ret |= wm8994_update_bits(WM8994_GPIO_5, WM8994_GPIO_DIR_MASK |
+ WM8994_GPIO_FUNCTION_MASK,
+ WM8994_GPIO_DIR_OUTPUT |
+ WM8994_GPIO_FUNCTION_I2S_CLK);
+
+ ret |= wm8994_init_volume_aif2_dac1();
+ if (ret < 0)
+ goto err;
+
+ debug("%s: Codec chip init ok\n", __func__);
+ return 0;
+err:
+ debug("%s: Codec chip init error\n", __func__);
+ return -1;
+}
+
+/*
+ * Gets fdt values for wm8994 config parameters
+ *
+ * @param pcodec_info codec information structure
+ * @param blob FDT blob
+ * @return int value, 0 for success
+ */
+static int get_codec_values(struct sound_codec_info *pcodec_info,
+ const void *blob)
+{
+ int error = 0;
+#ifdef CONFIG_OF_CONTROL
+ enum fdt_compat_id compat;
+ int node;
+ int parent;
+
+ /* Get the node from FDT for codec */
+ node = fdtdec_next_compatible(blob, 0, COMPAT_WOLFSON_WM8994_CODEC);
+ if (node <= 0) {
+ debug("EXYNOS_SOUND: No node for codec in device tree\n");
+ debug("node = %d\n", node);
+ return -1;
+ }
+
+ parent = fdt_parent_offset(blob, node);
+ if (parent < 0) {
+ debug("%s: Cannot find node parent\n", __func__);
+ return -1;
+ }
+
+ compat = fdtdec_lookup(blob, parent);
+ switch (compat) {
+ case COMPAT_SAMSUNG_S3C2440_I2C:
+ pcodec_info->i2c_bus = i2c_get_bus_num_fdt(parent);
+ error |= pcodec_info->i2c_bus;
+ debug("i2c bus = %d\n", pcodec_info->i2c_bus);
+ pcodec_info->i2c_dev_addr = fdtdec_get_int(blob, node,
+ "reg", 0);
+ error |= pcodec_info->i2c_dev_addr;
+ debug("i2c dev addr = %d\n", pcodec_info->i2c_dev_addr);
+ break;
+ default:
+ debug("%s: Unknown compat id %d\n", __func__, compat);
+ return -1;
+ }
+#else
+ pcodec_info->i2c_bus = AUDIO_I2C_BUS;
+ pcodec_info->i2c_dev_addr = AUDIO_I2C_REG;
+ debug("i2c dev addr = %d\n", pcodec_info->i2c_dev_addr);
+#endif
+
+ pcodec_info->codec_type = CODEC_WM_8994;
+
+ if (error == -1) {
+ debug("fail to get wm8994 codec node properties\n");
+ return -1;
+ }
+
+ return 0;
+}
+
+/*wm8994 Device Initialisation */
+int wm8994_init(const void *blob, enum en_audio_interface aif_id,
+ int sampling_rate, int mclk_freq,
+ int bits_per_sample, unsigned int channels)
+{
+ int ret = 0;
+ struct sound_codec_info *pcodec_info = &g_codec_info;
+
+ /* Get the codec Values */
+ if (get_codec_values(pcodec_info, blob) < 0) {
+ debug("FDT Codec values failed\n");
+ return -1;
+ }
+
+ /* shift the device address by 1 for 7 bit addressing */
+ g_wm8994_i2c_dev_addr = pcodec_info->i2c_dev_addr;
+ wm8994_i2c_init(pcodec_info->i2c_bus);
+
+ if (pcodec_info->codec_type == CODEC_WM_8994)
+ g_wm8994_info.type = WM8994;
+ else {
+ debug("%s: Codec id [%d] not defined\n", __func__,
+ pcodec_info->codec_type);
+ return -1;
+ }
+
+ ret = wm8994_device_init(&g_wm8994_info);
+ if (ret < 0) {
+ debug("%s: wm8994 codec chip init failed\n", __func__);
+ return ret;
+ }
+
+ ret = wm8994_set_sysclk(&g_wm8994_info, aif_id, WM8994_SYSCLK_MCLK1,
+ mclk_freq);
+ if (ret < 0) {
+ debug("%s: wm8994 codec set sys clock failed\n", __func__);
+ return ret;
+ }
+
+ ret = wm8994_hw_params(&g_wm8994_info, aif_id, sampling_rate,
+ bits_per_sample, channels);
+
+ if (ret == 0) {
+ ret = wm8994_set_fmt(aif_id, SND_SOC_DAIFMT_I2S |
+ SND_SOC_DAIFMT_NB_NF |
+ SND_SOC_DAIFMT_CBS_CFS);
+ }
+ return ret;
+}
--- /dev/null
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ * R. Chadrasekar <rcsekar@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __WM8994_H__
+#define __WM8994_H__
+
+/* Sources for AIF1/2 SYSCLK - use with set_dai_sysclk() */
+#define WM8994_SYSCLK_MCLK1 1
+#define WM8994_SYSCLK_MCLK2 2
+#define WM8994_SYSCLK_FLL1 3
+#define WM8994_SYSCLK_FLL2 4
+
+/* Avilable audi interface ports in wm8994 codec */
+enum en_audio_interface {
+ WM8994_AIF1 = 1,
+ WM8994_AIF2,
+ WM8994_AIF3
+};
+
+/* OPCLK is also configured with set_dai_sysclk, specify division*10 as rate. */
+#define WM8994_SYSCLK_OPCLK 5
+
+#define WM8994_FLL1 1
+#define WM8994_FLL2 2
+
+#define WM8994_FLL_SRC_MCLK1 1
+#define WM8994_FLL_SRC_MCLK2 2
+#define WM8994_FLL_SRC_LRCLK 3
+#define WM8994_FLL_SRC_BCLK 4
+
+/* maximum available digital interfac in the dac to configure */
+#define WM8994_MAX_AIF 2
+
+#define WM8994_MAX_INPUT_CLK_FREQ 13500000
+#define WM8994_ID 0x8994
+
+enum wm8994_vmid_mode {
+ WM8994_VMID_NORMAL,
+ WM8994_VMID_FORCE,
+};
+
+/* wm 8994 family devices */
+enum wm8994_type {
+ WM8994 = 0,
+ WM8958 = 1,
+ WM1811 = 2,
+};
+
+/*
+ * intialise wm8994 sound codec device for the given configuration
+ *
+ * @param blob FDT node for codec values
+ * @param aif_id enum value of codec interface port in which
+ * soc i2s is connected
+ * @param sampling_rate Sampling rate ranges between from 8khz to 96khz
+ * @param mclk_freq Master clock frequency.
+ * @param bits_per_sample bits per Sample can be 16 or 24
+ * @param channels Number of channnels, maximum 2
+ *
+ * @returns -1 for error and 0 Success.
+ */
+int wm8994_init(const void *blob, enum en_audio_interface aif_id,
+ int sampling_rate, int mclk_freq,
+ int bits_per_sample, unsigned int channels);
+#endif /*__WM8994_H__ */
--- /dev/null
+/*
+ * (C) Copyright 2012 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#ifndef __WM8994_REGISTERS_H__
+#define __WM8994_REGISTERS_H__
+
+/*
+ * Register values.
+ */
+#define WM8994_SOFTWARE_RESET 0x00
+#define WM8994_POWER_MANAGEMENT_1 0x01
+#define WM8994_POWER_MANAGEMENT_2 0x02
+#define WM8994_POWER_MANAGEMENT_5 0x05
+#define WM8994_LEFT_OUTPUT_VOLUME 0x1C
+#define WM8994_RIGHT_OUTPUT_VOLUME 0x1D
+#define WM8994_OUTPUT_MIXER_1 0x2D
+#define WM8994_OUTPUT_MIXER_2 0x2E
+#define WM8994_CHARGE_PUMP_1 0x4C
+#define WM8994_DC_SERVO_1 0x54
+#define WM8994_ANALOGUE_HP_1 0x60
+#define WM8994_CHIP_REVISION 0x100
+#define WM8994_AIF1_CLOCKING_1 0x200
+#define WM8994_AIF1_CLOCKING_2 0x201
+#define WM8994_AIF2_CLOCKING_1 0x204
+#define WM8994_CLOCKING_1 0x208
+#define WM8994_CLOCKING_2 0x209
+#define WM8994_AIF1_RATE 0x210
+#define WM8994_AIF2_RATE 0x211
+#define WM8994_RATE_STATUS 0x212
+#define WM8994_AIF1_CONTROL_1 0x300
+#define WM8994_AIF1_CONTROL_2 0x301
+#define WM8994_AIF1_MASTER_SLAVE 0x302
+#define WM8994_AIF1_BCLK 0x303
+#define WM8994_AIF2_CONTROL_1 0x310
+#define WM8994_AIF2_CONTROL_2 0x311
+#define WM8994_AIF2_MASTER_SLAVE 0x312
+#define WM8994_AIF2_BCLK 0x313
+#define WM8994_AIF2_DAC_LEFT_VOLUME 0x502
+#define WM8994_AIF2_DAC_RIGHT_VOLUME 0x503
+#define WM8994_AIF2_DAC_FILTERS_1 0x520
+#define WM8994_DAC1_LEFT_MIXER_ROUTING 0x601
+#define WM8994_DAC1_RIGHT_MIXER_ROUTING 0x602
+#define WM8994_DAC1_LEFT_VOLUME 0x610
+#define WM8994_DAC1_RIGHT_VOLUME 0x611
+#define WM8994_GPIO_3 0x702
+#define WM8994_GPIO_4 0x703
+#define WM8994_GPIO_5 0x704
+
+/*
+ * Field Definitions.
+ */
+
+/*
+ * R0 (0x00) - Software Reset
+ */
+/* SW_RESET */
+#define WM8994_SW_RESET 1
+/*
+ * R1 (0x01) - Power Management (1)
+ */
+/* HPOUT1L_ENA */
+#define WM8994_HPOUT1L_ENA 0x0200
+/* HPOUT1L_ENA */
+#define WM8994_HPOUT1L_ENA_MASK 0x0200
+/* HPOUT1R_ENA */
+#define WM8994_HPOUT1R_ENA 0x0100
+/* HPOUT1R_ENA */
+#define WM8994_HPOUT1R_ENA_MASK 0x0100
+/* VMID_SEL - [2:1] */
+#define WM8994_VMID_SEL_MASK 0x0006
+/* BIAS_ENA */
+#define WM8994_BIAS_ENA 0x0001
+/* BIAS_ENA */
+#define WM8994_BIAS_ENA_MASK 0x0001
+
+/*
+ * R2 (0x02) - Power Management (2)
+ */
+/* OPCLK_ENA */
+#define WM8994_OPCLK_ENA 0x0800
+
+/*
+ * R5 (0x05) - Power Management (5)
+ */
+/* AIF2DACL_ENA */
+#define WM8994_AIF2DACL_ENA 0x2000
+#define WM8994_AIF2DACL_ENA_MASK 0x2000
+/* AIF2DACR_ENA */
+#define WM8994_AIF2DACR_ENA 0x1000
+#define WM8994_AIF2DACR_ENA_MASK 0x1000
+/* DAC1L_ENA */
+#define WM8994_DAC1L_ENA 0x0002
+#define WM8994_DAC1L_ENA_MASK 0x0002
+/* DAC1R_ENA */
+#define WM8994_DAC1R_ENA 0x0001
+#define WM8994_DAC1R_ENA_MASK 0x0001
+
+/*
+ * R45 (0x2D) - Output Mixer (1)
+ */
+/* DAC1L_TO_HPOUT1L */
+#define WM8994_DAC1L_TO_HPOUT1L 0x0100
+#define WM8994_DAC1L_TO_HPOUT1L_MASK 0x0100
+
+/*
+ * R46 (0x2E) - Output Mixer (2)
+ */
+/* DAC1R_TO_HPOUT1R */
+#define WM8994_DAC1R_TO_HPOUT1R 0x0100
+#define WM8994_DAC1R_TO_HPOUT1R_MASK 0x0100
+
+/*
+ * R76 (0x4C) - Charge Pump (1)
+ */
+/* CP_ENA */
+#define WM8994_CP_ENA 0x8000
+#define WM8994_CP_ENA_MASK 0x8000
+/*
+ * R84 (0x54) - DC Servo (1)
+ */
+/* DCS_ENA_CHAN_1 */
+#define WM8994_DCS_ENA_CHAN_1 0x0002
+#define WM8994_DCS_ENA_CHAN_1_MASK 0x0002
+/* DCS_ENA_CHAN_0 */
+#define WM8994_DCS_ENA_CHAN_0 0x0001
+#define WM8994_DCS_ENA_CHAN_0_MASK 0x0001
+
+/*
+ * R96 (0x60) - Analogue HP (1)
+ */
+/* HPOUT1L_RMV_SHORT */
+#define WM8994_HPOUT1L_RMV_SHORT 0x0080
+#define WM8994_HPOUT1L_RMV_SHORT_MASK 0x0080
+/* HPOUT1L_OUTP */
+#define WM8994_HPOUT1L_OUTP 0x0040
+#define WM8994_HPOUT1L_OUTP_MASK 0x0040
+/* HPOUT1L_DLY */
+#define WM8994_HPOUT1L_DLY 0x0020
+#define WM8994_HPOUT1L_DLY_MASK 0x0020
+/* HPOUT1R_RMV_SHORT */
+#define WM8994_HPOUT1R_RMV_SHORT 0x0008
+#define WM8994_HPOUT1R_RMV_SHORT_MASK 0x0008
+/* HPOUT1R_OUTP */
+#define WM8994_HPOUT1R_OUTP 0x0004
+#define WM8994_HPOUT1R_OUTP_MASK 0x0004
+/* HPOUT1R_DLY */
+#define WM8994_HPOUT1R_DLY 0x0002
+#define WM8994_HPOUT1R_DLY_MASK 0x0002
+
+/*
+ * R512 (0x200) - AIF1 Clocking (1)
+ */
+/* AIF1CLK_SRC - [4:3] */
+#define WM8994_AIF1CLK_SRC_MASK 0x0018
+/* AIF1CLK_DIV */
+#define WM8994_AIF1CLK_DIV 0x0002
+/* AIF1CLK_ENA */
+#define WM8994_AIF1CLK_ENA 0x0001
+#define WM8994_AIF1CLK_ENA_MASK 0x0001
+
+/*
+ * R517 (0x205) - AIF2 Clocking (2)
+ */
+/* AIF2DAC_DIV - [5:3] */
+#define WM8994_AIF2DAC_DIV_MASK 0x0038
+
+/*
+ * R520 (0x208) - Clocking (1)
+ */
+/* AIF2DSPCLK_ENA */
+#define WM8994_AIF2DSPCLK_ENA 0x0004
+#define WM8994_AIF2DSPCLK_ENA_MASK 0x0004
+/* SYSDSPCLK_ENA */
+#define WM8994_SYSDSPCLK_ENA 0x0002
+#define WM8994_SYSDSPCLK_ENA_MASK 0x0002
+/* SYSCLK_SRC */
+#define WM8994_SYSCLK_SRC 0x0001
+
+/*
+ * R521 (0x209) - Clocking (2)
+ */
+/* OPCLK_DIV - [2:0] */
+#define WM8994_OPCLK_DIV_MASK 0x0007
+
+/*
+ * R528 (0x210) - AIF1 Rate
+ */
+/* AIF1_SR - [7:4] */
+#define WM8994_AIF1_SR_MASK 0x00F0
+#define WM8994_AIF1_SR_SHIFT 4
+/* AIF1CLK_RATE - [3:0] */
+#define WM8994_AIF1CLK_RATE_MASK 0x000F
+
+/*
+ * R768 (0x300) - AIF1 Control (1)
+ */
+/* AIF1_BCLK_INV */
+#define WM8994_AIF1_BCLK_INV 0x0100
+/* AIF1_LRCLK_INV */
+#define WM8994_AIF1_LRCLK_INV 0x0080
+#define WM8994_AIF1_LRCLK_INV_MASK 0x0080
+/* AIF1_WL - [6:5] */
+#define WM8994_AIF1_WL_MASK 0x0060
+/* AIF1_FMT - [4:3] */
+#define WM8994_AIF1_FMT_MASK 0x0018
+
+/*
+ * R769 (0x301) - AIF1 Control (2)
+ */
+/* AIF1_MONO */
+#define WM8994_AIF1_MONO 0x0100
+
+/*
+ * R770 (0x302) - AIF1 Master/Slave
+ */
+/* AIF1_MSTR */
+#define WM8994_AIF1_MSTR 0x4000
+#define WM8994_AIF1_MSTR_MASK 0x4000
+
+/*
+ * R771 (0x303) - AIF1 BCLK
+ */
+/* AIF1_BCLK_DIV - [8:4] */
+#define WM8994_AIF1_BCLK_DIV_MASK 0x01F0
+#define WM8994_AIF1_BCLK_DIV_SHIFT 4
+
+/*
+ * R1282 (0x502) - AIF2 DAC Left Volume
+ */
+/* AIF2DAC_VU */
+#define WM8994_AIF2DAC_VU 0x0100
+#define WM8994_AIF2DAC_VU_MASK 0x0100
+/* AIF2DACL_VOL - [7:0] */
+#define WM8994_AIF2DACL_VOL_MASK 0x00FF
+
+/*
+ * R1283 (0x503) - AIF2 DAC Right Volume
+ */
+/* AIF2DACR_VOL - [7:0] */
+#define WM8994_AIF2DACR_VOL_MASK 0x00FF
+
+/*
+ * R1312 (0x520) - AIF2 DAC Filters (1)
+ */
+/* AIF2DAC_MUTE */
+#define WM8994_AIF2DAC_MUTE_MASK 0x0200
+
+/*
+ * R1537 (0x601) - DAC1 Left Mixer Routing
+ */
+/* AIF2DACL_TO_DAC1L */
+#define WM8994_AIF2DACL_TO_DAC1L 0x0004
+#define WM8994_AIF2DACL_TO_DAC1L_MASK 0x0004
+
+/*
+ * R1538 (0x602) - DAC1 Right Mixer Routing
+ */
+/* AIF2DACR_TO_DAC1R */
+#define WM8994_AIF2DACR_TO_DAC1R 0x0004
+#define WM8994_AIF2DACR_TO_DAC1R_MASK 0x0004
+
+/*
+ * R1552 (0x610) - DAC1 Left Volume
+ */
+/* DAC1L_MUTE */
+#define WM8994_DAC1L_MUTE_MASK 0x0200
+/* DAC1_VU */
+#define WM8994_DAC1_VU 0x0100
+#define WM8994_DAC1_VU_MASK 0x0100
+/* DAC1L_VOL - [7:0] */
+#define WM8994_DAC1L_VOL_MASK 0x00FF
+
+/*
+ * R1553 (0x611) - DAC1 Right Volume
+ */
+/* DAC1R_MUTE */
+#define WM8994_DAC1R_MUTE_MASK 0x0200
+/* DAC1R_VOL - [7:0] */
+#define WM8994_DAC1R_VOL_MASK 0x00FF
+
+/*
+ * GPIO
+ */
+/* OUTPUT PIN */
+#define WM8994_GPIO_DIR_OUTPUT 0x8000
+/* GPIO PIN MASK */
+#define WM8994_GPIO_DIR_MASK 0xFFE0
+/* I2S CLK */
+#define WM8994_GPIO_FUNCTION_I2S_CLK 0x0000
+/* GPn FN */
+#define WM8994_GPIO_FUNCTION_MASK 0x001F
+#endif
COBJS-$(CONFIG_CF_SPI) += cf_spi.o
COBJS-$(CONFIG_CF_QSPI) += cf_qspi.o
COBJS-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
+COBJS-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
COBJS-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
COBJS-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o
COBJS-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
as->slave.cs = cs;
as->regs = regs;
as->mr = ATMEL_SPI_MR_MSTR | ATMEL_SPI_MR_MODFDIS
-#if defined(CONFIG_AT91SAM9X5)
+#if defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9M10G45)
| ATMEL_SPI_MR_WDRBT
#endif
| ATMEL_SPI_MR_PCS(~(1 << cs) & 0xf);
--- /dev/null
+/*
+ * (C) Copyright 2012 SAMSUNG Electronics
+ * Padmavathi Venna <padma.v@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <spi.h>
+#include <fdtdec.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch-exynos/spi.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Information about each SPI controller */
+struct spi_bus {
+ enum periph_id periph_id;
+ s32 frequency; /* Default clock frequency, -1 for none */
+ struct exynos_spi *regs;
+ int inited; /* 1 if this bus is ready for use */
+ int node;
+};
+
+/* A list of spi buses that we know about */
+static struct spi_bus spi_bus[EXYNOS5_SPI_NUM_CONTROLLERS];
+static unsigned int bus_count;
+
+struct exynos_spi_slave {
+ struct spi_slave slave;
+ struct exynos_spi *regs;
+ unsigned int freq; /* Default frequency */
+ unsigned int mode;
+ enum periph_id periph_id; /* Peripheral ID for this device */
+ unsigned int fifo_size;
+};
+
+static struct spi_bus *spi_get_bus(unsigned dev_index)
+{
+ if (dev_index < bus_count)
+ return &spi_bus[dev_index];
+ debug("%s: invalid bus %d", __func__, dev_index);
+
+ return NULL;
+}
+
+static inline struct exynos_spi_slave *to_exynos_spi(struct spi_slave *slave)
+{
+ return container_of(slave, struct exynos_spi_slave, slave);
+}
+
+/**
+ * Setup the driver private data
+ *
+ * @param bus ID of the bus that the slave is attached to
+ * @param cs ID of the chip select connected to the slave
+ * @param max_hz Required spi frequency
+ * @param mode Required spi mode (clk polarity, clk phase and
+ * master or slave)
+ * @return new device or NULL
+ */
+struct spi_slave *spi_setup_slave(unsigned int busnum, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ struct exynos_spi_slave *spi_slave;
+ struct spi_bus *bus;
+
+ if (!spi_cs_is_valid(busnum, cs)) {
+ debug("%s: Invalid bus/chip select %d, %d\n", __func__,
+ busnum, cs);
+ return NULL;
+ }
+
+ spi_slave = malloc(sizeof(*spi_slave));
+ if (!spi_slave) {
+ debug("%s: Could not allocate spi_slave\n", __func__);
+ return NULL;
+ }
+
+ bus = &spi_bus[busnum];
+ spi_slave->slave.bus = busnum;
+ spi_slave->slave.cs = cs;
+ spi_slave->regs = bus->regs;
+ spi_slave->mode = mode;
+ spi_slave->periph_id = bus->periph_id;
+ if (bus->periph_id == PERIPH_ID_SPI1 ||
+ bus->periph_id == PERIPH_ID_SPI2)
+ spi_slave->fifo_size = 64;
+ else
+ spi_slave->fifo_size = 256;
+
+ spi_slave->freq = bus->frequency;
+ if (max_hz)
+ spi_slave->freq = min(max_hz, spi_slave->freq);
+
+ return &spi_slave->slave;
+}
+
+/**
+ * Free spi controller
+ *
+ * @param slave Pointer to spi_slave to which controller has to
+ * communicate with
+ */
+void spi_free_slave(struct spi_slave *slave)
+{
+ struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
+
+ free(spi_slave);
+}
+
+/**
+ * Flush spi tx, rx fifos and reset the SPI controller
+ *
+ * @param slave Pointer to spi_slave to which controller has to
+ * communicate with
+ */
+static void spi_flush_fifo(struct spi_slave *slave)
+{
+ struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
+ struct exynos_spi *regs = spi_slave->regs;
+
+ clrsetbits_le32(®s->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST);
+ clrbits_le32(®s->ch_cfg, SPI_CH_RST);
+ setbits_le32(®s->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON);
+}
+
+/**
+ * Initialize the spi base registers, set the required clock frequency and
+ * initialize the gpios
+ *
+ * @param slave Pointer to spi_slave to which controller has to
+ * communicate with
+ * @return zero on success else a negative value
+ */
+int spi_claim_bus(struct spi_slave *slave)
+{
+ struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
+ struct exynos_spi *regs = spi_slave->regs;
+ u32 reg = 0;
+ int ret;
+
+ ret = set_spi_clk(spi_slave->periph_id,
+ spi_slave->freq);
+ if (ret < 0) {
+ debug("%s: Failed to setup spi clock\n", __func__);
+ return ret;
+ }
+
+ exynos_pinmux_config(spi_slave->periph_id, PINMUX_FLAG_NONE);
+
+ spi_flush_fifo(slave);
+
+ reg = readl(®s->ch_cfg);
+ reg &= ~(SPI_CH_CPHA_B | SPI_CH_CPOL_L);
+
+ if (spi_slave->mode & SPI_CPHA)
+ reg |= SPI_CH_CPHA_B;
+
+ if (spi_slave->mode & SPI_CPOL)
+ reg |= SPI_CH_CPOL_L;
+
+ writel(reg, ®s->ch_cfg);
+ writel(SPI_FB_DELAY_180, ®s->fb_clk);
+
+ return 0;
+}
+
+/**
+ * Reset the spi H/W and flush the tx and rx fifos
+ *
+ * @param slave Pointer to spi_slave to which controller has to
+ * communicate with
+ */
+void spi_release_bus(struct spi_slave *slave)
+{
+ spi_flush_fifo(slave);
+}
+
+static void spi_get_fifo_levels(struct exynos_spi *regs,
+ int *rx_lvl, int *tx_lvl)
+{
+ uint32_t spi_sts = readl(®s->spi_sts);
+
+ *rx_lvl = (spi_sts >> SPI_RX_LVL_OFFSET) & SPI_FIFO_LVL_MASK;
+ *tx_lvl = (spi_sts >> SPI_TX_LVL_OFFSET) & SPI_FIFO_LVL_MASK;
+}
+
+/**
+ * If there's something to transfer, do a software reset and set a
+ * transaction size.
+ *
+ * @param regs SPI peripheral registers
+ * @param count Number of bytes to transfer
+ */
+static void spi_request_bytes(struct exynos_spi *regs, int count)
+{
+ assert(count && count < (1 << 16));
+ setbits_le32(®s->ch_cfg, SPI_CH_RST);
+ clrbits_le32(®s->ch_cfg, SPI_CH_RST);
+ writel(count | SPI_PACKET_CNT_EN, ®s->pkt_cnt);
+}
+
+static void spi_rx_tx(struct exynos_spi_slave *spi_slave, int todo,
+ void **dinp, void const **doutp)
+{
+ struct exynos_spi *regs = spi_slave->regs;
+ uchar *rxp = *dinp;
+ const uchar *txp = *doutp;
+ int rx_lvl, tx_lvl;
+ uint out_bytes, in_bytes;
+
+ out_bytes = in_bytes = todo;
+
+ /*
+ * If there's something to send, do a software reset and set a
+ * transaction size.
+ */
+ spi_request_bytes(regs, todo);
+
+ /*
+ * Bytes are transmitted/received in pairs. Wait to receive all the
+ * data because then transmission will be done as well.
+ */
+ while (in_bytes) {
+ int temp;
+
+ /* Keep the fifos full/empty. */
+ spi_get_fifo_levels(regs, &rx_lvl, &tx_lvl);
+ if (tx_lvl < spi_slave->fifo_size && out_bytes) {
+ temp = txp ? *txp++ : 0xff;
+ writel(temp, ®s->tx_data);
+ out_bytes--;
+ }
+ if (rx_lvl > 0 && in_bytes) {
+ temp = readl(®s->rx_data);
+ if (rxp)
+ *rxp++ = temp;
+ in_bytes--;
+ }
+ }
+ *dinp = rxp;
+ *doutp = txp;
+}
+
+/**
+ * Transfer and receive data
+ *
+ * @param slave Pointer to spi_slave to which controller has to
+ * communicate with
+ * @param bitlen No of bits to tranfer or receive
+ * @param dout Pointer to transfer buffer
+ * @param din Pointer to receive buffer
+ * @param flags Flags for transfer begin and end
+ * @return zero on success else a negative value
+ */
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
+ void *din, unsigned long flags)
+{
+ struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
+ int upto, todo;
+ int bytelen;
+
+ /* spi core configured to do 8 bit transfers */
+ if (bitlen % 8) {
+ debug("Non byte aligned SPI transfer.\n");
+ return -1;
+ }
+
+ /* Start the transaction, if necessary. */
+ if ((flags & SPI_XFER_BEGIN))
+ spi_cs_activate(slave);
+
+ /* Exynos SPI limits each transfer to 65535 bytes */
+ bytelen = bitlen / 8;
+ for (upto = 0; upto < bytelen; upto += todo) {
+ todo = min(bytelen - upto, (1 << 16) - 1);
+ spi_rx_tx(spi_slave, todo, &din, &dout);
+ }
+
+ /* Stop the transaction, if necessary. */
+ if ((flags & SPI_XFER_END))
+ spi_cs_deactivate(slave);
+
+ return 0;
+}
+
+/**
+ * Validates the bus and chip select numbers
+ *
+ * @param bus ID of the bus that the slave is attached to
+ * @param cs ID of the chip select connected to the slave
+ * @return one on success else zero
+ */
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return spi_get_bus(bus) && cs == 0;
+}
+
+/**
+ * Activate the CS by driving it LOW
+ *
+ * @param slave Pointer to spi_slave to which controller has to
+ * communicate with
+ */
+void spi_cs_activate(struct spi_slave *slave)
+{
+ struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
+
+ clrbits_le32(&spi_slave->regs->cs_reg, SPI_SLAVE_SIG_INACT);
+ debug("Activate CS, bus %d\n", spi_slave->slave.bus);
+}
+
+/**
+ * Deactivate the CS by driving it HIGH
+ *
+ * @param slave Pointer to spi_slave to which controller has to
+ * communicate with
+ */
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
+
+ setbits_le32(&spi_slave->regs->cs_reg, SPI_SLAVE_SIG_INACT);
+ debug("Deactivate CS, bus %d\n", spi_slave->slave.bus);
+}
+
+static inline struct exynos_spi *get_spi_base(int dev_index)
+{
+ if (dev_index < 3)
+ return (struct exynos_spi *)samsung_get_base_spi() + dev_index;
+ else
+ return (struct exynos_spi *)samsung_get_base_spi_isp() +
+ (dev_index - 3);
+}
+
+/*
+ * Read the SPI config from the device tree node.
+ *
+ * @param blob FDT blob to read from
+ * @param node Node offset to read from
+ * @param bus SPI bus structure to fill with information
+ * @return 0 if ok, or -FDT_ERR_NOTFOUND if something was missing
+ */
+static int spi_get_config(const void *blob, int node, struct spi_bus *bus)
+{
+ bus->node = node;
+ bus->regs = (struct exynos_spi *)fdtdec_get_addr(blob, node, "reg");
+ bus->periph_id = pinmux_decode_periph_id(blob, node);
+
+ if (bus->periph_id == PERIPH_ID_NONE) {
+ debug("%s: Invalid peripheral ID %d\n", __func__,
+ bus->periph_id);
+ return -FDT_ERR_NOTFOUND;
+ }
+
+ /* Use 500KHz as a suitable default */
+ bus->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
+ 500000);
+
+ return 0;
+}
+
+/*
+ * Process a list of nodes, adding them to our list of SPI ports.
+ *
+ * @param blob fdt blob
+ * @param node_list list of nodes to process (any <=0 are ignored)
+ * @param count number of nodes to process
+ * @param is_dvc 1 if these are DVC ports, 0 if standard I2C
+ * @return 0 if ok, -1 on error
+ */
+static int process_nodes(const void *blob, int node_list[], int count)
+{
+ int i;
+
+ /* build the i2c_controllers[] for each controller */
+ for (i = 0; i < count; i++) {
+ int node = node_list[i];
+ struct spi_bus *bus;
+
+ if (node <= 0)
+ continue;
+
+ bus = &spi_bus[i];
+ if (spi_get_config(blob, node, bus)) {
+ printf("exynos spi_init: failed to decode bus %d\n",
+ i);
+ return -1;
+ }
+
+ debug("spi: controller bus %d at %p, periph_id %d\n",
+ i, bus->regs, bus->periph_id);
+ bus->inited = 1;
+ bus_count++;
+ }
+
+ return 0;
+}
+
+/* Sadly there is no error return from this function */
+void spi_init(void)
+{
+ int count;
+
+#ifdef CONFIG_OF_CONTROL
+ int node_list[EXYNOS5_SPI_NUM_CONTROLLERS];
+ const void *blob = gd->fdt_blob;
+
+ count = fdtdec_find_aliases_for_id(blob, "spi",
+ COMPAT_SAMSUNG_EXYNOS_SPI, node_list,
+ EXYNOS5_SPI_NUM_CONTROLLERS);
+ if (process_nodes(blob, node_list, count))
+ return;
+
+#else
+ struct spi_bus *bus;
+
+ for (count = 0; count < EXYNOS5_SPI_NUM_CONTROLLERS; count++) {
+ bus = &spi_bus[count];
+ bus->regs = get_spi_base(count);
+ bus->periph_id = PERIPH_ID_SPI0 + count;
+
+ /* Although Exynos5 supports upto 50Mhz speed,
+ * we are setting it to 10Mhz for safe side
+ */
+ bus->frequency = 10000000;
+ bus->inited = 1;
+ bus->node = 0;
+ bus_count = EXYNOS5_SPI_NUM_CONTROLLERS;
+ }
+#endif
+}
{
struct spi_slave *slave;
u32 data;
- u32 kwspi_mpp_config[] = { 0, 0 };
+ static const u32 kwspi_mpp_config[2][2] = {
+ { MPP0_SPI_SCn, 0 }, /* if cs == 0 */
+ { MPP7_SPI_SCn, 0 } /* if cs != 0 */
+ };
if (!spi_cs_is_valid(bus, cs))
return NULL;
writel(KWSPI_IRQMASK, &spireg->irq_mask);
/* program mpp registers to select SPI_CSn */
- if (cs) {
- kwspi_mpp_config[0] = MPP7_SPI_SCn;
- } else {
- kwspi_mpp_config[0] = MPP0_SPI_SCn;
- }
- kirkwood_mpp_conf(kwspi_mpp_config, cs_spi_mpp_back);
+ kirkwood_mpp_conf(kwspi_mpp_config[cs ? 1 : 0], cs_spi_mpp_back);
return slave;
}
reg_ctrl = reg_read(®s->ctrl);
/* Reset spi */
- reg_write(®s->ctrl, 0);
- reg_write(®s->ctrl, (reg_ctrl | 0x1));
+ reg_write(®s->ctrl, (reg_ctrl & ~MXC_CSPICTRL_EN));
+ reg_write(®s->ctrl, (reg_ctrl | MXC_CSPICTRL_EN));
/*
* The following computation is taken directly from Freescale's code.
if (cs > 3) {
mxcs->gpio = cs >> 8;
cs &= 3;
- ret = gpio_direction_output(mxcs->gpio, 0);
+ ret = gpio_direction_output(mxcs->gpio, !(mxcs->ss_pol));
if (ret) {
printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio);
return -EINVAL;
return NULL;
}
+ mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;
+
ret = decode_cs(mxcs, cs);
if (ret < 0) {
free(mxcs);
mxcs->slave.bus = bus;
mxcs->slave.cs = cs;
mxcs->base = spi_bases[bus];
- mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;
ret = spi_cfg_mxc(mxcs, cs, max_hz, mode);
if (ret) {
writel(OMAP3_MCSPI_WAKEUPENABLE_WKEN, &ds->regs->wakeupenable);
}
+static void omap3_spi_write_chconf(struct omap3_spi_slave *ds, int val)
+{
+ writel(val, &ds->regs->channel[ds->slave.cs].chconf);
+ /* Flash post writes to make immediate effect */
+ readl(&ds->regs->channel[ds->slave.cs].chconf);
+}
+
+static void omap3_spi_set_enable(struct omap3_spi_slave *ds, int enable)
+{
+ writel(enable, &ds->regs->channel[ds->slave.cs].chctrl);
+ /* Flash post writes to make immediate effect */
+ readl(&ds->regs->channel[ds->slave.cs].chctrl);
+}
+
void spi_init()
{
/* do nothing */
/* Transmit & receive mode */
conf &= ~OMAP3_MCSPI_CHCONF_TRM_MASK;
- writel(conf, &ds->regs->channel[ds->slave.cs].chconf);
+ omap3_spi_write_chconf(ds,conf);
return 0;
}
int timeout = SPI_WAIT_TIMEOUT;
int chconf = readl(&ds->regs->channel[ds->slave.cs].chconf);
- if (flags & SPI_XFER_BEGIN)
- writel(OMAP3_MCSPI_CHCTRL_EN,
- &ds->regs->channel[ds->slave.cs].chctrl);
+ /* Enable the channel */
+ omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_EN);
chconf &= ~OMAP3_MCSPI_CHCONF_TRM_MASK;
chconf |= OMAP3_MCSPI_CHCONF_TRM_TX_ONLY;
chconf |= OMAP3_MCSPI_CHCONF_FORCE;
- writel(chconf, &ds->regs->channel[ds->slave.cs].chconf);
+ omap3_spi_write_chconf(ds,chconf);
for (i = 0; i < len; i++) {
/* wait till TX register is empty (TXS == 1) */
writel(txp[i], &ds->regs->channel[ds->slave.cs].tx);
}
+ /* wait to finish of transfer */
+ while (!(readl(&ds->regs->channel[ds->slave.cs].chstat) &
+ OMAP3_MCSPI_CHSTAT_EOT));
+
+ /* Disable the channel otherwise the next immediate RX will get affected */
+ omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_DIS);
+
if (flags & SPI_XFER_END) {
- /* wait to finish of transfer */
- while (!(readl(&ds->regs->channel[ds->slave.cs].chstat) &
- OMAP3_MCSPI_CHSTAT_EOT));
chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
- writel(chconf, &ds->regs->channel[ds->slave.cs].chconf);
-
- writel(0, &ds->regs->channel[ds->slave.cs].chctrl);
+ omap3_spi_write_chconf(ds,chconf);
}
return 0;
}
int timeout = SPI_WAIT_TIMEOUT;
int chconf = readl(&ds->regs->channel[ds->slave.cs].chconf);
- if (flags & SPI_XFER_BEGIN)
- writel(OMAP3_MCSPI_CHCTRL_EN,
- &ds->regs->channel[ds->slave.cs].chctrl);
+ /* Enable the channel */
+ omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_EN);
chconf &= ~OMAP3_MCSPI_CHCONF_TRM_MASK;
chconf |= OMAP3_MCSPI_CHCONF_TRM_RX_ONLY;
chconf |= OMAP3_MCSPI_CHCONF_FORCE;
- writel(chconf, &ds->regs->channel[ds->slave.cs].chconf);
+ omap3_spi_write_chconf(ds,chconf);
writel(0, &ds->regs->channel[ds->slave.cs].tx);
return -1;
}
}
+
+ /* Disable the channel to prevent furher receiving */
+ if(i == (len - 1))
+ omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_DIS);
+
/* Read the data */
rxp[i] = readl(&ds->regs->channel[ds->slave.cs].rx);
}
if (flags & SPI_XFER_END) {
chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
- writel(chconf, &ds->regs->channel[ds->slave.cs].chconf);
-
- writel(0, &ds->regs->channel[ds->slave.cs].chctrl);
+ omap3_spi_write_chconf(ds,chconf);
}
return 0;
int i=0;
/*Enable SPI channel*/
- if (flags & SPI_XFER_BEGIN)
- writel(OMAP3_MCSPI_CHCTRL_EN,
- &ds->regs->channel[ds->slave.cs].chctrl);
+ omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_EN);
/*set TRANSMIT-RECEIVE Mode*/
chconf &= ~OMAP3_MCSPI_CHCONF_TRM_MASK;
chconf |= OMAP3_MCSPI_CHCONF_FORCE;
- writel(chconf, &ds->regs->channel[ds->slave.cs].chconf);
+ omap3_spi_write_chconf(ds,chconf);
/*Shift in and out 1 byte at time*/
for (i=0; i < len; i++){
/* Read the data */
rxp[i] = readl(&ds->regs->channel[ds->slave.cs].rx);
}
+ /* Disable the channel */
+ omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_DIS);
/*if transfer must be terminated disable the channel*/
if (flags & SPI_XFER_END) {
chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
- writel(chconf, &ds->regs->channel[ds->slave.cs].chconf);
-
- writel(0, &ds->regs->channel[ds->slave.cs].chctrl);
+ omap3_spi_write_chconf(ds,chconf);
}
return 0;
int chconf = readl(&ds->regs->channel[ds->slave.cs].chconf);
if (flags & SPI_XFER_BEGIN) {
- writel(OMAP3_MCSPI_CHCTRL_EN,
- &ds->regs->channel[ds->slave.cs].chctrl);
+ omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_EN);
chconf |= OMAP3_MCSPI_CHCONF_FORCE;
- writel(chconf,
- &ds->regs->channel[ds->slave.cs].chconf);
+ omap3_spi_write_chconf(ds,chconf);
}
if (flags & SPI_XFER_END) {
chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
- writel(chconf,
- &ds->regs->channel[ds->slave.cs].chconf);
- writel(0, &ds->regs->channel[ds->slave.cs].chctrl);
+ omap3_spi_write_chconf(ds,chconf);
+ omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_DIS);
}
ret = 0;
} else {
#define OMAP3_MCSPI_CHSTAT_EOT (1 << 2)
#define OMAP3_MCSPI_CHCTRL_EN (1 << 0)
+#define OMAP3_MCSPI_CHCTRL_DIS (0 << 0)
#define OMAP3_MCSPI_WAKEUPENABLE_WKEN (1 << 0)
static struct usb_string g_dnl_string_defs[] = {
{ 0, manufacturer, },
{ 1, product, },
+ { } /* end of list */
};
static struct usb_gadget_strings g_dnl_string_tab = {
static int g_dnl_unbind(struct usb_composite_dev *cdev)
{
- debug("%s\n", __func__);
+ struct usb_gadget *gadget = cdev->gadget;
+
+ debug("%s: calling usb_gadget_disconnect for "
+ "controller '%s'\n", shortname, gadget->name);
+ usb_gadget_disconnect(gadget);
+
return 0;
}
device_desc.bcdDevice = __constant_cpu_to_le16(0x9999);
}
+ debug("%s: calling usb_gadget_connect for "
+ "controller '%s'\n", shortname, gadget->name);
+ usb_gadget_connect(gadget);
+
return 0;
error:
#include <asm/io.h>
#include <asm/arch/pxa.h>
-#include <usbdescriptors.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
#include <usb/lin_gadget_compat.h>
*/
#include <common.h>
+#include <fdtdec.h>
+#include <libfdt.h>
+#include <malloc.h>
#include <usb.h>
#include <asm/arch/cpu.h>
#include <asm/arch/ehci.h>
#include <asm/arch/system.h>
#include <asm/arch/power.h>
+#include <asm-generic/errno.h>
+#include <linux/compat.h>
#include "ehci.h"
+/* Declare global data pointer */
+DECLARE_GLOBAL_DATA_PTR;
+
+/**
+ * Contains pointers to register base addresses
+ * for the usb controller.
+ */
+struct exynos_ehci {
+ struct exynos_usb_phy *usb;
+ unsigned int *hcd;
+};
+
+static int exynos_usb_parse_dt(const void *blob, struct exynos_ehci *exynos)
+{
+ unsigned int node;
+ int depth;
+
+ node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS_EHCI);
+ if (node <= 0) {
+ debug("EHCI: Can't get device node for ehci\n");
+ return -ENODEV;
+ }
+
+ /*
+ * Get the base address for EHCI controller from the device node
+ */
+ exynos->hcd = (unsigned int *)fdtdec_get_addr(blob, node, "reg");
+ if (exynos->hcd == NULL) {
+ debug("Can't get the EHCI register address\n");
+ return -ENXIO;
+ }
+
+ depth = 0;
+ node = fdtdec_next_compatible_subnode(blob, node,
+ COMPAT_SAMSUNG_EXYNOS_USB_PHY, &depth);
+ if (node <= 0) {
+ debug("EHCI: Can't get device node for usb-phy controller\n");
+ return -ENODEV;
+ }
+
+ /*
+ * Get the base address for usbphy from the device node
+ */
+ exynos->usb = (struct exynos_usb_phy *)fdtdec_get_addr(blob, node,
+ "reg");
+ if (exynos->usb == NULL) {
+ debug("Can't get the usbphy register address\n");
+ return -ENXIO;
+ }
+
+ return 0;
+}
+
/* Setup the EHCI host controller. */
static void setup_usb_phy(struct exynos_usb_phy *usb)
{
*/
int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
- struct exynos_usb_phy *usb;
+ struct exynos_ehci *exynos = NULL;
+
+ exynos = (struct exynos_ehci *)
+ kzalloc(sizeof(struct exynos_ehci), GFP_KERNEL);
+ if (!exynos) {
+ debug("failed to allocate exynos ehci context\n");
+ return -ENOMEM;
+ }
- usb = (struct exynos_usb_phy *)samsung_get_base_usb_phy();
- setup_usb_phy(usb);
+ exynos_usb_parse_dt(gd->fdt_blob, exynos);
- *hccr = (struct ehci_hccr *)samsung_get_base_usb_ehci();
+ setup_usb_phy(exynos->usb);
+
+ *hccr = (struct ehci_hccr *)(exynos->hcd);
*hcor = (struct ehci_hcor *)((uint32_t) *hccr
+ HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
(uint32_t)*hccr, (uint32_t)*hcor,
(uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
+ kfree(exynos);
+
return 0;
}
*/
int ehci_hcd_stop(int index)
{
- struct exynos_usb_phy *usb;
+ struct exynos_ehci *exynos = NULL;
+
+ exynos = (struct exynos_ehci *)
+ kzalloc(sizeof(struct exynos_ehci), GFP_KERNEL);
+ if (!exynos) {
+ debug("failed to allocate exynos ehci context\n");
+ return -ENOMEM;
+ }
+
+ exynos_usb_parse_dt(gd->fdt_blob, exynos);
+
+ reset_usb_phy(exynos->usb);
- usb = (struct exynos_usb_phy *)samsung_get_base_usb_phy();
- reset_usb_phy(usb);
+ kfree(exynos);
return 0;
}
#define MX5_USBOTHER_REGS_OFFSET 0x800
-#define MXC_OTG_OFFSET 0
-#define MXC_H1_OFFSET 0x200
-#define MXC_H2_OFFSET 0x400
+#define MXC_OTG_OFFSET 0
+#define MXC_H1_OFFSET 0x200
+#define MXC_H2_OFFSET 0x400
+#define MXC_H3_OFFSET 0x600
#define MXC_USBCTRL_OFFSET 0
#define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8
#define MXC_USB_PHY_CTR_FUNC2_OFFSET 0xc
#define MXC_USB_CTRL_1_OFFSET 0x10
#define MXC_USBH2CTRL_OFFSET 0x14
+#define MXC_USBH3CTRL_OFFSET 0x18
/* USB_CTRL */
-#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable */
-#define MXC_OTG_UCTRL_OPM_BIT (1 << 24) /* OTG power mask */
-#define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) /* Host1 ULPI interrupt enable */
-#define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) /* HOST1 wakeup intr enable */
-#define MXC_H1_UCTRL_H1PM_BIT (1 << 8) /* HOST1 power mask */
+/* OTG wakeup intr enable */
+#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27)
+/* OTG power mask */
+#define MXC_OTG_UCTRL_OPM_BIT (1 << 24)
+/* OTG power pin polarity */
+#define MXC_OTG_UCTRL_O_PWR_POL_BIT (1 << 24)
+/* Host1 ULPI interrupt enable */
+#define MXC_H1_UCTRL_H1UIE_BIT (1 << 12)
+/* HOST1 wakeup intr enable */
+#define MXC_H1_UCTRL_H1WIE_BIT (1 << 11)
+/* HOST1 power mask */
+#define MXC_H1_UCTRL_H1PM_BIT (1 << 8)
+/* HOST1 power pin polarity */
+#define MXC_H1_UCTRL_H1_PWR_POL_BIT (1 << 8)
/* USB_PHY_CTRL_FUNC */
-#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */
-#define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */
+/* OTG Polarity of Overcurrent */
+#define MXC_OTG_PHYCTRL_OC_POL_BIT (1 << 9)
+/* OTG Disable Overcurrent Event */
+#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8)
+/* UH1 Polarity of Overcurrent */
+#define MXC_H1_OC_POL_BIT (1 << 6)
+/* UH1 Disable Overcurrent Event */
+#define MXC_H1_OC_DIS_BIT (1 << 5)
+/* OTG Power Pin Polarity */
+#define MXC_OTG_PHYCTRL_PWR_POL_BIT (1 << 3)
/* USBH2CTRL */
-#define MXC_H2_UCTRL_H2UIE_BIT (1 << 8)
-#define MXC_H2_UCTRL_H2WIE_BIT (1 << 7)
-#define MXC_H2_UCTRL_H2PM_BIT (1 << 4)
+#define MXC_H2_UCTRL_H2_OC_POL_BIT (1 << 31)
+#define MXC_H2_UCTRL_H2_OC_DIS_BIT (1 << 30)
+#define MXC_H2_UCTRL_H2UIE_BIT (1 << 8)
+#define MXC_H2_UCTRL_H2WIE_BIT (1 << 7)
+#define MXC_H2_UCTRL_H2PM_BIT (1 << 4)
+#define MXC_H2_UCTRL_H2_PWR_POL_BIT (1 << 4)
+
+/* USBH3CTRL */
+#define MXC_H3_UCTRL_H3_OC_POL_BIT (1 << 31)
+#define MXC_H3_UCTRL_H3_OC_DIS_BIT (1 << 30)
+#define MXC_H3_UCTRL_H3UIE_BIT (1 << 8)
+#define MXC_H3_UCTRL_H3WIE_BIT (1 << 7)
+#define MXC_H3_UCTRL_H3_PWR_POL_BIT (1 << 4)
/* USB_CTRL_1 */
-#define MXC_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
+#define MXC_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
/* USB pin configuration */
#define USB_PAD_CONFIG (PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST | \
if (flags & MXC_EHCI_INTERNAL_PHY) {
v = __raw_readl(usbother_base +
MXC_USB_PHY_CTR_FUNC_OFFSET);
+ if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
+ v |= MXC_OTG_PHYCTRL_OC_POL_BIT;
+ else
+ v &= ~MXC_OTG_PHYCTRL_OC_POL_BIT;
if (flags & MXC_EHCI_POWER_PINS_ENABLED)
+ /* OC/USBPWR is used */
+ v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
+ else
/* OC/USBPWR is not used */
v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
+#ifdef CONFIG_MX51
+ if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+ v |= MXC_OTG_PHYCTRL_PWR_POL_BIT;
else
- /* OC/USBPWR is used */
- v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
+ v &= ~MXC_OTG_PHYCTRL_PWR_POL_BIT;
+#endif
__raw_writel(v, usbother_base +
MXC_USB_PHY_CTR_FUNC_OFFSET);
v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
+#ifdef CONFIG_MX51
if (flags & MXC_EHCI_POWER_PINS_ENABLED)
+ v &= ~MXC_OTG_UCTRL_OPM_BIT;
+ else
v |= MXC_OTG_UCTRL_OPM_BIT;
+#endif
+#ifdef CONFIG_MX53
+ if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+ v |= MXC_OTG_UCTRL_O_PWR_POL_BIT;
else
- v &= ~MXC_OTG_UCTRL_OPM_BIT;
+ v &= ~MXC_OTG_UCTRL_O_PWR_POL_BIT;
+#endif
__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
}
break;
- case 1: /* Host 1 Host ULPI */
+ case 1: /* Host 1 ULPI */
#ifdef CONFIG_MX51
/* The clock for the USBH1 ULPI port will come externally
from the PHY. */
#endif
v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
+#ifdef CONFIG_MX51
if (flags & MXC_EHCI_POWER_PINS_ENABLED)
- v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used */
+ v &= ~MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask unused */
else
- v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used */
+ v |= MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask used */
+#endif
+#ifdef CONFIG_MX53
+ if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+ v |= MXC_H1_UCTRL_H1_PWR_POL_BIT;
+ else
+ v &= ~MXC_H1_UCTRL_H1_PWR_POL_BIT;
+#endif
__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
+ if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
+ v |= MXC_H1_OC_POL_BIT;
+ else
+ v &= ~MXC_H1_OC_POL_BIT;
if (flags & MXC_EHCI_POWER_PINS_ENABLED)
v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */
else
break;
case 2: /* Host 2 ULPI */
v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
+#ifdef CONFIG_MX51
if (flags & MXC_EHCI_POWER_PINS_ENABLED)
- v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used */
+ v &= ~MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask unused */
else
- v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used */
-
+ v |= MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask used */
+#endif
+#ifdef CONFIG_MX53
+ if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
+ v |= MXC_H2_UCTRL_H2_OC_POL_BIT;
+ else
+ v &= ~MXC_H2_UCTRL_H2_OC_POL_BIT;
+ if (flags & MXC_EHCI_POWER_PINS_ENABLED)
+ v &= ~MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is used */
+ else
+ v |= MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is not used */
+ if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+ v |= MXC_H2_UCTRL_H2_PWR_POL_BIT;
+ else
+ v &= ~MXC_H2_UCTRL_H2_PWR_POL_BIT;
+#endif
__raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
break;
+#ifdef CONFIG_MX53
+ case 3: /* Host 3 ULPI */
+ v = __raw_readl(usbother_base + MXC_USBH3CTRL_OFFSET);
+ if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
+ v |= MXC_H3_UCTRL_H3_OC_POL_BIT;
+ else
+ v &= ~MXC_H3_UCTRL_H3_OC_POL_BIT;
+ if (flags & MXC_EHCI_POWER_PINS_ENABLED)
+ v &= ~MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is used */
+ else
+ v |= MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is not used */
+ if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+ v |= MXC_H3_UCTRL_H3_PWR_POL_BIT;
+ else
+ v &= ~MXC_H3_UCTRL_H3_PWR_POL_BIT;
+ __raw_writel(v, usbother_base + MXC_USBH3CTRL_OFFSET);
+ break;
+#endif
}
return ret;
}
-void __board_ehci_hcd_postinit(struct usb_ehci *ehci, int port)
+int __weak board_ehci_hcd_init(int port)
{
+ return 0;
}
-void board_ehci_hcd_postinit(struct usb_ehci *ehci, int port)
- __attribute((weak, alias("__board_ehci_hcd_postinit")));
+void __weak board_ehci_hcd_postinit(struct usb_ehci *ehci, int port)
+{
+}
int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
__raw_writel(val, usbother_base + USB_H1_CTRL_OFFSET);
}
+int __weak board_ehci_hcd_init(int port)
+{
+ return 0;
+}
+
int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
struct usb_ehci *ehci;
#define USBCTRL_OTGBASE_OFFSET 0x600
-#ifdef CONFIG_MX25
-#define MX25_USB_CTRL_IP_PUE_DOWN_BIT (1<<6)
-#define MX25_USB_CTRL_HSTD_BIT (1<<5)
-#define MX25_USB_CTRL_USBTE_BIT (1<<4)
-#define MX25_USB_CTRL_OCPOL_OTG_BIT (1<<3)
-#endif
+#define MX25_OTG_SIC_SHIFT 29
+#define MX25_OTG_SIC_MASK (0x3 << MX25_OTG_SIC_SHIFT)
+#define MX25_OTG_PM_BIT (1 << 24)
+#define MX25_OTG_PP_BIT (1 << 11)
+#define MX25_OTG_OCPOL_BIT (1 << 3)
+
+#define MX25_H1_SIC_SHIFT 21
+#define MX25_H1_SIC_MASK (0x3 << MX25_H1_SIC_SHIFT)
+#define MX25_H1_PP_BIT (1 << 18)
+#define MX25_H1_PM_BIT (1 << 16)
+#define MX25_H1_IPPUE_UP_BIT (1 << 7)
+#define MX25_H1_IPPUE_DOWN_BIT (1 << 6)
+#define MX25_H1_TLL_BIT (1 << 5)
+#define MX25_H1_USBTE_BIT (1 << 4)
+#define MX25_H1_OCPOL_BIT (1 << 2)
-#ifdef CONFIG_MX31
#define MX31_OTG_SIC_SHIFT 29
#define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT)
#define MX31_OTG_PM_BIT (1 << 24)
#define MX31_H1_SIC_MASK (0x3 << MX31_H1_SIC_SHIFT)
#define MX31_H1_PM_BIT (1 << 8)
#define MX31_H1_DT_BIT (1 << 4)
-#endif
+
+#define MX35_OTG_SIC_SHIFT 29
+#define MX35_OTG_SIC_MASK (0x3 << MX35_OTG_SIC_SHIFT)
+#define MX35_OTG_PM_BIT (1 << 24)
+#define MX35_OTG_PP_BIT (1 << 11)
+#define MX35_OTG_OCPOL_BIT (1 << 3)
+
+#define MX35_H1_SIC_SHIFT 21
+#define MX35_H1_SIC_MASK (0x3 << MX35_H1_SIC_SHIFT)
+#define MX35_H1_PP_BIT (1 << 18)
+#define MX35_H1_PM_BIT (1 << 16)
+#define MX35_H1_IPPUE_UP_BIT (1 << 7)
+#define MX35_H1_IPPUE_DOWN_BIT (1 << 6)
+#define MX35_H1_TLL_BIT (1 << 5)
+#define MX35_H1_USBTE_BIT (1 << 4)
+#define MX35_H1_OCPOL_BIT (1 << 2)
static int mxc_set_usbcontrol(int port, unsigned int flags)
{
unsigned int v;
-#ifdef CONFIG_MX25
- v = MX25_USB_CTRL_IP_PUE_DOWN_BIT | MX25_USB_CTRL_HSTD_BIT |
- MX25_USB_CTRL_USBTE_BIT | MX25_USB_CTRL_OCPOL_OTG_BIT;
-#endif
+ v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
+#if defined(CONFIG_MX25)
+ switch (port) {
+ case 0: /* OTG port */
+ v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT | MX25_OTG_PP_BIT |
+ MX25_OTG_OCPOL_BIT);
+ v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_OTG_SIC_SHIFT;
-#ifdef CONFIG_MX31
- v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
-
- switch (port) {
- case 0: /* OTG port */
- v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
- v |= (flags & MXC_EHCI_INTERFACE_MASK)
- << MX31_OTG_SIC_SHIFT;
- if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
- v |= MX31_OTG_PM_BIT;
-
- break;
- case 1: /* H1 port */
- v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT |
- MX31_H1_DT_BIT);
- v |= (flags & MXC_EHCI_INTERFACE_MASK)
- << MX31_H1_SIC_SHIFT;
- if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
- v |= MX31_H1_PM_BIT;
-
- if (!(flags & MXC_EHCI_TTL_ENABLED))
- v |= MX31_H1_DT_BIT;
-
- break;
- case 2: /* H2 port */
- v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT |
- MX31_H2_DT_BIT);
- v |= (flags & MXC_EHCI_INTERFACE_MASK)
- << MX31_H2_SIC_SHIFT;
- if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
- v |= MX31_H2_PM_BIT;
-
- if (!(flags & MXC_EHCI_TTL_ENABLED))
- v |= MX31_H2_DT_BIT;
-
- break;
- default:
- return -EINVAL;
- }
-#endif
+ if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+ v |= MX25_OTG_PM_BIT;
+
+ if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+ v |= MX25_OTG_PP_BIT;
+
+ if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
+ v |= MX25_OTG_OCPOL_BIT;
+
+ break;
+ case 1: /* H1 port */
+ v &= ~(MX25_H1_SIC_MASK | MX25_H1_PM_BIT | MX25_H1_PP_BIT |
+ MX25_H1_OCPOL_BIT | MX25_H1_TLL_BIT |
+ MX25_H1_USBTE_BIT | MX25_H1_IPPUE_DOWN_BIT |
+ MX25_H1_IPPUE_UP_BIT);
+ v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_H1_SIC_SHIFT;
+
+ if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+ v |= MX25_H1_PM_BIT;
+
+ if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+ v |= MX25_H1_PP_BIT;
+
+ if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
+ v |= MX25_H1_OCPOL_BIT;
+
+ if (!(flags & MXC_EHCI_TTL_ENABLED))
+ v |= MX25_H1_TLL_BIT;
+
+ if (flags & MXC_EHCI_INTERNAL_PHY)
+ v |= MX25_H1_USBTE_BIT;
+
+ if (flags & MXC_EHCI_IPPUE_DOWN)
+ v |= MX25_H1_IPPUE_DOWN_BIT;
+
+ if (flags & MXC_EHCI_IPPUE_UP)
+ v |= MX25_H1_IPPUE_UP_BIT;
+
+ break;
+ default:
+ return -EINVAL;
+ }
+#elif defined(CONFIG_MX31)
+ switch (port) {
+ case 0: /* OTG port */
+ v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
+ v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_OTG_SIC_SHIFT;
+
+ if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+ v |= MX31_OTG_PM_BIT;
+ break;
+ case 1: /* H1 port */
+ v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT);
+ v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H1_SIC_SHIFT;
+
+ if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+ v |= MX31_H1_PM_BIT;
+
+ if (!(flags & MXC_EHCI_TTL_ENABLED))
+ v |= MX31_H1_DT_BIT;
+
+ break;
+ case 2: /* H2 port */
+ v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT);
+ v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H2_SIC_SHIFT;
+
+ if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+ v |= MX31_H2_PM_BIT;
+
+ if (!(flags & MXC_EHCI_TTL_ENABLED))
+ v |= MX31_H2_DT_BIT;
+
+ break;
+ default:
+ return -EINVAL;
+ }
+#elif defined(CONFIG_MX35)
+ switch (port) {
+ case 0: /* OTG port */
+ v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT | MX35_OTG_PP_BIT |
+ MX35_OTG_OCPOL_BIT);
+ v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_OTG_SIC_SHIFT;
+
+ if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+ v |= MX35_OTG_PM_BIT;
+
+ if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+ v |= MX35_OTG_PP_BIT;
+
+ if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
+ v |= MX35_OTG_OCPOL_BIT;
+
+ break;
+ case 1: /* H1 port */
+ v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_PP_BIT |
+ MX35_H1_OCPOL_BIT | MX35_H1_TLL_BIT |
+ MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT |
+ MX35_H1_IPPUE_UP_BIT);
+ v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_H1_SIC_SHIFT;
+
+ if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+ v |= MX35_H1_PM_BIT;
+
+ if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+ v |= MX35_H1_PP_BIT;
+
+ if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
+ v |= MX35_H1_OCPOL_BIT;
+
+ if (!(flags & MXC_EHCI_TTL_ENABLED))
+ v |= MX35_H1_TLL_BIT;
+
+ if (flags & MXC_EHCI_INTERNAL_PHY)
+ v |= MX35_H1_USBTE_BIT;
+
+ if (flags & MXC_EHCI_IPPUE_DOWN)
+ v |= MX35_H1_IPPUE_DOWN_BIT;
+
+ if (flags & MXC_EHCI_IPPUE_UP)
+ v |= MX35_H1_IPPUE_UP_BIT;
+
+ break;
+ default:
+ return -EINVAL;
+ }
+#else
+#error MXC EHCI USB driver not supported on this platform
+#endif
writel(v, IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
+
return 0;
}
udelay(80);
ehci = (struct usb_ehci *)(IMX_USB_BASE +
- (0x200 * CONFIG_MXC_USB_PORT));
+ IMX_USB_PORT_OFFSET * CONFIG_MXC_USB_PORT);
*hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
*hcor = (struct ehci_hcor *)((uint32_t) *hccr +
HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
setbits_le32(&ehci->usbmode, CM_HOST);
__raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);
+#ifdef CONFIG_MX35
+ /* Workaround for ENGcm11601 */
+ __raw_writel(0, &ehci->sbuscfg);
+#endif
udelay(10000);
writel(get_pllb_init(), &pmc->pllbr);
while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB)
;
-#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
+#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) || \
+ defined(CONFIG_AT91SAM9X5)
/* Enable UPLL */
writel(readl(&pmc->uckr) | AT91_PMC_UPLLEN | AT91_PMC_BIASEN,
&pmc->uckr);
writel(0, &pmc->pllbr);
while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != 0)
;
-#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
+#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) || \
+ defined(CONFIG_AT91SAM9X5)
/* Disable UPLL */
writel(readl(&pmc->uckr) & (~AT91_PMC_UPLLEN), &pmc->uckr);
while ((readl(&pmc->sr) & AT91_PMC_LOCKU) == AT91_PMC_LOCKU)
COBJS-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o videomodes.o
COBJS-$(CONFIG_S6E8AX0) += s6e8ax0.o
COBJS-$(CONFIG_S6E63D6) += s6e63d6.o
+COBJS-$(CONFIG_LD9040) += ld9040.o
COBJS-$(CONFIG_SED156X) += sed156x.o
COBJS-$(CONFIG_VIDEO_AMBA) += amba.o
COBJS-$(CONFIG_VIDEO_COREBOOT) += coreboot_fb.o
COBJS-$(CONFIG_VIDEO_SED13806) += sed13806.o
COBJS-$(CONFIG_VIDEO_SM501) += sm501.o
COBJS-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o videomodes.o
+COBJS-$(CONFIG_VIDEO_TEGRA) += tegra.o
COBJS-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o
COBJS := $(sort $(COBJS-y))
{
unsigned int ret;
struct edp_device_info *edp_info;
- struct edp_disp_info disp_info;
edp_info = kzalloc(sizeof(struct edp_device_info), GFP_KERNEL);
if (!edp_info) {
debug("failed to get edp_info data.\n");
return -EFAULT;
}
- disp_info = edp_info->disp_info;
exynos_dp_disp_info(&edp_info->disp_info);
static void exynos_lcd_init(vidinfo_t *vid)
{
exynos_fimd_lcd_init(vid);
+
+ /* Enable flushing after LCD writes if requested */
+ lcd_set_flush_dcache(1);
}
+#ifdef CONFIG_CMD_BMP
static void draw_logo(void)
{
int x, y;
ulong addr;
- x = ((panel_width - panel_info.logo_width) >> 1);
- y = ((panel_height - panel_info.logo_height) >> 1) - 4;
+ if (panel_width >= panel_info.logo_width) {
+ x = ((panel_width - panel_info.logo_width) >> 1);
+ } else {
+ x = 0;
+ printf("Warning: image width is bigger than display width\n");
+ }
+
+ if (panel_height >= panel_info.logo_height) {
+ y = ((panel_height - panel_info.logo_height) >> 1) - 4;
+ } else {
+ y = 0;
+ printf("Warning: image height is bigger than display height\n");
+ }
addr = panel_info.logo_addr;
bmp_display(addr, x, y);
}
+#endif
static void lcd_panel_on(vidinfo_t *vid)
{
if (panel_info.logo_on) {
memset(lcd_base, 0, panel_width * panel_height *
(NBITS(panel_info.vl_bpix) >> 3));
+#ifdef CONFIG_CMD_BMP
draw_logo();
+#endif
}
lcd_panel_on(&panel_info);
/* DATAPATH is DMA */
cfg |= EXYNOS_WINCON_DATAPATH_DMA;
- /* bpp is 32 */
- cfg |= EXYNOS_WINCON_WSWP_ENABLE;
+ if (pvid->logo_on) /* To get proprietary LOGO */
+ cfg |= EXYNOS_WINCON_WSWP_ENABLE;
+ else /* To get output console on LCD */
+ cfg |= EXYNOS_WINCON_HAWSWP_ENABLE;
/* dma burst is 16 */
cfg |= EXYNOS_WINCON_BURSTLEN_16WORD;
- /* pixel format is unpacked RGB888 */
- cfg |= EXYNOS_WINCON_BPPMODE_24BPP_888;
+ if (pvid->logo_on) /* To get proprietary LOGO */
+ cfg |= EXYNOS_WINCON_BPPMODE_24BPP_888;
+ else /* To get output console on LCD */
+ cfg |= EXYNOS_WINCON_BPPMODE_16BPP_565;
writel(cfg, (unsigned int)&fimd_ctrl->wincon0 +
EXYNOS_WINCON(win_id));
#define IPU_TPM_REG_BASE 0x01060000
#define IPU_DC_TMPL_REG_BASE 0x01080000
#define IPU_ISP_TBPR_REG_BASE 0x010C0000
-#elif defined(CONFIG_MX6Q)
+#elif defined(CONFIG_MX6)
#define IPU_CPMEM_REG_BASE 0x00100000
#define IPU_LUT_REG_BASE 0x00120000
#define IPU_SRM_REG_BASE 0x00140000
--- /dev/null
+/*
+ * ld9040 AMOLED LCD panel driver.
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ * Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <spi.h>
+
+static const unsigned char SEQ_SWRESET[] = {
+ 0x01,
+};
+
+static const unsigned char SEQ_USER_SETTING[] = {
+ 0xF0, 0x5A, 0x5A
+};
+
+static const unsigned char SEQ_ELVSS_ON[] = {
+ 0xB1, 0x0D, 0x00, 0x16,
+};
+
+static const unsigned char SEQ_TEMP_SWIRE[] = {
+ 0xB2, 0x06, 0x06, 0x06, 0x06,
+};
+
+static const unsigned char SEQ_GTCON[] = {
+ 0xF7, 0x09, 0x00, 0x00,
+};
+
+static const unsigned char SEQ_PANEL_CONDITION[] = {
+ 0xF8, 0x05, 0x65, 0x96, 0x71, 0x7D, 0x19, 0x3B,
+ 0x0D, 0x19, 0x7E, 0x0D, 0xE2, 0x00, 0x00, 0x7E,
+ 0x7D, 0x07, 0x07, 0x20, 0x20, 0x20, 0x02, 0x02,
+};
+
+static const unsigned char SEQ_GAMMA_SET1[] = {
+ 0xF9, 0x00, 0xA7, 0xB4, 0xAE, 0xBF, 0x00, 0x91,
+ 0x00, 0xB2, 0xB4, 0xAA, 0xBB, 0x00, 0xAC, 0x00,
+ 0xB3, 0xB1, 0xAA, 0xBC, 0x00, 0xB3,
+};
+
+static const unsigned char SEQ_GAMMA_CTRL[] = {
+ 0xFB, 0x02, 0x5A,
+};
+
+static const unsigned char SEQ_APON[] = {
+ 0xF3, 0x00, 0x00, 0x00, 0x0A, 0x02,
+};
+
+static const unsigned char SEQ_DISPCTL[] = {
+ 0xF2, 0x02, 0x08, 0x08, 0x10, 0x10,
+};
+
+static const unsigned char SEQ_MANPWR[] = {
+ 0xB0, 0x04,
+};
+
+static const unsigned char SEQ_PWR_CTRL[] = {
+ 0xF4, 0x0A, 0x87, 0x25, 0x6A, 0x44, 0x02, 0x88,
+};
+
+static const unsigned char SEQ_SLPOUT[] = {
+ 0x11,
+};
+
+static const unsigned char SEQ_SLPIN[] = {
+ 0x10,
+};
+
+static const unsigned char SEQ_DISPON[] = {
+ 0x29,
+};
+
+static const unsigned char SEQ_DISPOFF[] = {
+ 0x28,
+};
+
+static void ld9040_spi_write(const unsigned char *wbuf, unsigned int size_cmd)
+{
+ int i = 0;
+
+ /*
+ * Data are transmitted in 9-bit words:
+ * the first bit is command/parameter, the other are the value.
+ * The value's LSB is shifted to MSB position, to be sent as 9th bit
+ */
+
+ unsigned int data_out = 0, data_in = 0;
+ for (i = 0; i < size_cmd; i++) {
+ data_out = wbuf[i] >> 1;
+ if (i != 0)
+ data_out += 0x0080;
+ if (wbuf[i] & 0x01)
+ data_out += 0x8000;
+ spi_xfer(NULL, 9, &data_out, &data_in, SPI_XFER_BEGIN);
+ }
+}
+
+void ld9040_cfg_ldo(void)
+{
+ udelay(10);
+
+ ld9040_spi_write(SEQ_USER_SETTING,
+ ARRAY_SIZE(SEQ_USER_SETTING));
+ ld9040_spi_write(SEQ_PANEL_CONDITION,
+ ARRAY_SIZE(SEQ_PANEL_CONDITION));
+ ld9040_spi_write(SEQ_DISPCTL, ARRAY_SIZE(SEQ_DISPCTL));
+ ld9040_spi_write(SEQ_MANPWR, ARRAY_SIZE(SEQ_MANPWR));
+ ld9040_spi_write(SEQ_PWR_CTRL, ARRAY_SIZE(SEQ_PWR_CTRL));
+ ld9040_spi_write(SEQ_ELVSS_ON, ARRAY_SIZE(SEQ_ELVSS_ON));
+ ld9040_spi_write(SEQ_GTCON, ARRAY_SIZE(SEQ_GTCON));
+ ld9040_spi_write(SEQ_GAMMA_SET1, ARRAY_SIZE(SEQ_GAMMA_SET1));
+ ld9040_spi_write(SEQ_GAMMA_CTRL, ARRAY_SIZE(SEQ_GAMMA_CTRL));
+ ld9040_spi_write(SEQ_SLPOUT, ARRAY_SIZE(SEQ_SLPOUT));
+
+ udelay(120);
+}
+
+void ld9040_enable_ldo(unsigned int onoff)
+{
+ if (onoff)
+ ld9040_spi_write(SEQ_DISPON, ARRAY_SIZE(SEQ_DISPON));
+ else
+ ld9040_spi_write(SEQ_DISPOFF, ARRAY_SIZE(SEQ_DISPOFF));
+}
--- /dev/null
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <lcd.h>
+
+#include <asm/system.h>
+#include <asm/gpio.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/funcmux.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/pwm.h>
+#include <asm/arch/display.h>
+#include <asm/arch-tegra/timer.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* These are the stages we go throuh in enabling the LCD */
+enum stage_t {
+ STAGE_START,
+ STAGE_PANEL_VDD,
+ STAGE_LVDS,
+ STAGE_BACKLIGHT_VDD,
+ STAGE_PWM,
+ STAGE_BACKLIGHT_EN,
+ STAGE_DONE,
+};
+
+static enum stage_t stage; /* Current stage we are at */
+static unsigned long timer_next; /* Time we can move onto next stage */
+
+/* Our LCD config, set up in handle_stage() */
+static struct fdt_panel_config config;
+struct fdt_disp_config *disp_config; /* Display controller config */
+
+enum {
+ /* Maximum LCD size we support */
+ LCD_MAX_WIDTH = 1366,
+ LCD_MAX_HEIGHT = 768,
+ LCD_MAX_LOG2_BPP = 4, /* 2^4 = 16 bpp */
+};
+
+int lcd_line_length;
+int lcd_color_fg;
+int lcd_color_bg;
+
+void *lcd_base; /* Start of framebuffer memory */
+void *lcd_console_address; /* Start of console buffer */
+
+short console_col;
+short console_row;
+
+vidinfo_t panel_info = {
+ /* Insert a value here so that we don't end up in the BSS */
+ .vl_col = -1,
+};
+
+char lcd_cursor_enabled;
+
+ushort lcd_cursor_width;
+ushort lcd_cursor_height;
+
+#ifndef CONFIG_OF_CONTROL
+#error "You must enable CONFIG_OF_CONTROL to get Tegra LCD support"
+#endif
+
+void lcd_cursor_size(ushort width, ushort height)
+{
+ lcd_cursor_width = width;
+ lcd_cursor_height = height;
+}
+
+void lcd_toggle_cursor(void)
+{
+ ushort x, y;
+ uchar *dest;
+ ushort row;
+
+ x = console_col * lcd_cursor_width;
+ y = console_row * lcd_cursor_height;
+ dest = (uchar *)(lcd_base + y * lcd_line_length + x * (1 << LCD_BPP) /
+ 8);
+
+ for (row = 0; row < lcd_cursor_height; ++row, dest += lcd_line_length) {
+ ushort *d = (ushort *)dest;
+ ushort color;
+ int i;
+
+ for (i = 0; i < lcd_cursor_width; ++i) {
+ color = *d;
+ color ^= lcd_color_fg;
+ *d = color;
+ ++d;
+ }
+ }
+}
+
+void lcd_cursor_on(void)
+{
+ lcd_cursor_enabled = 1;
+ lcd_toggle_cursor();
+}
+void lcd_cursor_off(void)
+{
+ lcd_cursor_enabled = 0;
+ lcd_toggle_cursor();
+}
+
+char lcd_is_cursor_enabled(void)
+{
+ return lcd_cursor_enabled;
+}
+
+static void update_panel_size(struct fdt_disp_config *config)
+{
+ panel_info.vl_col = config->width;
+ panel_info.vl_row = config->height;
+ panel_info.vl_bpix = config->log2_bpp;
+}
+
+/*
+ * Main init function called by lcd driver.
+ * Inits and then prints test pattern if required.
+ */
+
+void lcd_ctrl_init(void *lcdbase)
+{
+ int line_length, size;
+ int type = DCACHE_OFF;
+
+ assert(disp_config);
+
+ lcd_base = (void *)disp_config->frame_buffer;
+
+ /* Make sure that we can acommodate the selected LCD */
+ assert(disp_config->width <= LCD_MAX_WIDTH);
+ assert(disp_config->height <= LCD_MAX_HEIGHT);
+ assert(disp_config->log2_bpp <= LCD_MAX_LOG2_BPP);
+ if (disp_config->width <= LCD_MAX_WIDTH
+ && disp_config->height <= LCD_MAX_HEIGHT
+ && disp_config->log2_bpp <= LCD_MAX_LOG2_BPP)
+ update_panel_size(disp_config);
+ size = lcd_get_size(&line_length);
+
+ /* Set up the LCD caching as requested */
+ if (config.cache_type & FDT_LCD_CACHE_WRITE_THROUGH)
+ type = DCACHE_WRITETHROUGH;
+ else if (config.cache_type & FDT_LCD_CACHE_WRITE_BACK)
+ type = DCACHE_WRITEBACK;
+ mmu_set_region_dcache_behaviour(disp_config->frame_buffer, size, type);
+
+ /* Enable flushing after LCD writes if requested */
+ lcd_set_flush_dcache(config.cache_type & FDT_LCD_CACHE_FLUSH);
+
+ debug("LCD frame buffer at %p\n", lcd_base);
+}
+
+ulong calc_fbsize(void)
+{
+ return (panel_info.vl_col * panel_info.vl_row *
+ NBITS(panel_info.vl_bpix)) / 8;
+}
+
+void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
+{
+}
+
+void tegra_lcd_early_init(const void *blob)
+{
+ /*
+ * Go with the maximum size for now. We will fix this up after
+ * relocation. These values are only used for memory alocation.
+ */
+ panel_info.vl_col = LCD_MAX_WIDTH;
+ panel_info.vl_row = LCD_MAX_HEIGHT;
+ panel_info.vl_bpix = LCD_MAX_LOG2_BPP;
+}
+
+/**
+ * Decode the panel information from the fdt.
+ *
+ * @param blob fdt blob
+ * @param config structure to store fdt config into
+ * @return 0 if ok, -ve on error
+ */
+static int fdt_decode_lcd(const void *blob, struct fdt_panel_config *config)
+{
+ int display_node;
+
+ disp_config = tegra_display_get_config();
+ if (!disp_config) {
+ debug("%s: Display controller is not configured\n", __func__);
+ return -1;
+ }
+ display_node = disp_config->panel_node;
+ if (display_node < 0) {
+ debug("%s: No panel configuration available\n", __func__);
+ return -1;
+ }
+
+ config->pwm_channel = pwm_request(blob, display_node, "nvidia,pwm");
+ if (config->pwm_channel < 0) {
+ debug("%s: Unable to request PWM channel\n", __func__);
+ return -1;
+ }
+
+ config->cache_type = fdtdec_get_int(blob, display_node,
+ "nvidia,cache-type",
+ FDT_LCD_CACHE_WRITE_BACK_FLUSH);
+
+ /* These GPIOs are all optional */
+ fdtdec_decode_gpio(blob, display_node, "nvidia,backlight-enable-gpios",
+ &config->backlight_en);
+ fdtdec_decode_gpio(blob, display_node, "nvidia,lvds-shutdown-gpios",
+ &config->lvds_shutdown);
+ fdtdec_decode_gpio(blob, display_node, "nvidia,backlight-vdd-gpios",
+ &config->backlight_vdd);
+ fdtdec_decode_gpio(blob, display_node, "nvidia,panel-vdd-gpios",
+ &config->panel_vdd);
+
+ return fdtdec_get_int_array(blob, display_node, "nvidia,panel-timings",
+ config->panel_timings, FDT_LCD_TIMINGS);
+}
+
+/**
+ * Handle the next stage of device init
+ */
+static int handle_stage(const void *blob)
+{
+ debug("%s: stage %d\n", __func__, stage);
+
+ /* do the things for this stage */
+ switch (stage) {
+ case STAGE_START:
+ /* Initialize the Tegra display controller */
+ if (tegra_display_probe(gd->fdt_blob, (void *)gd->fb_base)) {
+ printf("%s: Failed to probe display driver\n",
+ __func__);
+ return -1;
+ }
+
+ /* get panel details */
+ if (fdt_decode_lcd(blob, &config)) {
+ printf("No valid LCD information in device tree\n");
+ return -1;
+ }
+
+ /*
+ * It is possible that the FDT has requested that the LCD be
+ * disabled. We currently don't support this. It would require
+ * changes to U-Boot LCD subsystem to have LCD support
+ * compiled in but not used. An easier option might be to
+ * still have a frame buffer, but leave the backlight off and
+ * remove all mention of lcd in the stdout environment
+ * variable.
+ */
+
+ funcmux_select(PERIPH_ID_DISP1, FUNCMUX_DEFAULT);
+
+ fdtdec_setup_gpio(&config.panel_vdd);
+ fdtdec_setup_gpio(&config.lvds_shutdown);
+ fdtdec_setup_gpio(&config.backlight_vdd);
+ fdtdec_setup_gpio(&config.backlight_en);
+
+ /*
+ * TODO: If fdt includes output flag we can omit this code
+ * since fdtdec_setup_gpio will do it for us.
+ */
+ if (fdt_gpio_isvalid(&config.panel_vdd))
+ gpio_direction_output(config.panel_vdd.gpio, 0);
+ if (fdt_gpio_isvalid(&config.lvds_shutdown))
+ gpio_direction_output(config.lvds_shutdown.gpio, 0);
+ if (fdt_gpio_isvalid(&config.backlight_vdd))
+ gpio_direction_output(config.backlight_vdd.gpio, 0);
+ if (fdt_gpio_isvalid(&config.backlight_en))
+ gpio_direction_output(config.backlight_en.gpio, 0);
+ break;
+ case STAGE_PANEL_VDD:
+ if (fdt_gpio_isvalid(&config.panel_vdd))
+ gpio_direction_output(config.panel_vdd.gpio, 1);
+ break;
+ case STAGE_LVDS:
+ if (fdt_gpio_isvalid(&config.lvds_shutdown))
+ gpio_set_value(config.lvds_shutdown.gpio, 1);
+ break;
+ case STAGE_BACKLIGHT_VDD:
+ if (fdt_gpio_isvalid(&config.backlight_vdd))
+ gpio_set_value(config.backlight_vdd.gpio, 1);
+ break;
+ case STAGE_PWM:
+ /* Enable PWM at 15/16 high, 32768 Hz with divider 1 */
+ pinmux_set_func(PINGRP_GPU, PMUX_FUNC_PWM);
+ pinmux_tristate_disable(PINGRP_GPU);
+
+ pwm_enable(config.pwm_channel, 32768, 0xdf, 1);
+ break;
+ case STAGE_BACKLIGHT_EN:
+ if (fdt_gpio_isvalid(&config.backlight_en))
+ gpio_set_value(config.backlight_en.gpio, 1);
+ break;
+ case STAGE_DONE:
+ break;
+ }
+
+ /* set up timer for next stage */
+ timer_next = timer_get_us();
+ if (stage < FDT_LCD_TIMINGS)
+ timer_next += config.panel_timings[stage] * 1000;
+
+ /* move to next stage */
+ stage++;
+ return 0;
+}
+
+int tegra_lcd_check_next_stage(const void *blob, int wait)
+{
+ if (stage == STAGE_DONE)
+ return 0;
+
+ do {
+ /* wait if we need to */
+ debug("%s: stage %d\n", __func__, stage);
+ if (stage != STAGE_START) {
+ int delay = timer_next - timer_get_us();
+
+ if (delay > 0) {
+ if (wait)
+ udelay(delay);
+ else
+ return 0;
+ }
+ }
+
+ if (handle_stage(blob))
+ return -1;
+ } while (wait && stage != STAGE_DONE);
+ if (stage == STAGE_DONE)
+ debug("%s: LCD init complete\n", __func__);
+
+ return 0;
+}
+
+void lcd_enable(void)
+{
+ /*
+ * Backlight and power init will be done separately in
+ * tegra_lcd_check_next_stage(), which should be called in
+ * board_late_init().
+ *
+ * U-Boot code supports only colour depth, selected at compile time.
+ * The device tree setting should match this. Otherwise the display
+ * will not look right, and U-Boot may crash.
+ */
+ if (disp_config->log2_bpp != LCD_BPP) {
+ printf("%s: Error: LCD depth configured in FDT (%d = %dbpp)"
+ " must match setting of LCD_BPP (%d)\n", __func__,
+ disp_config->log2_bpp, disp_config->bpp, LCD_BPP);
+ }
+}
COBJS-$(CONFIG_AT91SAM9_WATCHDOG) += at91sam9_wdt.o
COBJS-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o
+ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6))
+COBJS-y += imx_watchdog.o
+endif
COBJS-$(CONFIG_TNETV107X_WATCHDOG) += tnetv107x_wdt.o
+COBJS-$(CONFIG_S5P) += s5p_wdt.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
--- /dev/null
+/*
+ * watchdog.c - driver for i.mx on-chip watchdog
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <watchdog.h>
+#include <asm/arch/imx-regs.h>
+
+struct watchdog_regs {
+ u16 wcr; /* Control */
+ u16 wsr; /* Service */
+ u16 wrsr; /* Reset Status */
+};
+
+#define WCR_WDZST 0x01
+#define WCR_WDBG 0x02
+#define WCR_WDE 0x04 /* WDOG enable */
+#define WCR_WDT 0x08
+#define WCR_WDW 0x80
+#define SET_WCR_WT(x) (x << 8)
+
+#ifdef CONFIG_IMX_WATCHDOG
+void hw_watchdog_reset(void)
+{
+ struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
+
+ writew(0x5555, &wdog->wsr);
+ writew(0xaaaa, &wdog->wsr);
+}
+
+void hw_watchdog_init(void)
+{
+ struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
+ u16 timeout;
+
+ /*
+ * The timer watchdog can be set between
+ * 0.5 and 128 Seconds. If not defined
+ * in configuration file, sets 128 Seconds
+ */
+#ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS
+#define CONFIG_WATCHDOG_TIMEOUT_MSECS 128000
+#endif
+ timeout = (CONFIG_WATCHDOG_TIMEOUT_MSECS / 500) - 1;
+ writew(WCR_WDZST | WCR_WDBG | WCR_WDE | WCR_WDT |
+ WCR_WDW | SET_WCR_WT(timeout), &wdog->wcr);
+ hw_watchdog_reset();
+}
+#endif
+
+void reset_cpu(ulong addr)
+{
+ struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
+
+ writew(WCR_WDE, &wdog->wcr);
+ writew(0x5555, &wdog->wsr);
+ writew(0xaaaa, &wdog->wsr); /* load minimum 1/2 second timeout */
+ while (1) {
+ /*
+ * spin for .5 seconds before reset
+ */
+ }
+}
--- /dev/null
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/watchdog.h>
+
+#define PRESCALER_VAL 255
+
+void wdt_stop(void)
+{
+ struct s5p_watchdog *wdt =
+ (struct s5p_watchdog *)samsung_get_base_watchdog();
+ unsigned int wtcon;
+
+ wtcon = readl(&wdt->wtcon);
+ wtcon &= ~(WTCON_EN | WTCON_INT | WTCON_RESET);
+
+ writel(wtcon, &wdt->wtcon);
+}
+
+void wdt_start(unsigned int timeout)
+{
+ struct s5p_watchdog *wdt =
+ (struct s5p_watchdog *)samsung_get_base_watchdog();
+ unsigned int wtcon;
+
+ wdt_stop();
+
+ wtcon = readl(&wdt->wtcon);
+ wtcon |= (WTCON_EN | WTCON_CLK(WTCON_CLK_128));
+ wtcon &= ~WTCON_INT;
+ wtcon |= WTCON_RESET;
+ wtcon |= WTCON_PRESCALER(PRESCALER_VAL);
+
+ writel(timeout, &wdt->wtdat);
+ writel(timeout, &wdt->wtcnt);
+ writel(wtcon, &wdt->wtcon);
+}
extern char console_buffer[];
/* arch/$(ARCH)/lib/board.c */
-void board_init_f (ulong) __attribute__ ((noreturn));
+void board_init_f(ulong);
void board_init_r (gd_t *, ulong) __attribute__ ((noreturn));
int checkboard (void);
int checkflash (void);
extern u8 _binary_dt_dtb_start[]; /* embedded device tree blob */
int set_cpu_clk_info(void);
+/**
+ * Show the DRAM size in a board-specific way
+ *
+ * This is used by boards to display DRAM information in their own way.
+ *
+ * @param size Size of DRAM (which should be displayed along with other info)
+ */
+void board_show_dram(ulong size);
+
/* common/flash.c */
void flash_perror (int);
#define CONFIG_CMD_LICENSE /* console license display */
#define CONFIG_CMD_LOADB /* loadb */
#define CONFIG_CMD_LOADS /* loads */
+#define CONFIG_CMD_MEMINFO /* meminfo */
#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */
#define CONFIG_CMD_MFSL /* FSL support for Microblaze */
#define CONFIG_CMD_MII /* MII support */
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* where to load what we get from TFTP */
-#define CONFIG_SYS_TFTP_LOADADDR CONFIG_SYS_LOAD_ADDR
#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
#define CONFIG_SYS_DRAM_TEST 1
#undef CONFIG_LOADS_ECHO
#define CONFIG_SYS_LOADS_BAUD_CHANGE
-/*
- * Set default load address for tftp network downloads
- */
-#define CONFIG_SYS_TFTP_LOADADDR 0x01000000
-
/*
* Turn off the watchdog timer
*/
#define CONFIG_IPADDR 10.0.4.111
#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
-#define CONFIG_SYS_TFTP_LOADADDR 0x00100000
/*
* For booting Linux, the board info and command line data
#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_NAND_AM33XX_BCH
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
+ CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_PAGE_SIZE 2048
+#define CONFIG_SYS_NAND_OOBSIZE 64
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
+ 10, 11, 12, 13, 14, 15, 16, 17, \
+ 18, 19, 20, 21, 22, 23, 24, 25, \
+ 26, 27, 28, 29, 30, 31, 32, 33, \
+ 34, 35, 36, 37, 38, 39, 40, 41, \
+ 42, 43, 44, 45, 46, 47, 48, 49, \
+ 50, 51, 52, 53, 54, 55, 56, 57, }
+
+#define CONFIG_SYS_NAND_ECCSIZE 512
+#define CONFIG_SYS_NAND_ECCBYTES 14
+
+#define CONFIG_SYS_NAND_ECCSTEPS 4
+#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \
+ CONFIG_SYS_NAND_ECCSTEPS)
+
+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
+
/*
* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
* 64 bytes before this address should be set aside for u-boot.img's
#define CONFIG_NET_MULTI
#define CONFIG_PHY_GIGE
#define CONFIG_PHYLIB
+#define CONFIG_PHY_ADDR 0
#define CONFIG_PHY_SMSC
+#define CONFIG_NAND
+/* NAND support */
+#ifdef CONFIG_NAND
+#define CONFIG_CMD_NAND
+#define CONFIG_NAND_OMAP_GPMC
+#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
+#define CONFIG_SYS_NAND_BASE (0x08000000) /* physical address */
+ /* to access nand at */
+ /* CS0 */
+#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND
+ devices */
+#undef CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */
+#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
+#endif
+
#endif /* ! __CONFIG_AM335X_EVM_H */
#define CONFIG_CMD_NAND
#define CONFIG_CMD_SF
#define CONFIG_CMD_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_USB
+
+/*
+ * define CONFIG_USB_EHCI to enable USB Hi-Speed (aka 2.0)
+ * NB: in this case, USB 1.1 devices won't be recognized.
+ */
+
/* SDRAM */
#define CONFIG_NR_DRAM_BANKS 1
/* MMC */
#ifdef CONFIG_CMD_MMC
#define CONFIG_MMC
-#define CONFIG_CMD_FAT
#define CONFIG_GENERIC_MMC
#define CONFIG_GENERIC_ATMEL_MCI
+#endif
+
+/* FAT */
+#ifdef CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION
#endif
#define CONFIG_NET_RETRY_COUNT 20
#define CONFIG_MACB_SEARCH_PHY
+/* USB */
+#ifdef CONFIG_CMD_USB
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_ATMEL
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2
+#else
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9x5"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
+#endif
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_STORAGE
+#endif
+
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
#define CONFIG_BOOTCOMMAND "sf probe 0; " \
"sf read 0x22000000 0x100000 0x300000; " \
"bootm 0x22000000"
+#elif defined(CONFIG_SYS_USE_DATAFLASH)
+/* bootstrap + u-boot + env + linux in data flash */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET 0x4200
+#define CONFIG_ENV_SIZE 0x4200
+#define CONFIG_ENV_SECT_SIZE 0x210
+#define CONFIG_ENV_SPI_MAX_HZ 30000000
+#define CONFIG_BOOTCOMMAND "sf probe 0; " \
+ "sf read 0x22000000 0x84000 0x294000; " \
+ "bootm 0x22000000"
#else /* CONFIG_SYS_USE_MMC */
/* bootstrap + u-boot + env + linux in mmc */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_DOS_PARTITION
/* USB */
-#define CONFIG_MUSB_UDC
#define CONFIG_USB_OMAP3
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_OMAP
+#define CONFIG_USB_ULPI
+#define CONFIG_USB_ULPI_VIEWPORT_OMAP
+#define CONFIG_USB_STORAGE
+#define CONFIG_MUSB_UDC
#define CONFIG_TWL4030_USB
+#define CONFIG_CMD_USB
/* USB device configuration */
#define CONFIG_USB_DEVICE
/* Environment information */
#define CONFIG_BOOTDELAY 10
+#define CONFIG_ZERO_BOOTDELAY_CHECK
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x82000000\0" \
*/
#define CONFIG_NR_DRAM_BANKS 1 /* CS1 is never populated */
#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
/*-----------------------------------------------------------------------
* FLASH and environment organization
#define CONFIG_CMD_GPIO
#define CONFIG_CMD_IMI
#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_IO
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_ITEST
#define CONFIG_CMD_LOADB
*/
#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
/*-----------------------------------------------------------------------
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM_BASE0
#define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM_SIZE0
-/* If M5282 port is fully implemented the monitor base will be behind
- * the vector table. */
-#if (CONFIG_SYS_TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE)
-#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
-#else
-#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */
-#endif
-
#define CONFIG_SYS_MONITOR_LEN 0x20000
#define CONFIG_SYS_MALLOC_LEN (256 << 10)
#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
-#define CONFIG_SYS_TFTP_LOADADDR 0x00100000 /* default load address for network file downloads */
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
--- /dev/null
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Configuration settings for the SAMSUNG EXYNOS5250 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_SAMSUNG /* in a SAMSUNG core */
+#define CONFIG_S5P /* S5P Family */
+#define CONFIG_EXYNOS5 /* which is in a Exynos5 Family */
+#define CONFIG_SMDK5250 /* which is in a SMDK5250 */
+
+#include <asm/arch/cpu.h> /* get chip and board defs */
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* Enable fdt support for Exynos5250 */
+#define CONFIG_ARCH_DEVICE_TREE exynos5250
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+
+/* Keep L2 Cache Disabled */
+#define CONFIG_SYS_DCACHE_OFF
+
+#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CONFIG_SYS_TEXT_BASE 0x43E00000
+
+/* input clock of PLL: SMDK5250 has 24MHz input clock */
+#define CONFIG_SYS_CLK_FREQ 24000000
+
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMDLINE_EDITING
+
+/* MACH_TYPE_SMDK5250 macro will be removed once added to mach-types */
+#define MACH_TYPE_SMDK5250 3774
+#define CONFIG_MACH_TYPE MACH_TYPE_SMDK5250
+
+/* Power Down Modes */
+#define S5P_CHECK_SLEEP 0x00000BAD
+#define S5P_CHECK_DIDLE 0xBAD00000
+#define S5P_CHECK_LPA 0xABAD0000
+
+/* Offset for inform registers */
+#define INFORM0_OFFSET 0x800
+#define INFORM1_OFFSET 0x804
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20))
+
+/* select serial console configuration */
+#define CONFIG_SERIAL3 /* use SERIAL 3 */
+#define CONFIG_BAUDRATE 115200
+#define EXYNOS5_DEFAULT_UART_OFFSET 0x010000
+
+/* Console configuration */
+#define CONFIG_CONSOLE_MUX
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define EXYNOS_DEVICE_SETTINGS \
+ "stdin=serial\0" \
+ "stdout=serial,lcd\0" \
+ "stderr=serial,lcd\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ EXYNOS_DEVICE_SETTINGS
+
+#define TZPC_BASE_OFFSET 0x10000
+
+/* SD/MMC configuration */
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC
+#define CONFIG_SDHCI
+#define CONFIG_S5P_SDHCI
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* PWM */
+#define CONFIG_PWM
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Command definition*/
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_NET
+
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+/* USB */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_EXYNOS
+#define CONFIG_USB_STORAGE
+
+/* MMC SPL */
+#define CONFIG_SPL
+#define COPY_BL2_FNPTR_ADDR 0x02020030
+
+/* specific .lds file */
+#define CONFIG_SPL_LDSCRIPT "board/samsung/smdk5250/smdk5250-uboot-spl.lds"
+#define CONFIG_SPL_TEXT_BASE 0x02023400
+#define CONFIG_SPL_MAX_SIZE (14 * 1024)
+
+#define CONFIG_BOOTCOMMAND "mmc read 40007000 451 2000; bootm 40007000"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT "SMDK5250 # "
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
+
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_RD_LVL
+
+#define CONFIG_NR_DRAM_BANKS 8
+#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
+#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
+#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
+#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
+
+#define CONFIG_SYS_MONITOR_BASE 0x00000000
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+#undef CONFIG_CMD_IMLS
+#define CONFIG_IDENT_STRING " for SMDK5250"
+
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#define CONFIG_SECURE_BL1_ONLY
+
+/* Secure FW size configuration */
+#ifdef CONFIG_SECURE_BL1_ONLY
+#define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */
+#else
+#define CONFIG_SEC_FW_SIZE 0
+#endif
+
+/* Configuration of BL1, BL2, ENV Blocks on mmc */
+#define CONFIG_RES_BLOCK_SIZE (512)
+#define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/
+#define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */
+#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
+
+#define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
+#define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
+#define CONFIG_ENV_OFFSET (CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE)
+
+/* U-boot copy size from boot Media to DRAM.*/
+#define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512)
+#define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512)
+
+#define OM_STAT (0x1f << 1)
+#define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058
+#define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
+
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_IRAM_STACK 0x02050000
+
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000)
+
+/* I2C */
+#define CONFIG_SYS_I2C_INIT_BOARD
+#define CONFIG_HARD_I2C
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C_SPEED 100000 /* 100 Kbps */
+#define CONFIG_DRIVER_S3C24X0_I2C
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_MAX_I2C_NUM 8
+#define CONFIG_SYS_I2C_SLAVE 0x0
+#define CONFIG_I2C_EDID
+
+/* PMIC */
+#define CONFIG_PMIC
+#define CONFIG_PMIC_I2C
+#define CONFIG_PMIC_MAX77686
+
+/* SPI */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_SPI_FLASH
+
+#ifdef CONFIG_SPI_FLASH
+#define CONFIG_EXYNOS_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
+#define CONFIG_SF_DEFAULT_SPEED 50000000
+#define EXYNOS5_SPI_NUM_CONTROLLERS 5
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_MODE SPI_MODE_0
+#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
+#define CONFIG_ENV_SPI_BUS 1
+#define CONFIG_ENV_SPI_MAX_HZ 50000000
+#endif
+
+/* PMIC */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_MAX77686
+
+/* SPI */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_SPI_FLASH
+
+#ifdef CONFIG_SPI_FLASH
+#define CONFIG_EXYNOS_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
+#define CONFIG_SF_DEFAULT_SPEED 50000000
+#define EXYNOS5_SPI_NUM_CONTROLLERS 5
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_MODE SPI_MODE_0
+#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
+#define CONFIG_ENV_SPI_BUS 1
+#define CONFIG_ENV_SPI_MAX_HZ 50000000
+#endif
+
+/* Ethernet Controllor Driver */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_BASE 0x5000000
+#define CONFIG_SMC911X_16_BIT
+#define CONFIG_ENV_SROM_BANK 1
+#endif /*CONFIG_CMD_NET*/
+
+/* Enable PXE Support */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_CMD_PXE
+#define CONFIG_MENU
+#endif
+
+/* Sound */
+#define CONFIG_CMD_SOUND
+#ifdef CONFIG_CMD_SOUND
+#define CONFIG_SOUND
+#define CONFIG_I2S
+#define CONFIG_SOUND_WM8994
+#endif
+
+/* Enable devicetree support */
+#define CONFIG_OF_LIBFDT
+
+/* SHA hashing */
+#define CONFIG_CMD_HASH
+#define CONFIG_HASH_VERIFY
+#define CONFIG_SHA1
+#define CONFIG_SHA256
+
+/* Display */
+#define CONFIG_LCD
+#ifdef CONFIG_LCD
+#define CONFIG_EXYNOS_FB
+#define CONFIG_EXYNOS_DP
+#define LCD_XRES 2560
+#define LCD_YRES 1600
+#define LCD_BPP LCD_COLOR16
+#endif
+
+#endif /* __CONFIG_H */
#define CONFIG_BOOTARGS "root=/dev/ram0 ro console=ttyS0,115200n8"
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_USB_DEV_PULLUP_GPIO 33
+/* USB VBUS GPIO 3 */
+
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+
+#define CONFIG_BOOTDELAY 2
+#define CONFIG_BOOTCOMMAND \
+ "setenv downloaded 0 ; while test $downloaded -eq 0 ; do " \
+ "if bootp ; then setenv downloaded 1 ; fi ; done ; " \
+ "source :script ; " \
+ "bootm ; "
+
+#define CONFIG_USB_GADGET_PXA2XX
+#define CONFIG_USB_ETHER
+#define CONFIG_USB_ETH_SUBSET
+
+#define CONFIG_USBNET_DEV_ADDR "de:ad:be:ef:00:01"
+#define CONFIG_USBNET_HOST_ADDR "de:ad:be:ef:00:02"
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "stdin=serial\0" \
+ "stdout=serial\0" \
+ "stderr=serial\0"
+
#endif /* __CONFIG_H */
#define CONFIG_DOS_PARTITION
#define CONFIG_EFI_PARTITION
+#define CONFIG_FS_EXT4
+#define CONFIG_FS_FAT
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FS_GENERIC
/* NAND support */
#define CONFIG_CMD_NAND
#define CONFIG_TEGRA_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE NV_PA_NAND_BASE
/* Environment in NAND (which is 512M), aligned to start of last sector */
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
+/* define to avoid U-Boot to hang while waiting for TEMT */
+#define CONFIG_SYS_NS16550_BROKEN_TEMT
+
/* select serial console configuration */
#define CONFIG_CONS_INDEX 3
#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
*/
#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 meg */
#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
/*
#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
+#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBDISK_SUPPORT
#define CONFIG_SPL_I2C_SUPPORT
"load=tftpboot ${load_addr_r} ${u-boot}\0" \
"mtdids=" MTDIDS_DEFAULT "\0" \
"mtdparts=" MTDPARTS_DEFAULT "\0" \
- "stderr=serial\0" \
- "stdin=serial\0" \
- "stdout=serial\0" \
""
#endif /* CONFIG_KM_DEF_ENV */
"config_nc_dhcp=setenv autoload_old ${autoload}; " \
"setenv autoload no " \
"&& bootp " \
- "&& setenv ncip ${serverip} " \
+ "&& setenv ncip " \
"&& setenv autoload ${autoload_old}; " \
"setenv autoload_old\0" \
"standard_env=setenv ipaddr; setenv netmask; setenv serverip; " \
"512k(environment)," \
"512k(redundant-environment)," \
"4m(kernel)," \
+ "128k(fdt)," \
+ "8m(ramdisk)," \
"-(filesystem)"
#else
#define CONFIG_ENV_IS_NOWHERE
"if tftp ${update_nand_full_filename} ; then " \
"run update_nand_get_fcb_size ; " \
"nand scrub -y 0x0 ${filesize} ; " \
- "nand write.raw ${loadaddr} 0x0 ${update_nand_fcb} ; " \
+ "nand write.raw ${loadaddr} 0x0 ${fcb_sz} ; " \
"setexpr update_off ${loadaddr} + ${update_nand_fcb} ; " \
"setexpr update_sz ${filesize} - ${update_nand_fcb} ; " \
"nand write ${update_off} ${update_nand_fcb} ${update_sz} ; " \
*/
#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
/*
/*
* Size of malloc() pool
*/
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* 1MiB for malloc() */
+#define CONFIG_SYS_MALLOC_LEN (1024 * 1024 * 4) /* 4MiB for malloc() */
/*
* Other required minimal configurations
/* High Level Configuration Options */
+#define CONFIG_MX25
#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_TEXT_BASE 0x81200000
+#define CONFIG_MXC_GPIO
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define PHYS_SDRAM_1_SIZE (64 * 1024 * 1024)
#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR IMX_RAM_BASE
/* No NOR flash present */
#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
#define CONFIG_ENV_SIZE (8 * 1024)
-#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
/* U-Boot general configuration */
#define CONFIG_SYS_PROMPT "MX25PDK U-Boot > "
/* U-Boot commands */
#include <config_cmd_default.h>
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_BOOTZ
#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
/* Ethernet */
#define CONFIG_FEC_MXC
#define CONFIG_CMD_NET
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_BOOTDELAY 3
+/* ESDHC driver */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CONFIG_SYS_FSL_ESDHC_NUM 1
+
+/* PMIC Configs */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_FSL
+#define CONFIG_PMIC_FSL_MC34704
+#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x54
+
+#define CONFIG_DOS_PARTITION
+
+/* I2C Configs */
+#define CONFIG_CMD_I2C
+#define CONFIG_HARD_I2C
+#define CONFIG_I2C_MXC
+#define CONFIG_SYS_I2C_BASE IMX_I2C_BASE
+#define CONFIG_SYS_I2C_SPEED 100000
+
+/* Ethernet Configs */
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+
+#define CONFIG_BOOTDELAY 1
#define CONFIG_LOADADDR 0x81000000 /* loadaddr env var */
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
*/
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTDELAY 1
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_LOADADDR 0x42000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
"if tftp ${update_nand_full_filename} ; then " \
"run update_nand_get_fcb_size ; " \
"nand scrub -y 0x0 ${filesize} ; " \
- "nand write.raw ${loadaddr} 0x0 ${update_nand_fcb} ; " \
+ "nand write.raw ${loadaddr} 0x0 ${fcb_sz} ; " \
"setexpr update_off ${loadaddr} + ${update_nand_fcb} ; " \
"setexpr update_sz ${filesize} - ${update_nand_fcb} ; " \
"nand write ${update_off} ${update_nand_fcb} ${update_sz} ; " \
"uimage=uImage\0" \
"console_fsl=ttyAM0\0" \
"console_mainline=ttyAMA0\0" \
+ "fdt_file=imx28-evk.dtb\0" \
+ "fdt_addr=0x41000000\0" \
+ "boot_fdt=try\0" \
+ "ip_dyn=yes\0" \
"mmcdev=0\0" \
"mmcpart=2\0" \
- "mmcroot=/dev/mmcblk0p3 rw\0" \
- "mmcrootfstype=ext3 rootwait\0" \
+ "mmcroot=/dev/mmcblk0p3 rw rootwait\0" \
"mmcargs=setenv bootargs console=${console_mainline},${baudrate} " \
- "root=${mmcroot} " \
- "rootfstype=${mmcrootfstype}\0" \
+ "root=${mmcroot}\0" \
"loadbootscript=" \
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"source\0" \
"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
"mmcboot=echo Booting from mmc ...; " \
- "run mmcargs; " \
- "bootm\0" \
+ "run mmcargs; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if run loadfdt; then " \
+ "bootm ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootm; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootm; " \
+ "fi;\0" \
"netargs=setenv bootargs console=${console_mainline},${baudrate} " \
"root=/dev/nfs " \
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
"netboot=echo Booting from net ...; " \
"run netargs; " \
- "dhcp ${uimage}; bootm\0"
+ "if test ${ip_dyn} = yes; then " \
+ "setenv get_cmd dhcp; " \
+ "else " \
+ "setenv get_cmd tftp; " \
+ "fi; " \
+ "${get_cmd} ${uimage}; " \
+ "if test ${boot_fdt} = yes; then " \
+ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+ "bootm ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootm; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi;" \
+ "fi; " \
+ "else " \
+ "bootm; " \
+ "fi;\0"
#define CONFIG_BOOTCOMMAND \
"mmc dev ${mmcdev}; if mmc rescan; then " \
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE
#define CONFIG_HW_WATCHDOG
+#define CONFIG_IMX_WATCHDOG
#define CONFIG_MXC_GPIO
#define CONFIG_HARD_SPI
#define CONFIG_BOARD_LATE_INIT
-#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTDELAY 1
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootargs_base=setenv bootargs console=ttymxc0,115200\0" \
#define CONFIG_POWER
#define CONFIG_POWER_I2C
#define CONFIG_POWER_FSL
+#define CONFIG_PMIC_FSL_MC13892
#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x08
#define CONFIG_RTC_MC13XXX
#include <config_cmd_default.h>
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_BOOTZ
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_NET_RETRY_COUNT 100
#define CONFIG_CMD_DATE
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
#define CONFIG_CMD_MMC
#define CONFIG_DOS_PARTITION
#define CONFIG_EFI_PARTITION
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
-#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTDELAY 1
#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
#define CONFIG_MXC_NAND_HWECC
#define CONFIG_SYS_NAND_LARGEPAGE
+/* EHCI driver */
+#define CONFIG_USB_EHCI
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_EHCI_MXC
+#define CONFIG_MXC_USB_PORT 0
+#define CONFIG_MXC_USB_FLAGS (MXC_EHCI_INTERFACE_DIFF_UNI | \
+ MXC_EHCI_POWER_PINS_ENABLED | \
+ MXC_EHCI_OC_PIN_ACTIVE_LOW)
+#define CONFIG_MXC_USB_PORTSC (MXC_EHCI_UTMI_16BIT | MXC_EHCI_MODE_UTMI)
+
/* mmc driver */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_SYS_DDR_CLKSEL 0
#define CONFIG_SYS_CLKTL_CBCDR 0x59E35145
+#define CONFIG_SYS_MAIN_PWR_ON
#endif
#define CONFIG_SYS_TEXT_BASE 0x97800000
#include <asm/arch/imx-regs.h>
-/*
- * Disabled for now due to build problems under Debian and a significant
- * increase in the final file size: 144260 vs. 109536 Bytes.
- */
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
***********************************************************/
#include <config_cmd_default.h>
-
+#define CONFIG_CMD_BOOTZ
#undef CONFIG_CMD_IMLS
#define CONFIG_CMD_DATE
-#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTDELAY 1
#define CONFIG_ETHPRIME "FEC0"
#define CONFIG_SYS_DDR_CLKSEL 0
#define CONFIG_SYS_CLKTL_CBCDR 0x59E35100
+#define CONFIG_SYS_MAIN_PWR_ON
/*-----------------------------------------------------------------------
* FLASH and environment organization
#define CONFIG_POWER_I2C
#define CONFIG_POWER_FSL
#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 8
+#define CONFIG_PMIC_FSL_MC13892
#define CONFIG_RTC_MC13XXX
/* MMC Configs */
#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
#define CONFIG_MXC_GPIO
#define CONFIG_REVISION_TAG
#define CONFIG_POWER_I2C
#define CONFIG_DIALOG_POWER
#define CONFIG_POWER_FSL
+#define CONFIG_PMIC_FSL_MC13892
#define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48
#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8
/* Command definition */
#include <config_cmd_default.h>
+#define CONFIG_CMD_BOOTZ
#undef CONFIG_CMD_IMLS
-#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTDELAY 1
#define CONFIG_ETHPRIME "FEC0"
-#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */
+#define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */
#define CONFIG_SYS_TEXT_BASE 0x77800000
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
"uimage=uImage\0" \
+ "fdt_file=imx53-qsb.dtb\0" \
+ "fdt_addr=0x71000000\0" \
+ "boot_fdt=try\0" \
+ "ip_dyn=yes\0" \
"mmcdev=0\0" \
"mmcpart=2\0" \
- "mmcroot=/dev/mmcblk0p3 rw\0" \
- "mmcrootfstype=ext3 rootwait\0" \
- "mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \
- "root=${mmcroot} " \
- "rootfstype=${mmcrootfstype}\0" \
+ "mmcroot=/dev/mmcblk0p3 rw rootwait\0" \
+ "mmcargs=setenv bootargs console=ttymxc0,${baudrate} root=${mmcroot}\0" \
"loadbootscript=" \
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"source\0" \
"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \
- "bootm\0" \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if run loadfdt; then " \
+ "bootm ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootm; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootm; " \
+ "fi;\0" \
"netargs=setenv bootargs console=ttymxc0,${baudrate} " \
"root=/dev/nfs " \
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
"netboot=echo Booting from net ...; " \
"run netargs; " \
- "dhcp ${uimage}; bootm\0" \
+ "if test ${ip_dyn} = yes; then " \
+ "setenv get_cmd dhcp; " \
+ "else " \
+ "setenv get_cmd tftp; " \
+ "fi; " \
+ "${get_cmd} ${uimage}; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+ "bootm ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootm; " \
+ "else " \
+ "echo ERROR: Cannot load the DT; " \
+ "exit; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootm; " \
+ "fi;\0"
#define CONFIG_BOOTCOMMAND \
"mmc dev ${mmcdev}; if mmc rescan; then " \
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_SYS_PROMPT "MX53LOCO U-Boot > "
#define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_MX6
#define CONFIG_MX6Q
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#ifndef __MX6QSABRE_COMMON_CONFIG_H
#define __MX6QSABRE_COMMON_CONFIG_H
+#define CONFIG_MX6
#define CONFIG_MX6Q
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_MMC
#define CONFIG_CMD_MMC
/* Command definition */
#include <config_cmd_default.h>
+#define CONFIG_CMD_BOOTZ
#undef CONFIG_CMD_IMLS
-#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTDELAY 1
-#define CONFIG_LOADADDR 0x10800000
+#define CONFIG_LOADADDR 0x12000000
#define CONFIG_SYS_TEXT_BASE 0x17800000
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
"uimage=uImage\0" \
+ "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+ "fdt_addr=0x11000000\0" \
+ "boot_fdt=try\0" \
+ "ip_dyn=yes\0" \
"console=" CONFIG_CONSOLE_DEV "\0" \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
- "mmcdev=0\0" \
+ "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
"mmcpart=1\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
"bootscript=echo Running bootscript from mmc ...; " \
"source\0" \
"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
- "mmcboot=echo Booting from mmc ...; " \
+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+ "mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \
- "bootm\0" \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if run loadfdt; then " \
+ "bootm ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootm; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootm; " \
+ "fi;\0" \
"netargs=setenv bootargs console=${console},${baudrate} " \
"root=/dev/nfs " \
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
"netboot=echo Booting from net ...; " \
"run netargs; " \
- "dhcp ${uimage}; bootm\0" \
+ "if test ${ip_dyn} = yes; then " \
+ "setenv get_cmd dhcp; " \
+ "else " \
+ "setenv get_cmd tftp; " \
+ "fi; " \
+ "${get_cmd} ${uimage}; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+ "bootm ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootm; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootm; " \
+ "fi;\0"
#define CONFIG_BOOTCOMMAND \
"mmc dev ${mmcdev};" \
#if defined(CONFIG_ENV_IS_IN_MMC)
#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
-#define CONFIG_SYS_MMC_ENV_DEV 0
#endif
#define CONFIG_OF_LIBFDT
#define CONFIG_MACH_TYPE 3529
#define CONFIG_MXC_UART_BASE UART4_BASE
#define CONFIG_CONSOLE_DEV "ttymxc3"
+#define CONFIG_DEFAULT_FDT_FILE "imx6q-sabreauto.dtb"
#define CONFIG_MMCROOT "/dev/mmcblk0p2"
#define PHYS_SDRAM_SIZE (2u * 1024 * 1024 * 1024)
#include "mx6qsabre_common.h"
+#define CONFIG_SYS_FSL_USDHC_NUM 2
+#if defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#endif
+
#endif /* __MX6QSABREAUTO_CONFIG_H */
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_MX6
#define CONFIG_MX6Q
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#undef CONFIG_CMD_IMLS
-#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTDELAY 1
#define CONFIG_PREBOOT ""
-#define CONFIG_LOADADDR 0x10800000
+#define CONFIG_LOADADDR 0x12000000
#define CONFIG_SYS_TEXT_BASE 0x17800000
#define CONFIG_EXTRA_ENV_SETTINGS \
- "script=boot.scr\0" \
- "uimage=uImage\0" \
+ "script=boot.scr\0" \
+ "uimage=uImage\0" \
"console=ttymxc1\0" \
- "fdt_high=0xffffffff\0" \
+ "fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
- "mmcdev=0\0" \
- "mmcpart=2\0" \
- "mmcroot=/dev/mmcblk0p3 rootwait rw\0" \
- "mmcargs=setenv bootargs console=${console},${baudrate} " \
- "root=${mmcroot}\0" \
- "loadbootscript=" \
- "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
- "bootscript=echo Running bootscript from mmc ...; " \
- "source\0" \
- "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
- "mmcboot=echo Booting from mmc ...; " \
- "run mmcargs; " \
- "bootm\0" \
- "netargs=setenv bootargs console=${console},${baudrate} " \
- "root=/dev/nfs " \
- "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
- "netboot=echo Booting from net ...; " \
- "run netargs; " \
- "dhcp ${uimage}; bootm\0" \
+ "fdt_file=imx6q-sabrelite.dtb\0" \
+ "fdt_addr=0x11000000\0" \
+ "boot_fdt=try\0" \
+ "ip_dyn=yes\0" \
+ "mmcdev=0\0" \
+ "mmcpart=2\0" \
+ "mmcroot=/dev/mmcblk0p3 rootwait rw\0" \
+ "mmcargs=setenv bootargs console=${console},${baudrate} " \
+ "root=${mmcroot}\0" \
+ "loadbootscript=" \
+ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source\0" \
+ "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if run loadfdt; then " \
+ "bootm ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootm; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootm; " \
+ "fi;\0" \
+ "netargs=setenv bootargs console=${console},${baudrate} " \
+ "root=/dev/nfs " \
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+ "netboot=echo Booting from net ...; " \
+ "run netargs; " \
+ "if test ${ip_dyn} = yes; then " \
+ "setenv get_cmd dhcp; " \
+ "else " \
+ "setenv get_cmd tftp; " \
+ "fi; " \
+ "${get_cmd} ${uimage}; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+ "bootm ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootm; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootm; " \
+ "fi;\0"
#define CONFIG_BOOTCOMMAND \
- "mmc dev ${mmcdev};" \
- "mmc dev ${mmcdev}; if mmc rescan; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loaduimage; then " \
- "run mmcboot; " \
- "else run netboot; " \
- "fi; " \
- "fi; " \
- "else run netboot; fi"
+ "mmc dev ${mmcdev};" \
+ "mmc dev ${mmcdev}; if mmc rescan; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loaduimage; then " \
+ "run mmcboot; " \
+ "else run netboot; " \
+ "fi; " \
+ "fi; " \
+ "else run netboot; fi"
#define CONFIG_ARP_TIMEOUT 200UL
#define CONFIG_MXC_UART_BASE UART1_BASE
#define CONFIG_CONSOLE_DEV "ttymxc0"
#define CONFIG_MMCROOT "/dev/mmcblk1p2"
+#define CONFIG_DEFAULT_FDT_FILE "imx6q-sabresd.dtb"
#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
#include "mx6qsabre_common.h"
+#define CONFIG_SYS_FSL_USDHC_NUM 3
+#if defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_SYS_MMC_ENV_DEV 1 /* SDHC3 */
+#define CONFIG_SYS_MMC_ENV_PART 1 /* Boot partition 1 */
+#endif
+
#endif /* __MX6QSABRESD_CONFIG_H */
"else run userbutton_nonxm; fi;\0" \
"userbutton_xm=gpio input 4;\0" \
"userbutton_nonxm=gpio input 7;\0"
-/* "run userbutton" will return 1 (false) if is pressed and 0 (false) if not */
+/* "run userbutton" will return 1 (false) if pressed and 0 (true) if not */
#define CONFIG_BOOTCOMMAND \
"mmc dev ${mmcdev}; if mmc rescan; then " \
"if run userbutton; then " \
*/
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
#define CONFIG_ENV_IS_NOWHERE 1
*/
#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
#define CONFIG_SYS_TEXT_BASE 0x80008000
*/
#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 meg */
#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
/*--------------------------------------------------------------------------*/
*/
#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
/*-----------------------------------------------------------------------
*/
#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
/*-----------------------------------------------------------------------
#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */
#define CONFIG_PALMLD 1 /* Palm LifeDrive board */
+/* we will never enable dcache, because we have to setup MMU first */
+#define CONFIG_SYS_DCACHE_OFF
+
/*
* Environment settings
*/
#define CONFIG_CPU_PXA25X 1 /* Intel PXA255 CPU */
#define CONFIG_PALMTC 1 /* Palm Tungsten|C board */
+/* we will never enable dcache, because we have to setup MMU first */
+#define CONFIG_SYS_DCACHE_OFF
+
/*
* Environment settings
*/
#define CONFIG_DOS_PARTITION
#define CONFIG_EFI_PARTITION
+#define CONFIG_FS_EXT4
+#define CONFIG_FS_FAT
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FS_GENERIC
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_MXC_GPIO
#define CONFIG_HW_WATCHDOG
+#define CONFIG_IMX_WATCHDOG
#define CONFIG_MXC_SPI
#define CONFIG_DEFAULT_SPI_BUS 1
#define CONFIG_S5P 1 /* which is in a S5P Family */
#define CONFIG_EXYNOS4210 1 /* which is in a EXYNOS4210 */
#define CONFIG_UNIVERSAL 1 /* working with Universal */
+#define CONFIG_TIZEN 1 /* TIZEN lib */
#include <asm/arch/cpu.h> /* get chip and board defs */
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG
#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
#define CONFIG_USB_GADGET_S3C_UDC_OTG
#define CONFIG_USB_GADGET_DUALSPEED
+/*
+ * SPI Settings
+ */
+#define CONFIG_SOFT_SPI
+#define CONFIG_SOFT_SPI_MODE SPI_MODE_3
+#define CONFIG_SOFT_SPI_GPIO_SCLK exynos4_gpio_part2_get_nr(y3, 1)
+#define CONFIG_SOFT_SPI_GPIO_MOSI exynos4_gpio_part2_get_nr(y3, 3)
+#define CONFIG_SOFT_SPI_GPIO_MISO exynos4_gpio_part2_get_nr(y3, 0)
+#define CONFIG_SOFT_SPI_GPIO_CS exynos4_gpio_part2_get_nr(y4, 3)
+
+#define SPI_DELAY udelay(1)
+#undef SPI_INIT
+#define SPI_SCL(bit) universal_spi_scl(bit)
+#define SPI_SDA(bit) universal_spi_sda(bit)
+#define SPI_READ universal_spi_read()
+#ifndef __ASSEMBLY__
+void universal_spi_scl(int bit);
+void universal_spi_sda(int bit);
+int universal_spi_read(void);
+#endif
+
+/*
+ * LCD Settings
+ */
+#define CONFIG_EXYNOS_FB
+#define CONFIG_LCD
+#define CONFIG_CMD_BMP
+#define CONFIG_BMP_32BPP
+#define CONFIG_LD9040
+#define CONFIG_EXYNOS_MIPI_DSIM
+#define CONFIG_VIDEO_BMP_GZIP
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((520 * 120 * 4) + (1 << 12))
+
#endif /* __CONFIG_H */
#define CONFIG_MACH_TYPE MACH_TYPE_SEABOARD
#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT /* Make sure LCD init is complete */
/* I2C */
#define CONFIG_TEGRA_I2C
#define CONFIG_DOS_PARTITION
#define CONFIG_EFI_PARTITION
+#define CONFIG_FS_EXT4
+#define CONFIG_FS_FAT
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FS_GENERIC
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
/* USB keyboard */
#define CONFIG_USB_KEYBOARD
-#include "tegra-common-post.h"
+/* LCD support */
+#define CONFIG_LCD
+#define CONFIG_PWM_TEGRA
+#define CONFIG_VIDEO_TEGRA
+#define LCD_BPP LCD_COLOR16
+#define CONFIG_SYS_WHITE_ON_BLACK
+#define CONFIG_CONSOLE_SCROLL_LINES 10
/* NAND support */
#define CONFIG_CMD_NAND
/* Max number of NAND devices */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-/* Somewhat oddly, the NAND base address must be a config option */
-#define CONFIG_SYS_NAND_BASE NV_PA_NAND_BASE
+#include "tegra-common-post.h"
+
#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * Configuation settings for the sh7752evb board
+ *
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __SH7752EVB_H
+#define __SH7752EVB_H
+
+#undef DEBUG
+#define CONFIG_SH 1
+#define CONFIG_SH4A 1
+#define CONFIG_SH_32BIT 1
+#define CONFIG_CPU_SH7752 1
+#define CONFIG_SH7752EVB 1
+
+#define CONFIG_SYS_TEXT_BASE 0x5ff80000
+#define CONFIG_SYS_LDSCRIPT "board/renesas/sh7752evb/u-boot.lds"
+
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_DFL
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_MD5SUM
+#define CONFIG_MD5
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MAC_PARTITION
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTARGS "console=ttySC2,115200 root=/dev/nfs ip=dhcp"
+
+#define CONFIG_VERSION_VARIABLE
+#undef CONFIG_SHOW_BOOT_PROGRESS
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+
+/* MEMORY */
+#define SH7752EVB_SDRAM_BASE (0x40000000)
+#define SH7752EVB_SDRAM_SIZE (512 * 1024 * 1024)
+
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT "=> "
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_PBSIZE 256
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_BARGSIZE 512
+#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
+
+/* SCIF */
+#define CONFIG_SCIF_CONSOLE 1
+#define CONFIG_CONS_SCIF2 1
+#undef CONFIG_SYS_CONSOLE_INFO_QUIET
+#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+
+#define CONFIG_SYS_MEMTEST_START (SH7752EVB_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
+ 480 * 1024 * 1024)
+#undef CONFIG_SYS_ALT_MEMTEST
+#undef CONFIG_SYS_MEMTEST_SCRATCH
+#undef CONFIG_SYS_LOADS_BAUD_CHANGE
+
+#define CONFIG_SYS_SDRAM_BASE (SH7752EVB_SDRAM_BASE)
+#define CONFIG_SYS_SDRAM_SIZE (SH7752EVB_SDRAM_SIZE)
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \
+ 128 * 1024 * 1024)
+
+#define CONFIG_SYS_MONITOR_BASE 0x00000000
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
+#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
+
+/* FLASH */
+#define CONFIG_SYS_NO_FLASH
+
+/* Ether */
+#define CONFIG_SH_ETHER 1
+#define CONFIG_SH_ETHER_USE_PORT 0
+#define CONFIG_SH_ETHER_PHY_ADDR 18
+#define CONFIG_SH_ETHER_CACHE_WRITEBACK 1
+#define CONFIG_SH_ETHER_USE_GETHER 1
+#define CONFIG_PHYLIB
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII
+#define CONFIG_PHY_VITESSE
+
+#define SH7752EVB_ETHERNET_MAC_BASE_SPI 0x00090000
+#define SH7752EVB_SPI_SECTOR_SIZE (64 * 1024)
+#define SH7752EVB_ETHERNET_MAC_BASE SH7752EVB_ETHERNET_MAC_BASE_SPI
+#define SH7752EVB_ETHERNET_MAC_SIZE 17
+#define SH7752EVB_ETHERNET_NUM_CH 2
+#define CONFIG_BOARD_LATE_INIT
+
+/* SPI */
+#define CONFIG_SH_SPI 1
+#define CONFIG_SH_SPI_BASE 0xfe002000
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO 1
+#define CONFIG_SPI_FLASH_MACRONIX 1
+
+/* MMCIF */
+#define CONFIG_MMC 1
+#define CONFIG_GENERIC_MMC 1
+#define CONFIG_SH_MMCIF 1
+#define CONFIG_SH_MMCIF_ADDR 0xffcb0000
+#define CONFIG_SH_MMCIF_CLK 48000000
+
+/* ENV setting */
+#define CONFIG_ENV_IS_EMBEDDED
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
+#define CONFIG_ENV_ADDR (0x00080000)
+#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR)
+#define CONFIG_ENV_OVERWRITE 1
+#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netboot=bootp; bootm\0"
+
+/* Board Clock */
+#define CONFIG_SYS_CLK_FREQ 48000000
+#define CONFIG_SYS_TMU_CLK_DIV 4
+#define CONFIG_SYS_HZ 1000
+#endif /* __SH7752EVB_H */
/*
- * Copyright (C) 2011 Samsung Electronics
+ * Copyright (C) 2012 Samsung Electronics
*
- * Configuration settings for the SAMSUNG SMDK5250 (EXYNOS5250) board.
+ * Configuration settings for the SAMSUNG SMDK5250 board.
*
* See file CREDITS for list of people who contributed to this
* project.
* MA 02111-1307 USA
*/
-#ifndef __CONFIG_H
-#define __CONFIG_H
+#ifndef __CONFIG_SMDK_H
+#define __CONFIG_SMDK_H
-/* High Level Configuration Options */
-#define CONFIG_SAMSUNG /* in a SAMSUNG core */
-#define CONFIG_S5P /* S5P Family */
-#define CONFIG_EXYNOS5 /* which is in a Exynos5 Family */
-#define CONFIG_SMDK5250 /* which is in a SMDK5250 */
+#include <configs/exynos5250-dt.h>
-#include <asm/arch/cpu.h> /* get chip and board defs */
+#undef CONFIG_DEFAULT_DEVICE_TREE
+#define CONFIG_DEFAULT_DEVICE_TREE exynos5250-smdk5250
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
-/* Keep L2 Cache Disabled */
-#define CONFIG_SYS_DCACHE_OFF
-
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
-#define CONFIG_SYS_TEXT_BASE 0x43E00000
-
-/* input clock of PLL: SMDK5250 has 24MHz input clock */
-#define CONFIG_SYS_CLK_FREQ 24000000
-
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_INITRD_TAG
-#define CONFIG_CMDLINE_EDITING
-
-/* MACH_TYPE_SMDK5250 macro will be removed once added to mach-types */
-#define MACH_TYPE_SMDK5250 3774
-#define CONFIG_MACH_TYPE MACH_TYPE_SMDK5250
-
-/* Power Down Modes */
-#define S5P_CHECK_SLEEP 0x00000BAD
-#define S5P_CHECK_DIDLE 0xBAD00000
-#define S5P_CHECK_LPA 0xABAD0000
-
-/* Offset for inform registers */
-#define INFORM0_OFFSET 0x800
-#define INFORM1_OFFSET 0x804
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
-
-/* select serial console configuration */
-#define CONFIG_SERIAL3 /* use SERIAL 3 */
-#define CONFIG_BAUDRATE 115200
-#define EXYNOS5_DEFAULT_UART_OFFSET 0x010000
-
-#define TZPC_BASE_OFFSET 0x10000
-
-/* SD/MMC configuration */
-#define CONFIG_GENERIC_MMC
-#define CONFIG_MMC
-#define CONFIG_SDHCI
-#define CONFIG_S5P_SDHCI
-
-#define CONFIG_BOARD_EARLY_INIT_F
-
-/* PWM */
-#define CONFIG_PWM
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-/* Command definition*/
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_NET
-
-#define CONFIG_BOOTDELAY 3
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-
-/* USB */
-#define CONFIG_CMD_USB
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_EXYNOS
-#define CONFIG_USB_STORAGE
-
-/* MMC SPL */
-#define CONFIG_SPL
-#define COPY_BL2_FNPTR_ADDR 0x02020030
-
-/* specific .lds file */
-#define CONFIG_SPL_LDSCRIPT "board/samsung/smdk5250/smdk5250-uboot-spl.lds"
-#define CONFIG_SPL_TEXT_BASE 0x02023400
-#define CONFIG_SPL_MAX_SIZE (14 * 1024)
-
-#define CONFIG_BOOTCOMMAND "mmc read 40007000 451 2000; bootm 40007000"
-
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#define CONFIG_SYS_PROMPT "SMDK5250 # "
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-/* memtest works on */
-#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
-
-#define CONFIG_SYS_HZ 1000
-
-#define CONFIG_RD_LVL
-
-#define CONFIG_NR_DRAM_BANKS 8
-#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
-#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
-#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
-#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
-#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
-#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
-#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
-#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
-#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
-#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
-
-#define CONFIG_SYS_MONITOR_BASE 0x00000000
-
-/* FLASH and environment organization */
-#define CONFIG_SYS_NO_FLASH
-#undef CONFIG_CMD_IMLS
-#define CONFIG_IDENT_STRING " for SMDK5250"
-
-#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV 0
-
-#define CONFIG_SECURE_BL1_ONLY
-
-/* Secure FW size configuration */
-#ifdef CONFIG_SECURE_BL1_ONLY
-#define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */
-#else
-#define CONFIG_SEC_FW_SIZE 0
-#endif
-
-/* Configuration of BL1, BL2, ENV Blocks on mmc */
-#define CONFIG_RES_BLOCK_SIZE (512)
-#define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/
-#define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */
-#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
-
-#define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
-#define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
-#define CONFIG_ENV_OFFSET (CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE)
-
-/* U-boot copy size from boot Media to DRAM.*/
-#define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512)
-#define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512)
-#define CONFIG_DOS_PARTITION
-
-#define CONFIG_IRAM_STACK 0x02050000
-
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000)
-
-/* I2C */
-#define CONFIG_SYS_I2C_INIT_BOARD
-#define CONFIG_HARD_I2C
-#define CONFIG_CMD_I2C
-#define CONFIG_SYS_I2C_SPEED 100000 /* 100 Kbps */
-#define CONFIG_DRIVER_S3C24X0_I2C
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_MAX_I2C_NUM 8
-#define CONFIG_SYS_I2C_SLAVE 0x0
-#define CONFIG_I2C_EDID
-
-/* Ethernet Controllor Driver */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_SMC911X
-#define CONFIG_SMC911X_BASE 0x5000000
-#define CONFIG_SMC911X_16_BIT
-#define CONFIG_ENV_SROM_BANK 1
-#endif /*CONFIG_CMD_NET*/
-
-/* Enable devicetree support */
-#define CONFIG_OF_LIBFDT
-
-/* SHA hashing */
-#define CONFIG_CMD_HASH
-#define CONFIG_HASH_VERIFY
-#define CONFIG_SHA1
-#define CONFIG_SHA256
-
-#endif /* __CONFIG_H */
+#endif /* __CONFIG_SMDK_H */
#define CONFIG_SYS_BOOTMAPSZ ((256*1024*1024) - (4*1024))
#define CONFIG_SPL_RAM_DEVICE
-#define CONFIG_SPL_STACK (&__stack_start)
+#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
#define CONFIG_SYS_SPL_MALLOC_START ((unsigned long) (&__malloc_start))
#define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start)
*/
#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
/*
* I2C EEPROM
*/
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
-
/*
* The I2C EEPROM on the TAM3517 contains
* mac address and production data
unsigned char _rev[100];
};
-#define TAM3517_READ_MAC_FROM_EEPROM \
-do { \
- struct tam3517_module_info info;\
- char buf[80], ethname[20]; \
- int i; \
+#define TAM3517_READ_EEPROM(info, ret) \
+do { \
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); \
if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, \
- (void *)&info, sizeof(info))) \
- break; \
+ (void *)info, sizeof(*info))) \
+ ret = 1; \
+ else \
+ ret = 0; \
+} while (0)
+
+#define TAM3517_READ_MAC_FROM_EEPROM(info) \
+do { \
+ char buf[80], ethname[20]; \
+ int i; \
memset(buf, 0, sizeof(buf)); \
- for (i = 0 ; i < ARRAY_SIZE(info.eth_addr); i++) { \
+ for (i = 0 ; i < ARRAY_SIZE((info)->eth_addr); i++) { \
sprintf(buf, "%02X:%02X:%02X:%02X:%02X:%02X", \
- info.eth_addr[i][5], \
- info.eth_addr[i][4], \
- info.eth_addr[i][3], \
- info.eth_addr[i][2], \
- info.eth_addr[i][1], \
- info.eth_addr[i][0]); \
+ (info)->eth_addr[i][5], \
+ (info)->eth_addr[i][4], \
+ (info)->eth_addr[i][3], \
+ (info)->eth_addr[i][2], \
+ (info)->eth_addr[i][1], \
+ (info)->eth_addr[i][0]); \
\
if (i) \
sprintf(ethname, "eth%daddr", i); \
setenv(ethname, buf); \
} \
} while (0)
+
+/* The following macros are taken from Technexion's documentation */
+#define TAM3517_sequence_number(info) \
+ ((info)->sequence_number % 0x1000000000000LL)
+#define TAM3517_week_of_year(info) (((info)->sequence_number >> 48) % 0x100)
+#define TAM3517_year(info) ((info)->sequence_number >> 56)
+#define TAM3517_revision_fixed(info) ((info)->revision % 0x100)
+#define TAM3517_revision_major(info) (((info)->revision >> 8) % 0x100)
+#define TAM3517_revision_tn(info) ((info)->revision >> 16)
+
+#define TAM3517_PRINT_SOM_INFO(info) \
+do { \
+ printf("Vendor:%s\n", (info)->customer); \
+ printf("SOM: %s\n", (info)->product); \
+ printf("SeqNr: %02llu%02llu%012llu\n", \
+ TAM3517_year(info), \
+ TAM3517_week_of_year(info), \
+ TAM3517_sequence_number(info)); \
+ printf("Rev: TN%u %u.%u\n", \
+ TAM3517_revision_tn(info), \
+ TAM3517_revision_major(info), \
+ TAM3517_revision_fixed(info)); \
+} while (0)
+
#endif
#endif /* __TAM3517_H */
#define CONFIG_CMD_NAND
#define CONFIG_TEGRA_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE NV_PA_NAND_BASE
/* Environment in NAND, aligned to start of last sector */
#define CONFIG_ENV_IS_IN_NAND
#else
-#ifdef CONFIG_CMD_EXT2
-#define BOOT_FSTYPE_EXT2 "ext2 "
-#else
-#define BOOT_FSTYPE_EXT2 ""
-#endif
-
-#ifdef CONFIG_CMD_FAT
-#define BOOT_FSTYPE_FAT "fat"
-#else
-#define BOOT_FSTYPE_FAT ""
-#endif
-
#ifdef CONFIG_CMD_MMC
#define BOOTCMDS_MMC \
"mmc_boot=" \
"rootpart=1\0" \
\
"script_boot=" \
- "if ${fs}load ${devtype} ${devnum}:${rootpart} " \
+ "if load ${devtype} ${devnum}:${rootpart} " \
"${scriptaddr} ${prefix}${script}; then " \
"echo ${script} found! Executing ...;" \
"source ${scriptaddr};" \
\
"scan_boot=" \
"echo Scanning ${devtype} ${devnum}...; " \
- "for fs in ${boot_fstypes}; do " \
- "for prefix in ${boot_prefixes}; do " \
- "for script in ${boot_scripts}; do " \
- "run script_boot; " \
- "done; " \
+ "for prefix in ${boot_prefixes}; do " \
+ "for script in ${boot_scripts}; do " \
+ "run script_boot; " \
"done; " \
"done;\0" \
\
BOOT_TARGETS_DHCP " " \
"\0" \
\
- "boot_fstypes=" \
- BOOT_FSTYPE_EXT2 " " \
- BOOT_FSTYPE_FAT " " \
- "\0" \
- \
"boot_prefixes=/ /boot/\0" \
\
"boot_scripts=boot.scr.uimg boot.scr\0" \
#define TEGRA_DEVICE_SETTINGS \
"stdin=serial" STDIN_KBD_KBC STDIN_KBD_USB "\0" \
- "stdout=serial\0" \
- "stderr=serial\0" \
+ "stdout=serial,lcd\0" \
+ "stderr=serial,lcd\0" \
#define CONFIG_EXTRA_ENV_SETTINGS \
TEGRA_DEVICE_SETTINGS \
#ifdef CONFIG_EFI_PARTITION
#undef CONFIG_EFI_PARTITION
#endif
+#ifdef CONFIG_CMD_FS_GENERIC
+#undef CONFIG_CMD_FS_GENERIC
+#endif
+#ifdef CONFIG_CMD_EXT4
+#undef CONFIG_CMD_EXT4
+#endif
#ifdef CONFIG_CMD_EXT2
#undef CONFIG_CMD_EXT2
#endif
#ifdef CONFIG_CMD_FAT
#undef CONFIG_CMD_FAT
#endif
+#ifdef CONFIG_FS_EXT4
+#undef CONFIG_FS_EXT4
+#endif
+#ifdef CONFIG_FS_FAT
+#undef CONFIG_FS_FAT
+#endif
/* remove USB */
#ifdef CONFIG_USB_EHCI
#include <asm/arch/tegra.h> /* get chip and board defs */
+/* Align LCD to 1MB boundary */
+#define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE
+
/*
* Display CPU and Board information
*/
#define CONFIG_CMD_MMC
#define CONFIG_CMD_DFU
#define CONFIG_CMD_GPT
+#define CONFIG_CMD_SETEXPR
/* FAT */
#define CONFIG_CMD_FAT
"name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \
#define CONFIG_DFU_ALT \
- "dfu_alt_info=" \
"u-boot mmc 80 400;" \
- "uImage fat 0 2\0" \
+ "uImage ext4 0 2\0" \
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SYS_CONSOLE_INFO_QUIET
"mmc read 0 0x42100000 0x80 0x200; run updatebackup\0" \
"lpj=lpj=3981312\0" \
"nfsboot=" \
- "set bootargs root=/dev/nfs rw " \
+ "setenv bootargs root=/dev/nfs rw " \
"nfsroot=${nfsroot},nolock,tcp " \
"ip=${ipaddr}:${serverip}:${gatewayip}:" \
"${netmask}:generic:usb0:off " CONFIG_ENV_COMMON_BOOT \
"; run bootk\0" \
"ramfsboot=" \
- "set bootargs root=/dev/ram0 rw rootfstype=ext2 " \
+ "setenv bootargs root=/dev/ram0 rw rootfstype=ext2 " \
"${console} ${meminfo} " \
"initrd=0x43000000,8M ramdisk=8192\0" \
"mmcboot=" \
- "set bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
+ "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
"${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \
"run loaduimage; bootm 0x40007FC0\0" \
- "bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \
+ "bootchart=setenv opts init=/sbin/bootchartd; run bootcmd\0" \
"boottrace=setenv opts initcall_debug; run bootcmd\0" \
"mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \
"verify=n\0" \
"meminfo=crashkernel=32M@0x50000000\0" \
"nfsroot=/nfsroot/arm\0" \
"bootblock=" CONFIG_BOOTBLOCK "\0" \
- "loaduimage=fatload mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \
+ "loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \
"mmcdev=0\0" \
"mmcbootpart=2\0" \
- "mmcrootpart=3\0" \
+ "mmcrootpart=5\0" \
"opts=always_resume=1\0" \
"partitions=" PARTS_DEFAULT \
- CONFIG_DFU_ALT \
+ "dfu_alt_info=" CONFIG_DFU_ALT \
+ "spladdr=0x40000100\0" \
+ "splsize=0x200\0" \
+ "splfile=falcon.bin\0" \
+ "spl_export=" \
+ "setexpr spl_imgsize ${splsize} + 8 ;" \
+ "setexpr spl_imgaddr ${spladdr} - 8 ;" \
+ "setexpr spl_addr_tmp ${spladdr} - 4 ;" \
+ "mw.b ${spl_imgaddr} 0x00 ${spl_imgsize};run loaduimage;" \
+ "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
+ "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo};" \
+ "spl export atags 0x40007FC0;" \
+ "crc32 ${spladdr} ${splsize} ${spl_imgaddr};" \
+ "mw.l ${spl_addr_tmp} ${splsize};" \
+ "ext4write mmc ${mmcdev}:${mmcbootpart}" \
+ " /${splfile} ${spl_imgaddr} ${spl_imgsize};" \
+ "setenv spl_imgsize;" \
+ "setenv spl_imgaddr;" \
+ "setenv spl_addr_tmp;\0"
/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HZ 1000
-/* TRATS has 2 banks of DRAM */
-#define CONFIG_NR_DRAM_BANKS 2
-#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* LDDDR2 DMC 0 */
-#define PHYS_SDRAM_1_SIZE (512 << 20) /* 512 MB in CS 0 */
-#define PHYS_SDRAM_2 0x50000000 /* LPDDR2 DMC 1 */
-#define PHYS_SDRAM_2_SIZE (512 << 20) /* 512 MB in CS 0 */
+/* TRATS has 4 banks of DRAM */
+#define CONFIG_NR_DRAM_BANKS 4
+#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
+#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
+#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
+#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */
#define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */
#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+
+/* EXT4 */
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+/* Falcon mode definitions */
+#define CONFIG_CMD_SPL
+#define CONFIG_SYS_SPL_ARGS_ADDR PHYS_SDRAM_1 + 0x100
/* GPT */
#define CONFIG_EFI_PARTITION
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_CACHELINE_SIZE 32
-
#define CONFIG_SOFT_I2C
#define CONFIG_SOFT_I2C_READ_REPEATED_START
#define CONFIG_SYS_I2C_INIT_BOARD
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_1_SIZE (128 << 20) /* at least 128 MiB */
#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
/* NAND and environment organization */
#define CONFIG_DOS_PARTITION
#define CONFIG_EFI_PARTITION
+#define CONFIG_FS_EXT4
+#define CONFIG_FS_FAT
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FS_GENERIC
/* Environment in SPI */
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET (512 * 1024)
/* USB Host support */
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_TEGRA
#define CONFIG_USB_STORAGE
#define CONFIG_BOOTARGS "root=/dev/ram console=ttyS0,57600" /* RAMdisk */
#define CONFIG_ETHADDR 00:AA:00:14:00:05 /* UTX5 */
#define CONFIG_SERVERIP 10.8.17.105 /* Spree */
-#define CONFIG_SYS_TFTP_LOADADDR 10000
#define CONFIG_EXTRA_ENV_SETTINGS \
"kernel_addr=FFA00000\0" \
#define CONFIG_DOS_PARTITION
#define CONFIG_EFI_PARTITION
+#define CONFIG_FS_EXT4
+#define CONFIG_FS_FAT
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FS_GENERIC
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
/* 166 MHz DDR RAM */
#define CONFIG_SYS_DDR_CLKSEL 0
#define CONFIG_SYS_CLKTL_CBCDR 0x19239100
+#define CONFIG_SYS_MAIN_PWR_ON
#define CONFIG_SYS_NO_FLASH
#define CONFIG_DOS_PARTITION
#define CONFIG_EFI_PARTITION
+#define CONFIG_FS_EXT4
+#define CONFIG_FS_FAT
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FS_GENERIC
/*
* Environment in eMMC, at the end of 2nd "boot sector". Note: This assumes
--- /dev/null
+/*
+ * Copyright (C) 2011 Albert ARIBAUD <albert.u.boot@aribaud.net>
+ *
+ * Based on the netspace_v2 code which is
+ * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _CONFIG_WIRELESS_SPACE_H
+#define _CONFIG_WIRELESS_SPACE_H
+
+/*
+ * Machine number definition
+ */
+#define MACH_TYPE_WIRELESS_SPACE 2500 /* is missing in mach-types.h */
+#define CONFIG_MACH_TYPE MACH_TYPE_WIRELESS_SPACE
+#define CONFIG_IDENT_STRING " Wireless Space"
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
+#define CONFIG_KIRKWOOD /* SoC Family Name */
+/* SoC name */
+#define CONFIG_KW88F6281
+#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH /* no NOR or SPI flash */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_USB
+
+/*
+ * Core clock definition
+ */
+#define CONFIG_SYS_TCLK 166000000 /* 166MHz */
+
+/*
+ * SDRAM configuration
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+
+/*
+ * Different SDRAM configuration and size for some of the boards derived
+ * from the Network Space v2
+ */
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/* Remove or override few declarations from mv-common.h */
+#undef CONFIG_RBTREE
+#undef CONFIG_SYS_IDE_MAXBUS
+#undef CONFIG_SYS_IDE_MAXDEVICE
+#define CONFIG_SYS_IDE_MAXBUS 1
+#define CONFIG_SYS_IDE_MAXDEVICE 1
+#undef CONFIG_SYS_PROMPT
+#define CONFIG_SYS_PROMPT "ws> "
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MISC_INIT_R /* misc_init_r() initializes MAC address */
+#define CONFIG_MVGBE_PORTS {1, 0} /* enable only egiga0... */
+#define PORT_SERIAL_CONTROL_VALUE 0x00A4260E /* ... tied to the switch... */
+#define CONFIG_PHY_BASE_ADR 0xa /* ... through a 'fake' PHY */
+#define CONFIG_MII
+#undef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#define CONFIG_NETCONSOLE
+#define CONFIG_MV88E61XX_SWITCH
+#define CONFIG_MV88E61XX_MULTICHIP_ADRMODE
+#define CONFIG_MV88E61XX_CMD
+#define CONFIG_CMD_TFTPPUT
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * SATA Driver configuration
+ */
+#ifdef CONFIG_MVSATA_IDE
+#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
+#endif /* CONFIG_MVSATA_IDE */
+
+/*
+ * Enable GPI0 support
+ */
+#define CONFIG_KIRKWOOD_GPIO
+
+/*
+ * Enable I2C support
+ */
+#ifdef CONFIG_CMD_I2C
+/* I2C EEPROM HT24LC04 (512B - 32 pages of 16 Bytes) */
+#define CONFIG_CMD_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16-byte page size */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* 8-bit device address */
+#endif /* CONFIG_CMD_I2C */
+
+/*
+ * Partition support
+ */
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+
+/*
+ * File systems support
+ */
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+
+/*
+ * Use the HUSH parser
+ */
+#define CONFIG_SYS_HUSH_PARSER
+
+/*
+ * Console configuration
+ */
+#define CONFIG_CONSOLE_MUX
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+/*
+ * Enable device tree support
+ */
+#define CONFIG_OF_LIBFDT
+
+/*
+ * Environment variables configurations
+ */
+
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128KB */
+#define CONFIG_ENV_SIZE 0x20000 /* 128KB */
+#define CONFIG_ENV_OFFSET 0x80000 /* env starts here */
+
+/*
+ * Board-specific command to make using buttons etc easier
+ */
+
+#define CONFIG_WIRELESS_SPACE_CMD
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_PREBOOT
+
+#define CONFIG_BOOTARGS "console=ttyS0,115200"
+
+#define CONFIG_BOOTCOMMAND \
+ "if run usbload || run diskload; then bootm; fi"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "stdin=serial\0" \
+ "stdout=serial\0" \
+ "stderr=serial\0" \
+ "bootfile=uImage\0" \
+ "loadaddr=0x800000\0" \
+ "autoload=no\0" \
+ "netconsole=" \
+ "set stdin $stdin,nc; " \
+ "set stdout $stdout,nc; " \
+ "set stderr $stderr,nc;\0" \
+ "diskload=ide reset && " \
+ "ext2load ide 0:1 $loadaddr /boot/$bootfile\0" \
+ "usbload=usb start && " \
+ "fatload usb 0:1 $loadaddr /boot/$bootfile\0" \
+ "preboot=" \
+ "dhcp && run netconsole\0"
+
+#endif /* _CONFIG_WIRELESS_SPACE_H */
--- /dev/null
+/*
+ * (C) Copyright 2011, Stefano Babic <sbabic@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Configuration for the woodburn board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+#include "woodburn_common.h"
+
+/* Set TEXT at the beginning of the NOR flash */
+#define CONFIG_SYS_TEXT_BASE 0xA0000000
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * (C) Copyright 2011, Stefano Babic <sbabic@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Configuration for the woodburn board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __WOODBURN_COMMON_CONFIG_H
+#define __WOODBURN_COMMON_CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+
+ /* High Level Configuration Options */
+#define CONFIG_ARM1136 /* This is an arm1136 CPU core */
+#define CONFIG_MX35
+#define CONFIG_MX35_HCLK_FREQ 24000000
+
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_SYS_CACHELINE_SIZE 32
+
+#define CONFIG_DISPLAY_CPUINFO
+
+/* Only in case the value is not present in mach-types.h */
+#ifndef MACH_TYPE_FLEA3
+#define MACH_TYPE_FLEA3 3668
+#endif
+
+#define CONFIG_MACH_TYPE MACH_TYPE_FLEA3
+
+/* This is required to setup the ESDC controller */
+
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_REVISION_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_HARD_I2C
+#define CONFIG_I2C_MXC
+#define CONFIG_SYS_I2C_BASE I2C1_BASE_ADDR
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_MXC_SPI
+#define CONFIG_MXC_GPIO
+
+/* PMIC Controller */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_FSL
+#define CONFIG_PMIC_FSL_MC13892
+#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8
+#define CONFIG_RTC_MC13XXX
+
+
+/* mmc driver */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CONFIG_SYS_FSL_ESDHC_NUM 1
+
+/*
+ * UART (console)
+ */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE UART1_BASE
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+
+/*
+ * Command definition
+ */
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_DNS
+
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_CACHE
+
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+
+#define CONFIG_CMD_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+
+#define CONFIG_CMD_GPIO
+#define CONFIG_MXC_GPIO
+
+#define CONFIG_NET_RETRY_COUNT 100
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
+
+
+/*
+ * Ethernet on SOC (FEC)
+ */
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE FEC_BASE_ADDR
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#define CONFIG_FEC_MXC_PHYADDR 0x1
+
+#define CONFIG_MII
+#define CONFIG_DISCOVER_PHY
+
+#define CONFIG_ARP_TIMEOUT 200UL
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "woodburn U-Boot > "
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
+
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x10000
+
+#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_SYS_HZ 1000
+
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE CSD0_BASE_ADDR
+
+#define CONFIG_SYS_GBL_DATA_OFFSET (LOW_LEVEL_SRAM_STACK - \
+ IRAM_BASE_ADDR - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR (IRAM_BASE_ADDR + \
+ CONFIG_SYS_GBL_DATA_OFFSET)
+
+/*
+ * MTD Command for mtdparts
+ */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_FLASH_CFI_MTD
+#define CONFIG_MTD_PARTITIONS
+#define MTDIDS_DEFAULT "nand0=mxc_nand,nor0=physmap-flash.0"
+#define MTDPARTS_DEFAULT "mtdparts=mxc_nand:50m(root1)," \
+ "32m(rootfb)," \
+ "64m(pcache)," \
+ "64m(app1)," \
+ "10m(app2),-(spool);" \
+ "physmap-flash.0:512k(u-boot),64k(env1)," \
+ "64k(env2),3776k(kernel1),3776k(kernel2)"
+
+/*
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
+/* Monitor at beginning of flash */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+
+#define CONFIG_ENV_SECT_SIZE (128 * 1024)
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+
+/* Address and size of Redundant Environment Sector */
+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
+ CONFIG_SYS_MONITOR_LEN)
+
+#define CONFIG_ENV_IS_IN_FLASH
+
+/*
+ * CFI FLASH driver setup
+ */
+#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
+#define CONFIG_FLASH_CFI_DRIVER
+
+/* A non-standard buffered write algorithm */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* faster */
+#define CONFIG_SYS_FLASH_PROTECTION /* Use hardware sector protection */
+
+/*
+ * NAND FLASH driver setup
+ */
+#define CONFIG_NAND_MXC
+#define CONFIG_NAND_MXC_V1_1
+#define CONFIG_MXC_NAND_REGS_BASE (NFC_BASE_ADDR)
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE (NFC_BASE_ADDR)
+#define CONFIG_MXC_NAND_HWECC
+#define CONFIG_SYS_NAND_LARGEPAGE
+
+#if 0
+#define CONFIG_MTD_DEBUG
+#define CONFIG_MTD_DEBUG_VERBOSE 7
+#endif
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/*
+ * Default environment and default scripts
+ * to update uboot and load kernel
+ */
+#define xstr(s) str(s)
+#define str(s) #s
+
+#define CONFIG_HOSTNAME woodburn
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip_sta=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
+ "addip=if test -n ${ipdyn};then run addip_dyn;" \
+ "else run addip_sta;fi\0" \
+ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+ "addtty=setenv bootargs ${bootargs}" \
+ " console=ttymxc0,${baudrate}\0" \
+ "addmisc=setenv bootargs ${bootargs} ${misc}\0" \
+ "loadaddr=80800000\0" \
+ "kernel_addr_r=80800000\0" \
+ "hostname=" xstr(CONFIG_HOSTNAME) "\0" \
+ "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \
+ "ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0" \
+ "flash_self=run ramargs addip addtty addmtd addmisc;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
+ "bootm ${kernel_addr}\0" \
+ "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
+ "run nfsargs addip addtty addmtd addmisc;" \
+ "bootm ${kernel_addr_r}\0" \
+ "net_self_load=tftp ${kernel_addr_r} ${bootfile};" \
+ "tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \
+ "net_self=if run net_self_load;then " \
+ "run ramargs addip addtty addmtd addmisc;" \
+ "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \
+ "else echo Images not loades;fi\0" \
+ "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \
+ "load=tftp ${loadaddr} ${u-boot}\0" \
+ "uboot_addr=" xstr(CONFIG_SYS_MONITOR_BASE) "\0" \
+ "update=protect off ${uboot_addr} +80000;" \
+ "erase ${uboot_addr} +80000;" \
+ "cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \
+ "upd=if run load;then echo Updating u-boot;if run update;" \
+ "then echo U-Boot updated;" \
+ "else echo Error updating u-boot !;" \
+ "echo Board without bootloader !!;" \
+ "fi;" \
+ "else echo U-Boot not downloaded..exiting;fi\0" \
+ "bootcmd=run net_nfs\0"
+
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * (C) Copyright 2011, Stefano Babic <sbabic@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Configuration for the woodburn board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+#include "woodburn_common.h"
+
+/* Set TEXT in RAM */
+#define CONFIG_SYS_TEXT_BASE 0x82000000
+
+#define CONFIG_BOOT_INTERNAL
+
+/*
+ * SPL
+ */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm1136/u-boot-spl.lds"
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x100 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 /* 512 KB */
+#define CONFIG_SPL_GPIO_SUPPORT
+
+#define CONFIG_SPL_TEXT_BASE 0x10002300
+#define CONFIG_SPL_MAX_SIZE (64 * 1024) /* 8 KB for stack */
+#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
+
+#define CONFIG_SYS_SPL_MALLOC_START 0x8f000000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
+#define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */
+#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
+
+#endif /* __CONFIG_H */
#define CONFIG_ENV_ADDR 0x40000
#define CONFIG_ENV_SIZE 0x20000
+/* we will never enable dcache, because we have to setup MMU first */
+#define CONFIG_SYS_DCACHE_OFF
+
#define CONFIG_SYS_MALLOC_LEN (128*1024)
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_USB_EHCI /* Enable EHCI USB support */
#define CONFIG_USB_EHCI_MXC
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_MXC_USB_PORT 2
-#define CONFIG_MXC_USB_PORTSC 0xC0000000
-#define CONFIG_MXC_USB_FLAGS 0
+#define CONFIG_MXC_USB_PORT 1
+#define CONFIG_MXC_USB_PORTSC MXC_EHCI_MODE_SERIAL
+#define CONFIG_MXC_USB_FLAGS (MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN)
#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_STORAGE
#define CONFIG_DOS_PARTITION
* when associated through the ".callbacks" environment variable, the callback
* will be executed any time the variable is inserted, overwritten, or deleted.
*/
+#ifdef CONFIG_SPL_BUILD
+#define U_BOOT_ENV_CALLBACK(name, callback) \
+ static inline void _u_boot_env_noop_##name(void) \
+ { \
+ (void)callback; \
+ }
+#else
#define U_BOOT_ENV_CALLBACK(name, callback) \
ll_entry_declare(struct env_clbk_tbl, name, env_clbk, env_clbk) = \
{#name, callback}
+#endif
#endif /* __ENV_CALLBACK_H__ */
COMPAT_NVIDIA_TEGRA20_EMC_TABLE, /* Tegra20 memory timing table */
COMPAT_NVIDIA_TEGRA20_KBC, /* Tegra20 Keyboard */
COMPAT_NVIDIA_TEGRA20_NAND, /* Tegra2 NAND controller */
+ COMPAT_NVIDIA_TEGRA20_PWM, /* Tegra 2 PWM controller */
+ COMPAT_NVIDIA_TEGRA20_DC, /* Tegra 2 Display controller */
+ COMPAT_SMSC_LAN9215, /* SMSC 10/100 Ethernet LAN9215 */
+ COMPAT_SAMSUNG_EXYNOS5_SROMC, /* Exynos5 SROMC */
+ COMPAT_SAMSUNG_S3C2440_I2C, /* Exynos I2C Controller */
+ COMPAT_SAMSUNG_EXYNOS5_SOUND, /* Exynos Sound */
+ COMPAT_WOLFSON_WM8994_CODEC, /* Wolfson WM8994 Sound Codec */
+ COMPAT_SAMSUNG_EXYNOS_SPI, /* Exynos SPI */
+ COMPAT_SAMSUNG_EXYNOS_EHCI, /* Exynos EHCI controller */
+ COMPAT_SAMSUNG_EXYNOS_USB_PHY, /* Exynos phy controller for usb2.0 */
+ COMPAT_MAXIM_MAX77686_PMIC, /* MAX77686 PMIC */
COMPAT_COUNT,
};
ulong buffer_write_tout; /* maximum buffer write timeout */
ushort vendor; /* the primary vendor id */
ushort cmd_reset; /* vendor specific reset command */
+ uchar cmd_erase_sector; /* vendor specific erase sect. command */
ushort interface; /* used for x8/x16 adjustments */
ushort legacy_unlock; /* support Intel legacy (un)locking */
ushort manufacturer_id; /* manufacturer id */
extern int get_multi_sda_pin(void);
extern int multi_i2c_init(void);
#endif
+
+/**
+ * Get FDT values for i2c bus.
+ *
+ * @param blob Device tree blbo
+ * @return the number of I2C bus
+ */
+void board_i2c_init(const void *blob);
+
+/**
+ * Find the I2C bus number by given a FDT I2C node.
+ *
+ * @param blob Device tree blbo
+ * @param node FDT I2C node to find
+ * @return the number of I2C bus (zero based), or -1 on error
+ */
+int i2c_get_bus_num_fdt(int node);
+
+/**
+ * Reset the I2C bus represented by the given a FDT I2C node.
+ *
+ * @param blob Device tree blbo
+ * @param node FDT I2C node to find
+ * @return 0 if port was reset, -1 if not found
+ */
+int i2c_reset_port_fdt(const void *blob, int node);
#endif /* _I2C_H_ */
--- /dev/null
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ * R. Chandrasekar <rcsekar@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __I2S_H__
+#define __I2S_H__
+
+/*
+ * DAI hardware audio formats.
+ *
+ * Describes the physical PCM data formating and clocking. Add new formats
+ * to the end.
+ */
+#define SND_SOC_DAIFMT_I2S 1 /* I2S mode */
+#define SND_SOC_DAIFMT_RIGHT_J 2 /* Right Justified mode */
+#define SND_SOC_DAIFMT_LEFT_J 3 /* Left Justified mode */
+#define SND_SOC_DAIFMT_DSP_A 4 /* L data MSB after FRM LRC */
+#define SND_SOC_DAIFMT_DSP_B 5 /* L data MSB during FRM LRC */
+#define SND_SOC_DAIFMT_AC97 6 /* AC97 */
+#define SND_SOC_DAIFMT_PDM 7 /* Pulse density modulation */
+
+/* left and right justified also known as MSB and LSB respectively */
+#define SND_SOC_DAIFMT_MSB SND_SOC_DAIFMT_LEFT_J
+#define SND_SOC_DAIFMT_LSB SND_SOC_DAIFMT_RIGHT_J
+
+/*
+ * DAI hardware signal inversions.
+ *
+ * Specifies whether the DAI can also support inverted clocks for the specified
+ * format.
+ */
+#define SND_SOC_DAIFMT_NB_NF (1 << 8) /* normal bit clock + frame */
+#define SND_SOC_DAIFMT_NB_IF (2 << 8) /* normal BCLK + inv FRM */
+#define SND_SOC_DAIFMT_IB_NF (3 << 8) /* invert BCLK + nor FRM */
+#define SND_SOC_DAIFMT_IB_IF (4 << 8) /* invert BCLK + FRM */
+
+/*
+ * DAI hardware clock masters.
+ *
+ * This is wrt the codec, the inverse is true for the interface
+ * i.e. if the codec is clk and FRM master then the interface is
+ * clk and frame slave.
+ */
+#define SND_SOC_DAIFMT_CBM_CFM (1 << 12) /* codec clk & FRM master */
+#define SND_SOC_DAIFMT_CBS_CFM (2 << 12) /* codec clk slave & FRM master */
+#define SND_SOC_DAIFMT_CBM_CFS (3 << 12) /* codec clk master & frame slave */
+#define SND_SOC_DAIFMT_CBS_CFS (4 << 12) /* codec clk & FRM slave */
+
+#define SND_SOC_DAIFMT_FORMAT_MASK 0x000f
+#define SND_SOC_DAIFMT_CLOCK_MASK 0x00f0
+#define SND_SOC_DAIFMT_INV_MASK 0x0f00
+#define SND_SOC_DAIFMT_MASTER_MASK 0xf000
+
+/*
+ * Master Clock Directions
+ */
+#define SND_SOC_CLOCK_IN 0
+#define SND_SOC_CLOCK_OUT 1
+
+/* I2S Tx Control */
+#define I2S_TX_ON 1
+#define I2S_TX_OFF 0
+
+#define FIFO_LENGTH 64
+
+/* I2s Registers */
+struct i2s_reg {
+ unsigned int con; /* base + 0 , Control register */
+ unsigned int mod; /* Mode register */
+ unsigned int fic; /* FIFO control register */
+ unsigned int psr; /* Reserved */
+ unsigned int txd; /* Transmit data register */
+ unsigned int rxd; /* Receive Data Register */
+};
+
+/* This structure stores the i2s related information */
+struct i2stx_info {
+ unsigned int rfs; /* LR clock frame size */
+ unsigned int bfs; /* Bit slock frame size */
+ unsigned int audio_pll_clk; /* Audio pll frequency in Hz */
+ unsigned int samplingrate; /* sampling rate */
+ unsigned int bitspersample; /* bits per sample */
+ unsigned int channels; /* audio channels */
+ unsigned int base_address; /* I2S Register Base */
+};
+
+/*
+ * Sends the given data through i2s tx
+ *
+ * @param pi2s_tx pointer of i2s transmitter parameter structure.
+ * @param data address of the data buffer
+ * @param data_size array size of the int buffer (total size / size of int)
+ *
+ * @return int value 0 for success, -1 in case of error
+ */
+int i2s_transfer_tx_data(struct i2stx_info *pi2s_tx, unsigned *data,
+ unsigned long data_size);
+
+/*
+ * Initialise i2s transmiter
+ *
+ * @param pi2s_tx pointer of i2s transmitter parameter structure.
+ *
+ * @return int value 0 for success, -1 in case of error
+ */
+int i2s_tx_init(struct i2stx_info *pi2s_tx);
+
+#endif /* __I2S_H__ */
#define IH_MAGIC 0x27051956 /* Image Magic Number */
#define IH_NMLEN 32 /* Image Name Length */
+/* Reused from common.h */
+#define ROUND(a, b) (((a) + (b) - 1) & ~((b) - 1))
+
/*
* Legacy format image header,
* all data in network byte order (aka natural aka bigendian).
extern struct bmp_image *gunzip_bmp(unsigned long addr, unsigned long *lenp);
extern int bmp_display(ulong addr, int x, int y);
+/**
+ * Set whether we need to flush the dcache when changing the LCD image. This
+ * defaults to off.
+ *
+ * @param flush non-zero to flush cache after update, 0 to skip
+ */
+void lcd_set_flush_dcache(int flush);
+
#if defined CONFIG_MPC823
/*
* LCD controller stucture for MPC823 CPU
/* Allow boards to customize the information displayed */
void lcd_show_board_info(void);
+/* Return the size of the LCD frame buffer, and the line length */
+int lcd_get_size(int *line_length);
+
/************************************************************************/
/* ** BITMAP DISPLAY SUPPORT */
/************************************************************************/
--- /dev/null
+/*
+ * ld9040 AMOLED LCD panel driver.
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ * Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __LD9040_H_
+#define __LD9040_H_
+
+void ld9040_cfg_ldo(void);
+void ld9040_enable_ldo(unsigned int onoff);
+
+#endif /* __LD9040_H_ */
--- /dev/null
+/*
+ * (C) Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ */
+
+#ifndef __MC34704_H__
+#define __MC34704_H__
+
+enum {
+ MC34704_RESERVED0_REG = 0, /* 0x00 */
+ MC34704_GENERAL1_REG, /* 0x01 */
+ MC34704_GENERAL2_REG, /* 0x02 */
+ MC34704_GENERAL3_REG, /* 0x03 */
+ MC34704_RESERVED4_REG, /* 0x04 */
+ MC34704_VGSET2_REG, /* 0x05 */
+ MC34704_REG2SET1_REG, /* 0x06 */
+ MC34704_REG2SET2_REG, /* 0x07 */
+ MC34704_REG3SET1_REG, /* 0x08 */
+ MC34704_REG3SET2_REG, /* 0x09 */
+ MC34704_REG4SET1_REG, /* 0x0a */
+ MC34704_REG4SET2_REG, /* 0x0b */
+ MC34704_REG5SET1_REG, /* 0x0c */
+ MC34704_REG5SET2_REG, /* 0x0d */
+ MC34704_REG5SET3_REG, /* 0x0e */
+ MC34704_RESERVEDF_REG, /* 0x0f */
+ MC34704_RESERVED10_REG, /* 0x10 */
+ MC34704_RESERVED11_REG, /* 0x11 */
+ MC34704_RESERVED12_REG, /* 0x12 */
+ MC34704_FSW2SET_REG, /* 0x13 */
+ MC34704_RESERVED14_REG, /* 0x14 */
+ MC34704_REG8SET1_REG, /* 0x15 */
+ MC34704_REG8SET2_REG, /* 0x16 */
+ MC34704_REG8SET3_REG, /* 0x17 */
+ MC34704_FAULTS_REG, /* 0x18 */
+ MC34704_I2CSET1, /* 0x19 */
+ MC34704_NUM_OF_REGS,
+};
+
+/* GENERAL2 register fields */
+#define ONOFFE (1 << 0)
+#define ONOFFD (1 << 1)
+#define ALLOFF (1 << 4)
+
+#endif /* __MC34704_H__ */
* the stuct and enums here are used to specify switch configuration params
*/
#if defined(CONFIG_MV88E61XX_SWITCH)
-enum mv88e61xx_cfg_vlan {
- MV88E61XX_VLANCFG_DEFAULT,
- MV88E61XX_VLANCFG_ROUTER
-};
+
+/* constants for any 88E61xx switch */
+#define MV88E61XX_MAX_PORTS_NUM 6
enum mv88e61xx_cfg_mdip {
MV88E61XX_MDIP_NOCHANGE,
struct mv88e61xx_config {
char *name;
- enum mv88e61xx_cfg_vlan vlancfg;
+ u8 vlancfg[MV88E61XX_MAX_PORTS_NUM];
enum mv88e61xx_cfg_rgmiid rgmii_delay;
enum mv88e61xx_cfg_prtstt portstate;
enum mv88e61xx_cfg_ledinit led_init;
u8 cpuport;
};
+/*
+ * Common mappings for Internal VLANs
+ * These mappings consider that all ports are useable; the driver
+ * will mask inexistent/unused ports.
+ */
+
+/* Switch mode : routes any port to any port */
+#define MV88E61XX_VLANCFG_SWITCH { 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F }
+
+/* Router mode: routes only CPU port 5 to/from non-CPU ports 0-4 */
+#define MV88E61XX_VLANCFG_ROUTER { 0x20, 0x20, 0x20, 0x20, 0x20, 0x1F }
+
int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig);
#endif /* CONFIG_MV88E61XX_SWITCH */
--- /dev/null
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ * Rajeshwari Shinde <rajeshwari.s@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MAX77686_H_
+#define __MAX77686_H_
+
+enum {
+ MAX77686_REG_PMIC_ID = 0x0,
+ MAX77686_REG_PMIC_INTSRC,
+ MAX77686_REG_PMIC_INT1,
+ MAX77686_REG_PMIC_INT2,
+ MAX77686_REG_PMIC_INT1MSK,
+ MAX77686_REG_PMIC_INT2MSK,
+
+ MAX77686_REG_PMIC_STATUS1,
+ MAX77686_REG_PMIC_STATUS2,
+
+ MAX77686_REG_PMIC_PWRON,
+ MAX77686_REG_PMIC_ONOFFDELAY,
+ MAX77686_REG_PMIC_MRSTB,
+
+ MAX77686_REG_PMIC_BUCK1CRTL = 0x10,
+ MAX77686_REG_PMIC_BUCK1OUT,
+ MAX77686_REG_PMIC_BUCK2CTRL1,
+ MAX77686_REG_PMIC_BUCK234FREQ,
+ MAX77686_REG_PMIC_BUCK2DVS1,
+ MAX77686_REG_PMIC_BUCK2DVS2,
+ MAX77686_REG_PMIC_BUCK2DVS3,
+ MAX77686_REG_PMIC_BUCK2DVS4,
+ MAX77686_REG_PMIC_BUCK2DVS5,
+ MAX77686_REG_PMIC_BUCK2DVS6,
+ MAX77686_REG_PMIC_BUCK2DVS7,
+ MAX77686_REG_PMIC_BUCK2DVS8,
+ MAX77686_REG_PMIC_BUCK3CTRL,
+ MAX77686_REG_PMIC_BUCK3DVS1,
+ MAX77686_REG_PMIC_BUCK3DVS2,
+ MAX77686_REG_PMIC_BUCK3DVS3,
+ MAX77686_REG_PMIC_BUCK3DVS4,
+ MAX77686_REG_PMIC_BUCK3DVS5,
+ MAX77686_REG_PMIC_BUCK3DVS6,
+ MAX77686_REG_PMIC_BUCK3DVS7,
+ MAX77686_REG_PMIC_BUCK3DVS8,
+ MAX77686_REG_PMIC_BUCK4CTRL1,
+ MAX77686_REG_PMIC_BUCK4DVS1 = 0x28,
+ MAX77686_REG_PMIC_BUCK4DVS2,
+ MAX77686_REG_PMIC_BUCK4DVS3,
+ MAX77686_REG_PMIC_BUCK4DVS4,
+ MAX77686_REG_PMIC_BUCK4DVS5,
+ MAX77686_REG_PMIC_BUCK4DVS6,
+ MAX77686_REG_PMIC_BUCK4DVS7,
+ MAX77686_REG_PMIC_BUCK4DVS8,
+ MAX77686_REG_PMIC_BUCK5CTRL,
+ MAX77686_REG_PMIC_BUCK5OUT,
+ MAX77686_REG_PMIC_BUCK6CRTL,
+ MAX77686_REG_PMIC_BUCK6OUT,
+ MAX77686_REG_PMIC_BUCK7CRTL,
+ MAX77686_REG_PMIC_BUCK7OUT,
+ MAX77686_REG_PMIC_BUCK8CRTL,
+ MAX77686_REG_PMIC_BUCK8OUT,
+ MAX77686_REG_PMIC_BUCK9CRTL,
+ MAX77686_REG_PMIC_BUCK9OUT,
+
+ MAX77686_REG_PMIC_LDO1CTRL1 = 0x40,
+ MAX77686_REG_PMIC_LDO2CTRL1,
+ MAX77686_REG_PMIC_LDO3CTRL1,
+ MAX77686_REG_PMIC_LDO4CTRL1,
+ MAX77686_REG_PMIC_LDO5CTRL1,
+ MAX77686_REG_PMIC_LDO6CTRL1,
+ MAX77686_REG_PMIC_LDO7CTRL1,
+ MAX77686_REG_PMIC_LDO8CTRL1,
+ MAX77686_REG_PMIC_LDO9CTRL1,
+ MAX77686_REG_PMIC_LDO10CTRL1,
+ MAX77686_REG_PMIC_LDO11CTRL1,
+ MAX77686_REG_PMIC_LDO12CTRL1,
+ MAX77686_REG_PMIC_LDO13CTRL1,
+ MAX77686_REG_PMIC_LDO14CTRL1,
+ MAX77686_REG_PMIC_LDO15CTRL1,
+ MAX77686_REG_PMIC_LDO16CTRL1,
+ MAX77686_REG_PMIC_LDO17CTRL1,
+ MAX77686_REG_PMIC_LDO18CTRL1,
+ MAX77686_REG_PMIC_LDO19CTRL1,
+ MAX77686_REG_PMIC_LDO20CTRL1,
+ MAX77686_REG_PMIC_LDO21CTRL1,
+ MAX77686_REG_PMIC_LDO22CTRL1,
+ MAX77686_REG_PMIC_LDO23CTRL1,
+ MAX77686_REG_PMIC_LDO24CTRL1,
+ MAX77686_REG_PMIC_LDO25CTRL1,
+ MAX77686_REG_PMIC_LDO26CTRL1,
+ MAX77686_REG_PMIC_LDO1CTRL2,
+ MAX77686_REG_PMIC_LDO2CTRL2,
+ MAX77686_REG_PMIC_LDO3CTRL2,
+ MAX77686_REG_PMIC_LDO4CTRL2,
+ MAX77686_REG_PMIC_LDO5CTRL2,
+ MAX77686_REG_PMIC_LDO6CTRL2,
+ MAX77686_REG_PMIC_LDO7CTRL2,
+ MAX77686_REG_PMIC_LDO8CTRL2,
+ MAX77686_REG_PMIC_LDO9CTRL2,
+ MAX77686_REG_PMIC_LDO10CTRL2,
+ MAX77686_REG_PMIC_LDO11CTRL2,
+ MAX77686_REG_PMIC_LDO12CTRL2,
+ MAX77686_REG_PMIC_LDO13CTRL2,
+ MAX77686_REG_PMIC_LDO14CTRL2,
+ MAX77686_REG_PMIC_LDO15CTRL2,
+ MAX77686_REG_PMIC_LDO16CTRL2,
+ MAX77686_REG_PMIC_LDO17CTRL2,
+ MAX77686_REG_PMIC_LDO18CTRL2,
+ MAX77686_REG_PMIC_LDO19CTRL2,
+ MAX77686_REG_PMIC_LDO20CTRL2,
+ MAX77686_REG_PMIC_LDO21CTRL2,
+ MAX77686_REG_PMIC_LDO22CTRL2,
+ MAX77686_REG_PMIC_LDO23CTRL2,
+ MAX77686_REG_PMIC_LDO24CTRL2,
+ MAX77686_REG_PMIC_LDO25CTRL2,
+ MAX77686_REG_PMIC_LDO26CTRL2,
+
+ MAX77686_REG_PMIC_BBAT = 0x7e,
+ MAX77686_REG_PMIC_32KHZ,
+
+ PMIC_NUM_OF_REGS,
+};
+
+/* I2C device address for pmic max77686 */
+#define MAX77686_I2C_ADDR (0x12 >> 1)
+
+enum {
+ REG_DISABLE = 0,
+ REG_ENABLE
+};
+
+enum {
+ LDO_OFF = 0,
+ LDO_ON,
+
+ DIS_LDO = (0x00 << 6),
+ EN_LDO = (0x3 << 6),
+};
+
+#endif /* __MAX77686_PMIC_H_ */
#define MAX8998_LDO3 (1 << 2)
#define MAX8998_LDO4 (1 << 1)
+#define MAX8998_LDO7 (1 << 6)
#define MAX8998_LDO8 (1 << 5)
+#define MAX8998_LDO17 (1 << 4)
#define MAX8998_SAFEOUT1 (1 << 4)
#define MAX8998_I2C_ADDR (0xCC >> 1)
--- /dev/null
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ * R. Chandrasekar < rcsekar@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __SOUND_H__
+#define __SOUND_H__
+
+/* sound codec enum */
+enum en_sound_codec {
+ CODEC_WM_8994,
+ CODEC_WM_8995,
+ CODEC_MAX
+};
+
+/* sound codec enum */
+enum sound_compat {
+ AUDIO_COMPAT_SPI,
+ AUDIO_COMPAT_I2C,
+};
+
+/* Codec information structure to store the info from device tree */
+struct sound_codec_info {
+ int i2c_bus;
+ int i2c_dev_addr;
+ enum en_sound_codec codec_type;
+};
+
+/*
+ * Initialises audio sub system
+ * @param blob Pointer of device tree node or NULL if none.
+ * @return int value 0 for success, -1 for error
+ */
+int sound_init(const void *blob);
+
+/*
+ * plays the pcm data buffer in pcm_data.h through i2s1 to make the
+ * sine wave sound
+ *
+ * @return int 0 for success, -1 for error
+ */
+int sound_play(uint32_t msec, uint32_t frequency);
+
+#endif /* __SOUND__H__ */
#define TWL4030_USB_PHY_CLK_CTRL 0xFE
#define TWL4030_USB_PHY_CLK_CTRL_STS 0xFF
+/* GPIO */
+#define TWL4030_GPIO_GPIODATAIN1 0x00
+#define TWL4030_GPIO_GPIODATAIN2 0x01
+#define TWL4030_GPIO_GPIODATAIN3 0x02
+#define TWL4030_GPIO_GPIODATADIR1 0x03
+#define TWL4030_GPIO_GPIODATADIR2 0x04
+#define TWL4030_GPIO_GPIODATADIR3 0x05
+#define TWL4030_GPIO_GPIODATAOUT1 0x06
+#define TWL4030_GPIO_GPIODATAOUT2 0x07
+#define TWL4030_GPIO_GPIODATAOUT3 0x08
+#define TWL4030_GPIO_CLEARGPIODATAOUT1 0x09
+#define TWL4030_GPIO_CLEARGPIODATAOUT2 0x0A
+#define TWL4030_GPIO_CLEARGPIODATAOUT3 0x0B
+#define TWL4030_GPIO_SETGPIODATAOUT1 0x0C
+#define TWL4030_GPIO_SETGPIODATAOUT2 0x0D
+#define TWL4030_GPIO_SETGPIODATAOUT3 0x0E
+#define TWL4030_GPIO_GPIO_DEBEN1 0x0F
+#define TWL4030_GPIO_GPIO_DEBEN2 0x10
+#define TWL4030_GPIO_GPIO_DEBEN3 0x11
+#define TWL4030_GPIO_GPIO_CTRL 0x12
+#define TWL4030_GPIO_GPIOPUPDCTR1 0x13
+#define TWL4030_GPIO_GPIOPUPDCTR2 0x14
+#define TWL4030_GPIO_GPIOPUPDCTR3 0x15
+#define TWL4030_GPIO_GPIOPUPDCTR4 0x16
+#define TWL4030_GPIO_GPIOPUPDCTR5 0x17
+#define TWL4030_GPIO_GPIO_ISR1A 0x19
+#define TWL4030_GPIO_GPIO_ISR2A 0x1A
+#define TWL4030_GPIO_GPIO_ISR3A 0x1B
+#define TWL4030_GPIO_GPIO_IMR1A 0x1C
+#define TWL4030_GPIO_GPIO_IMR2A 0x1D
+#define TWL4030_GPIO_GPIO_IMR3A 0x1E
+#define TWL4030_GPIO_GPIO_ISR1B 0x1F
+#define TWL4030_GPIO_GPIO_ISR2B 0x20
+#define TWL4030_GPIO_GPIO_ISR3B 0x21
+#define TWL4030_GPIO_GPIO_IMR1B 0x22
+#define TWL4030_GPIO_GPIO_IMR2B 0x23
+#define TWL4030_GPIO_GPIO_IMR3B 0x24
+#define TWL4030_GPIO_GPIO_EDR1 0x28
+#define TWL4030_GPIO_GPIO_EDR2 0x29
+#define TWL4030_GPIO_GPIO_EDR3 0x2A
+#define TWL4030_GPIO_GPIO_EDR4 0x2B
+#define TWL4030_GPIO_GPIO_EDR5 0x2C
+#define TWL4030_GPIO_GPIO_SIH_CTRL 0x2D
+
/*
* Convience functions to read and write from TWL4030
*
int twl6035_i2c_write_u8(u8 chip_no, u8 val, u8 reg);
int twl6035_i2c_read_u8(u8 chip_no, u8 *val, u8 reg);
void twl6035_init_settings(void);
-void twl6035_mmc1_poweron_ldo(void);
+int twl6035_mmc1_poweron_ldo(void);
struct usb_device *usb_alloc_new_device(void *controller);
int usb_new_device(struct usb_device *dev);
+void usb_free_device(void);
#endif /*_USB_H_ */
/*
* For MXC SOCs
*/
+
+/* values for portsc field */
+#define MXC_EHCI_PHY_LOW_POWER_SUSPEND (1 << 23)
+#define MXC_EHCI_FORCE_FS (1 << 24)
+#define MXC_EHCI_UTMI_8BIT (0 << 28)
+#define MXC_EHCI_UTMI_16BIT (1 << 28)
+#define MXC_EHCI_SERIAL (1 << 29)
+#define MXC_EHCI_MODE_UTMI (0 << 30)
+#define MXC_EHCI_MODE_PHILIPS (1 << 30)
+#define MXC_EHCI_MODE_ULPI (2 << 30)
+#define MXC_EHCI_MODE_SERIAL (3 << 30)
+
+/* values for flags field */
+#define MXC_EHCI_INTERFACE_DIFF_UNI (0 << 0)
+#define MXC_EHCI_INTERFACE_DIFF_BI (1 << 0)
+#define MXC_EHCI_INTERFACE_SINGLE_UNI (2 << 0)
+#define MXC_EHCI_INTERFACE_SINGLE_BI (3 << 0)
+#define MXC_EHCI_INTERFACE_MASK (0xf)
+
#define MXC_EHCI_POWER_PINS_ENABLED (1 << 5)
-#define MXC_EHCI_TTL_ENABLED (1 << 6)
-#define MXC_EHCI_INTERNAL_PHY (1 << 7)
+#define MXC_EHCI_PWR_PIN_ACTIVE_HIGH (1 << 6)
+#define MXC_EHCI_OC_PIN_ACTIVE_LOW (1 << 7)
+#define MXC_EHCI_TTL_ENABLED (1 << 8)
+
+#define MXC_EHCI_INTERNAL_PHY (1 << 9)
+#define MXC_EHCI_IPPUE_DOWN (1 << 10)
+#define MXC_EHCI_IPPUE_UP (1 << 11)
/* Board-specific initialization */
int board_ehci_hcd_init(int port);
void reset_4xx_watchdog(void);
#endif
+/* Freescale i.MX */
+#if defined(CONFIG_IMX_WATCHDOG) && !defined(__ASSEMBLY__)
+ void hw_watchdog_init(void);
+#endif
#endif /* _WATCHDOG_H_ */
DEFINE(GENERATED_BD_INFO_SIZE,
(sizeof(struct bd_info) + 15) & ~15);
+ DEFINE(GD_SIZE, sizeof(struct global_data));
+
+ DEFINE(GD_BD, offsetof(struct global_data, bd));
+
+#if defined(CONFIG_ARM)
+
+ DEFINE(GD_RELOCADDR, offsetof(struct global_data, relocaddr));
+
+ DEFINE(GD_RELOC_OFF, offsetof(struct global_data, reloc_off));
+
+ DEFINE(GD_START_ADDR_SP, offsetof(struct global_data, start_addr_sp));
+
+#endif
+
return 0;
}
COMPAT(NVIDIA_TEGRA20_EMC_TABLE, "nvidia,tegra20-emc-table"),
COMPAT(NVIDIA_TEGRA20_KBC, "nvidia,tegra20-kbc"),
COMPAT(NVIDIA_TEGRA20_NAND, "nvidia,tegra20-nand"),
+ COMPAT(NVIDIA_TEGRA20_PWM, "nvidia,tegra20-pwm"),
+ COMPAT(NVIDIA_TEGRA20_DC, "nvidia,tegra20-dc"),
+ COMPAT(SMSC_LAN9215, "smsc,lan9215"),
+ COMPAT(SAMSUNG_EXYNOS5_SROMC, "samsung,exynos-sromc"),
+ COMPAT(SAMSUNG_S3C2440_I2C, "samsung,s3c2440-i2c"),
+ COMPAT(SAMSUNG_EXYNOS5_SOUND, "samsung,exynos-sound"),
+ COMPAT(WOLFSON_WM8994_CODEC, "wolfson,wm8994-codec"),
+ COMPAT(SAMSUNG_EXYNOS_SPI, "samsung,exynos-spi"),
+ COMPAT(SAMSUNG_EXYNOS_EHCI, "samsung,exynos-ehci"),
+ COMPAT(SAMSUNG_EXYNOS_USB_PHY, "samsung,exynos-usb-phy"),
+ COMPAT(MAXIM_MAX77686_PMIC, "maxim,max77686_pmic"),
};
const char *fdtdec_get_compatible(enum fdt_compat_id id)
AFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_NAND_SPL
CFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_NAND_SPL
-SOBJS = start.o lowlevel_init.o
+SOBJS = start.o crt0.o lowlevel_init.o
COBJS = nand_boot_fsl_nfc.o
SRCS := $(SRCTREE)/nand_spl/nand_boot_fsl_nfc.c
SRCS += $(SRCTREE)/arch/arm/cpu/arm1136/start.S
+SRCS += $(SRCTREE)/arch/arm/lib/crt0.S
SRCS += $(SRCTREE)/board/freescale/mx31pdk/lowlevel_init.S
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
__OBJS := $(SOBJS) $(COBJS)
$(obj)%.o: $(SRCTREE)/arch/arm/cpu/arm1136/%.S
$(CC) $(AFLAGS) -c -o $@ $<
+$(obj)%.o: $(SRCTREE)/arch/arm/lib/%.S
+ $(CC) $(AFLAGS) -c -o $@ $<
+
$(obj)%.o: $(SRCTREE)/board/freescale/mx31pdk/%.S
$(CC) $(AFLAGS) -c -o $@ $<
. = ALIGN(4);
+ __image_copy_end = .;
+
.rel.dyn : {
__rel_dyn_start = .;
*(.rel*)
AFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_NAND_SPL
CFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_NAND_SPL
-SOBJS = start.o lowlevel_init.o
+SOBJS = start.o crt0.o lowlevel_init.o
COBJS = nand_boot_fsl_nfc.o
SRCS := $(SRCTREE)/nand_spl/nand_boot_fsl_nfc.c
SRCS += $(SRCTREE)/arch/arm/cpu/arm926ejs/start.S
+SRCS += $(SRCTREE)/arch/arm/lib/crt0.S
SRCS += $(SRCTREE)/board/karo/tx25/lowlevel_init.S
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
__OBJS := $(SOBJS) $(COBJS)
$(obj)%.o: $(SRCTREE)/arch/arm/cpu/arm926ejs/%.S
$(CC) $(AFLAGS) -c -o $@ $<
+$(obj)%.o: $(SRCTREE)/arch/arm/lib/%.S
+ $(CC) $(AFLAGS) -c -o $@ $<
+
$(obj)%.o: $(SRCTREE)/board/karo/tx25/%.S
$(CC) $(AFLAGS) -c -o $@ $<
void link_local_start(void)
{
ip = getenv_IPaddr("llipaddr");
- if (ip != 0 && (ip & IN_CLASSB_NET) != LINKLOCAL_ADDR) {
+ if (ip != 0 && (ntohl(ip) & IN_CLASSB_NET) != LINKLOCAL_ADDR) {
puts("invalid link address");
net_set_state(NETLOOP_FAIL);
return;
static ulong TftpTimeoutMSecs = TIMEOUT;
static int TftpTimeoutCountMax = TIMEOUT_COUNT;
+static ulong time_start; /* Record time we started tftp */
/*
* These globals govern the timeout behavior when attempting a connection to a
TftpNumchars++;
}
#endif
+ time_start = get_timer(time_start);
+ if (time_start > 0) {
+ puts("\n\t "); /* Line up with "Loading: " */
+ print_size(NetBootFileXferSize /
+ time_start * 1000, "/s");
+ }
puts("\ndone\n");
net_set_state(NETLOOP_SUCCESS);
}
TftpState = STATE_SEND_RRQ;
}
+ time_start = get_timer(0);
TftpTimeoutCountMax = TftpRRQTimeoutCountMax;
NetSetTimeout(TftpTimeoutMSecs, TftpTimeout);
$(OBJTREE)/tools/mkimage -T omapimage -n byteswap \
-a $(CONFIG_SPL_TEXT_BASE) -d $< $@
+ifneq ($(CONFIG_IMX_CONFIG),)
+$(OBJTREE)/SPL: $(obj)u-boot-spl.bin
+ $(OBJTREE)/tools/mkimage -n $(SRCTREE)/$(CONFIG_IMX_CONFIG) -T imximage \
+ -e $(CONFIG_SPL_TEXT_BASE) -d $< $@
+endif
+
ALL-y += $(obj)u-boot-spl.bin
ifdef CONFIG_SAMSUNG
*/
int fw_setenv(int argc, char *argv[])
{
- int i, len;
+ int i;
+ size_t len;
char *name;
char *value = NULL;
int lockfd = -1;
int retval = EXIT_SUCCESS;
- lockfd = open(lockname, O_WRONLY | O_CREAT | O_TRUNC);
+ lockfd = open(lockname, O_WRONLY | O_CREAT | O_TRUNC, 0666);
if (-1 == lockfd) {
fprintf(stderr, "Error opening lock file %s\n", lockname);
return EXIT_FAILURE;
/* Set the imx header */
(*set_imx_hdr)(imxhdr, dcd_len, params->ep, imxhdr->flash_offset);
- *header_size_ptr = sbuf->st_size + imxhdr->flash_offset;
+
+ /*
+ * ROM bug alert
+ * mx53 only loads 512 byte multiples.
+ * The remaining fraction of a block bytes would
+ * not be loaded.
+ */
+ *header_size_ptr = ROUND(sbuf->st_size + imxhdr->flash_offset, 512);
}
int imximage_check_params(struct mkimage_params *params)
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