]> git.sur5r.net Git - u-boot/commitdiff
armv8: ls2080aqds: Enable QSPI boot support
authorYuan Yao <yao.yuan@nxp.com>
Wed, 8 Jun 2016 10:25:00 +0000 (18:25 +0800)
committerYork Sun <york.sun@nxp.com>
Fri, 10 Jun 2016 20:45:01 +0000 (13:45 -0700)
This patch adds QSPI boot support for LS2080AQDS board.
The QSPI boot image need to be programmed into the QSPI flash
first. Then we can switch to booting from QSPI memory space.

Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
arch/arm/include/asm/arch-fsl-layerscape/cpu.h
board/freescale/ls2080aqds/ls2080aqds.c
configs/ls2080aqds_qspi_defconfig [new file with mode: 0644]
include/configs/ls2080a_common.h
include/configs/ls2080aqds.h

index 1cebe2fbb010736ae0e35a944773a025e3638701..df877ddc7dc0ec9c49787a4b8169285a18a6219d 100644 (file)
@@ -122,6 +122,8 @@ static const struct sys_mmu_table early_mmu_table[] = {
          PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
        { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
          CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PTE_BLOCK_NON_SHARE },
+       { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
+         CONFIG_SYS_FSL_QSPI_SIZE1,  MT_NORMAL, PTE_BLOCK_NON_SHARE},
        /* For IFC Region #1, only the first 4MB is cache-enabled */
        { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
          CONFIG_SYS_FSL_IFC_SIZE1_1, MT_NORMAL, PTE_BLOCK_NON_SHARE },
@@ -176,6 +178,8 @@ static const struct sys_mmu_table final_mmu_table[] = {
        { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
          CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
          PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
+       { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
+         CONFIG_SYS_FSL_QSPI_SIZE1,  MT_NORMAL, PTE_BLOCK_NON_SHARE},
        { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
          CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE,
          PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
index 694b28b13ca1cbda8a1ed701eb1e7de2589a3860..477f55646f93bd1e646a418ce3e9f4a260ad0e73 100644 (file)
@@ -81,6 +81,8 @@ int checkboard(void)
                puts("PromJet\n");
        else if (sw == 0x9)
                puts("NAND\n");
+       else if (sw == 0xf)
+               puts("QSPI\n");
        else if (sw == 0x15)
                printf("IFCCard\n");
        else
diff --git a/configs/ls2080aqds_qspi_defconfig b/configs/ls2080aqds_qspi_defconfig
new file mode 100644 (file)
index 0000000..0850a68
--- /dev/null
@@ -0,0 +1,37 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS2080AQDS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,QSPI_BOOT,LS2080A"
+CONFIG_BOOTDELAY=10
+CONFIG_HUSH_PARSER=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DM=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_SF=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_OF_LIBFDT=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
index cab3ba9484ae66eddcbe4dadbd8abefc9a3b1f36..ebe14154213c1b413968f07403b6be2a059545f4 100644 (file)
 #define CONFIG_FSL_CAAM                        /* Enable SEC/CAAM */
 
 /* Link Definitions */
+#ifndef CONFIG_QSPI_BOOT
 #ifdef CONFIG_SPL
 #define CONFIG_SYS_TEXT_BASE           0x80400000
 #else
 #define CONFIG_SYS_TEXT_BASE           0x30100000
 #endif
+#endif
 
 #ifdef CONFIG_EMU
 #define CONFIG_SYS_NO_FLASH
index e634d2512ae7321238c780c4a3e7b7d5821d7c5c..df1455bef34297585968095cc2317d1af3bd764b 100644 (file)
@@ -172,11 +172,13 @@ unsigned long get_board_ddr_clk(void);
 #define QIXIS_LBMAP_DFLTBANK           0x00
 #define QIXIS_LBMAP_ALTBANK            0x04
 #define QIXIS_LBMAP_NAND               0x09
+#define QIXIS_LBMAP_QSPI               0x0f
 #define QIXIS_RST_CTL_RESET            0x31
 #define QIXIS_RCFG_CTL_RECONFIG_IDLE   0x20
 #define QIXIS_RCFG_CTL_RECONFIG_START  0x21
 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE  0x08
 #define QIXIS_RCW_SRC_NAND             0x107
+#define QIXIS_RCW_SRC_QSPI             0x62
 #define        QIXIS_RST_FORCE_MEM             0x01
 
 #define CONFIG_SYS_CSPR3_EXT   (0x0)
@@ -267,11 +269,19 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_CS2_FTIM2           CONFIG_SYS_NAND_FTIM2
 #define CONFIG_SYS_CS2_FTIM3           CONFIG_SYS_NAND_FTIM3
 
+#if defined(CONFIG_QSPI_BOOT)
+#define CONFIG_SYS_TEXT_BASE           0x20010000
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE                        0x2000          /* 8KB */
+#define CONFIG_ENV_OFFSET              0x100000        /* 1MB */
+#define CONFIG_ENV_SECT_SIZE           0x10000
+#else
 #define CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_ADDR                        (CONFIG_SYS_FLASH_BASE + 0x200000)
 #define CONFIG_ENV_SECT_SIZE           0x20000
 #define CONFIG_ENV_SIZE                        0x2000
 #endif
+#endif
 
 /* Debug Server firmware */
 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR