Changes since for U-Boot 0.1.0:
======================================================================
+* Fix startup problems with VFD display on TRAB
+
+* Patch by Pierre Aubert, 20 Nov 2002
+ Add driver for Epson SED13806 graphic controller.
+ Add support for BMP logos in cfb_console driver.
+
* Added support for both PCMCIA slots (at the same time!) on MPC8xx
* Patch by Rod Boyce, 21 Nov 2002:
(requires CFG_CMD_DATE)
CONFIG_VIDEO_LOGO display Linux logo in
upper left corner
+ CONFIG_VIDEO_BMP_LOGO use bmp_logo.h instead of
+ linux_logo.h for logo.
+ Requires CONFIG_VIDEO_LOGO
CONFIG_CONSOLE_EXTRA_INFO
addional board info beside
the logo
16,7 Mill (24bit) 315 318 31b
(i.e. setenv videomode 317; saveenv; reset;)
+ CONFIG_VIDEO_SED13806
+ Enable Epson SED13806 driver. This driver supports 8bpp
+ and 16bpp modes defined by CONFIG_VIDEO_SED13806_8BPP
+ or CONFIG_VIDEO_SED13806_16BPP
+
+
- LCD Support: CONFIG_LCD
Define this to enable LCD support (for output to LCD
#
#############################################################################
+CC = $(CROSS_COMPILE)gcc
+AR = $(CROSS_COMPILE)ar
+
TARGETLIB = libx86emu.a
TARGETDEBUGLIB =libx86emud.a
all: $(TARGETLIB) $(TARGETDEBUGLIB)
$(TARGETLIB): $(OBJS)
- ppc-elf32-ar rv $(TARGETLIB) $(OBJS)
+ $(AR) rv $(TARGETLIB) $(OBJS)
$(TARGETDEBUGLIB): $(DEBUGOBJS)
- ppc-elf32-ar rv $(TARGETDEBUGLIB) $(DEBUGOBJS)
+ $(AR) rv $(TARGETDEBUGLIB) $(DEBUGOBJS)
INCS = -I. -Ix86emu -I../../include
CFLAGS = -D__DRIVER__ -DFORCE_POST -D_CEXPORT= -DNO_LONG_LONG -Dprintk=printf -fsigned-char -fomit-frame-pointer -mrelocatable -ffixed-r14 -meabi -mrelocatable -ffixed-r14 -meabi
CDEBUGFLAGS = -DDEBUG
.c.o:
- ppc-elf32-gcc -g -O2 -Wall -c $(CFLAGS) $(INCS) $*.c
+ $(CC) -g -O2 -Wall -c $(CFLAGS) $(INCS) $*.c
.c.d:
- ppc-elf32-gcc -g -O2 -Wall -c -o$*.d $(CFLAGS) $(CDEBUGFLAGS) $(INCS) $*.c
+ $(CC) -g -O2 -Wall -c -o$*.d $(CFLAGS) $(CDEBUGFLAGS) $(INCS) $*.c
.cpp.o:
- ppc-elf32-gcc -c $(CFLAGS) $(INCS) $*.cpp
+ $(CC) -c $(CFLAGS) $(INCS) $*.cpp
clean:
rm -f *.a *.o *.d
validate: validate.o libx86emu.a
- ppc-elf32-gcc -o validate validate.o -lx86emu -L.
+ $(CC) -o validate validate.o -lx86emu -L.
LIB = lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+OBJS = $(BOARD).o flash.o eccx.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $^
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Stäubli Faverges - <www.staubli.com>
+ * Pierre AUBERT p.aubert@staubli.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+/* Video support for the ECCX daughter board */
+
+
+#include <common.h>
+#include <config.h>
+
+#ifdef CONFIG_VIDEO_SED13806
+#include <sed13806.h>
+
+
+
+/* Screen configurations: the initialization of the SD13806 depends on
+ screen and on display mode. We handle only 8bpp and 16 bpp modes */
+
+/* ECCX board is supplied with a NEC NL6448BC20 screen */
+#ifdef CONFIG_NEC_NL6448BC20
+#define DISPLAY_WIDTH 640
+#define DISPLAY_HEIGHT 480
+
+#ifdef CONFIG_VIDEO_SED13806_8BPP
+static const S1D_REGS init_regs [] =
+{
+ {0x0001,0x00}, // Miscellaneous Register
+ {0x01FC,0x00}, // Display Mode Register
+ {0x0004,0x1b}, // General IO Pins Configuration Register 0
+ {0x0005,0x00}, // General IO Pins Configuration Register 1
+ {0x0008,0xe5}, // General IO Pins Control Register 0
+ {0x0009,0x1f}, // General IO Pins Control Register 1
+ {0x0010,0x02}, // Memory Clock Configuration Register
+ {0x0014,0x10}, // LCD Pixel Clock Configuration Register
+ {0x0018,0x02}, // CRT/TV Pixel Clock Configuration Register
+ {0x001C,0x02}, // MediaPlug Clock Configuration Register
+ {0x001E,0x01}, // CPU To Memory Wait State Select Register
+ {0x0021,0x04}, // DRAM Refresh Rate Register
+ {0x002A,0x00}, // DRAM Timings Control Register 0
+ {0x002B,0x01}, // DRAM Timings Control Register 1
+ {0x0020,0x80}, // Memory Configuration Register
+ {0x0030,0x25}, // Panel Type Register
+ {0x0031,0x00}, // MOD Rate Register
+ {0x0032,0x4F}, // LCD Horizontal Display Width Register
+ {0x0034,0x13}, // LCD Horizontal Non-Display Period Register
+ {0x0035,0x01}, // TFT FPLINE Start Position Register
+ {0x0036,0x0B}, // TFT FPLINE Pulse Width Register
+ {0x0038,0xDF}, // LCD Vertical Display Height Register 0
+ {0x0039,0x01}, // LCD Vertical Display Height Register 1
+ {0x003A,0x2C}, // LCD Vertical Non-Display Period Register
+ {0x003B,0x00}, // TFT FPFRAME Start Position Register
+ {0x003C,0x01}, // TFT FPFRAME Pulse Width Register
+ {0x0040,0x03}, // LCD Display Mode Register
+ {0x0041,0x02}, // LCD Miscellaneous Register
+ {0x0042,0x00}, // LCD Display Start Address Register 0
+ {0x0043,0x00}, // LCD Display Start Address Register 1
+ {0x0044,0x00}, // LCD Display Start Address Register 2
+ {0x0046,0x40}, // LCD Memory Address Offset Register 0
+ {0x0047,0x01}, // LCD Memory Address Offset Register 1
+ {0x0048,0x00}, // LCD Pixel Panning Register
+ {0x004A,0x00}, // LCD Display FIFO High Threshold Control Register
+ {0x004B,0x00}, // LCD Display FIFO Low Threshold Control Register
+ {0x0050,0x4F}, // CRT/TV Horizontal Display Width Register
+ {0x0052,0x13}, // CRT/TV Horizontal Non-Display Period Register
+ {0x0053,0x01}, // CRT/TV HRTC Start Position Register
+ {0x0054,0x0B}, // CRT/TV HRTC Pulse Width Register
+ {0x0056,0xDF}, // CRT/TV Vertical Display Height Register 0
+ {0x0057,0x01}, // CRT/TV Vertical Display Height Register 1
+ {0x0058,0x2B}, // CRT/TV Vertical Non-Display Period Register
+ {0x0059,0x09}, // CRT/TV VRTC Start Position Register
+ {0x005A,0x01}, // CRT/TV VRTC Pulse Width Register
+ {0x005B,0x00}, // TV Output Control Register
+ {0x0060,0x03}, // CRT/TV Display Mode Register
+ {0x0062,0x00}, // CRT/TV Display Start Address Register 0
+ {0x0063,0x00}, // CRT/TV Display Start Address Register 1
+ {0x0064,0x00}, // CRT/TV Display Start Address Register 2
+ {0x0066,0x40}, // CRT/TV Memory Address Offset Register 0
+ {0x0067,0x01}, // CRT/TV Memory Address Offset Register 1
+ {0x0068,0x00}, // CRT/TV Pixel Panning Register
+ {0x006A,0x00}, // CRT/TV Display FIFO High Threshold Control Register
+ {0x006B,0x00}, // CRT/TV Display FIFO Low Threshold Control Register
+ {0x0070,0x00}, // LCD Ink/Cursor Control Register
+ {0x0071,0x00}, // LCD Ink/Cursor Start Address Register
+ {0x0072,0x00}, // LCD Cursor X Position Register 0
+ {0x0073,0x00}, // LCD Cursor X Position Register 1
+ {0x0074,0x00}, // LCD Cursor Y Position Register 0
+ {0x0075,0x00}, // LCD Cursor Y Position Register 1
+ {0x0076,0x00}, // LCD Ink/Cursor Blue Color 0 Register
+ {0x0077,0x00}, // LCD Ink/Cursor Green Color 0 Register
+ {0x0078,0x00}, // LCD Ink/Cursor Red Color 0 Register
+ {0x007A,0x1F}, // LCD Ink/Cursor Blue Color 1 Register
+ {0x007B,0x3F}, // LCD Ink/Cursor Green Color 1 Register
+ {0x007C,0x1F}, // LCD Ink/Cursor Red Color 1 Register
+ {0x007E,0x00}, // LCD Ink/Cursor FIFO Threshold Register
+ {0x0080,0x00}, // CRT/TV Ink/Cursor Control Register
+ {0x0081,0x00}, // CRT/TV Ink/Cursor Start Address Register
+ {0x0082,0x00}, // CRT/TV Cursor X Position Register 0
+ {0x0083,0x00}, // CRT/TV Cursor X Position Register 1
+ {0x0084,0x00}, // CRT/TV Cursor Y Position Register 0
+ {0x0085,0x00}, // CRT/TV Cursor Y Position Register 1
+ {0x0086,0x00}, // CRT/TV Ink/Cursor Blue Color 0 Register
+ {0x0087,0x00}, // CRT/TV Ink/Cursor Green Color 0 Register
+ {0x0088,0x00}, // CRT/TV Ink/Cursor Red Color 0 Register
+ {0x008A,0x1F}, // CRT/TV Ink/Cursor Blue Color 1 Register
+ {0x008B,0x3F}, // CRT/TV Ink/Cursor Green Color 1 Register
+ {0x008C,0x1F}, // CRT/TV Ink/Cursor Red Color 1 Register
+ {0x008E,0x00}, // CRT/TV Ink/Cursor FIFO Threshold Register
+ {0x0100,0x00}, // BitBlt Control Register 0
+ {0x0101,0x00}, // BitBlt Control Register 1
+ {0x0102,0x00}, // BitBlt ROP Code/Color Expansion Register
+ {0x0103,0x00}, // BitBlt Operation Register
+ {0x0104,0x00}, // BitBlt Source Start Address Register 0
+ {0x0105,0x00}, // BitBlt Source Start Address Register 1
+ {0x0106,0x00}, // BitBlt Source Start Address Register 2
+ {0x0108,0x00}, // BitBlt Destination Start Address Register 0
+ {0x0109,0x00}, // BitBlt Destination Start Address Register 1
+ {0x010A,0x00}, // BitBlt Destination Start Address Register 2
+ {0x010C,0x00}, // BitBlt Memory Address Offset Register 0
+ {0x010D,0x00}, // BitBlt Memory Address Offset Register 1
+ {0x0110,0x00}, // BitBlt Width Register 0
+ {0x0111,0x00}, // BitBlt Width Register 1
+ {0x0112,0x00}, // BitBlt Height Register 0
+ {0x0113,0x00}, // BitBlt Height Register 1
+ {0x0114,0x00}, // BitBlt Background Color Register 0
+ {0x0115,0x00}, // BitBlt Background Color Register 1
+ {0x0118,0x00}, // BitBlt Foreground Color Register 0
+ {0x0119,0x00}, // BitBlt Foreground Color Register 1
+ {0x01E0,0x00}, // Look-Up Table Mode Register
+ {0x01E2,0x00}, // Look-Up Table Address Register
+ {0x01E4,0x00}, // Look-Up Table Data Register
+ {0x01F0,0x10}, // Power Save Configuration Register
+ {0x01F1,0x00}, // Power Save Status Register
+ {0x01F4,0x00}, // CPU-to-Memory Access Watchdog Timer Register
+ {0x01FC,0x01}, // Display Mode Register
+ {0, 0}
+};
+#endif /* CONFIG_VIDEO_SED13806_8BPP */
+
+#ifdef CONFIG_VIDEO_SED13806_16BPP
+
+static const S1D_REGS init_regs [] =
+{
+ {0x0001,0x00}, // Miscellaneous Register
+ {0x01FC,0x00}, // Display Mode Register
+ {0x0004,0x1b}, // General IO Pins Configuration Register 0
+ {0x0005,0x00}, // General IO Pins Configuration Register 1
+ {0x0008,0xe5}, // General IO Pins Control Register 0
+ {0x0009,0x1f}, // General IO Pins Control Register 1
+ {0x0010,0x02}, // Memory Clock Configuration Register
+ {0x0014,0x10}, // LCD Pixel Clock Configuration Register
+ {0x0018,0x02}, // CRT/TV Pixel Clock Configuration Register
+ {0x001C,0x02}, // MediaPlug Clock Configuration Register
+ {0x001E,0x01}, // CPU To Memory Wait State Select Register
+ {0x0021,0x04}, // DRAM Refresh Rate Register
+ {0x002A,0x00}, // DRAM Timings Control Register 0
+ {0x002B,0x01}, // DRAM Timings Control Register 1
+ {0x0020,0x80}, // Memory Configuration Register
+ {0x0030,0x25}, // Panel Type Register
+ {0x0031,0x00}, // MOD Rate Register
+ {0x0032,0x4F}, // LCD Horizontal Display Width Register
+ {0x0034,0x13}, // LCD Horizontal Non-Display Period Register
+ {0x0035,0x01}, // TFT FPLINE Start Position Register
+ {0x0036,0x0B}, // TFT FPLINE Pulse Width Register
+ {0x0038,0xDF}, // LCD Vertical Display Height Register 0
+ {0x0039,0x01}, // LCD Vertical Display Height Register 1
+ {0x003A,0x2C}, // LCD Vertical Non-Display Period Register
+ {0x003B,0x00}, // TFT FPFRAME Start Position Register
+ {0x003C,0x01}, // TFT FPFRAME Pulse Width Register
+ {0x0040,0x05}, // LCD Display Mode Register
+ {0x0041,0x02}, // LCD Miscellaneous Register
+ {0x0042,0x00}, // LCD Display Start Address Register 0
+ {0x0043,0x00}, // LCD Display Start Address Register 1
+ {0x0044,0x00}, // LCD Display Start Address Register 2
+ {0x0046,0x80}, // LCD Memory Address Offset Register 0
+ {0x0047,0x02}, // LCD Memory Address Offset Register 1
+ {0x0048,0x00}, // LCD Pixel Panning Register
+ {0x004A,0x00}, // LCD Display FIFO High Threshold Control Register
+ {0x004B,0x00}, // LCD Display FIFO Low Threshold Control Register
+ {0x0050,0x4F}, // CRT/TV Horizontal Display Width Register
+ {0x0052,0x13}, // CRT/TV Horizontal Non-Display Period Register
+ {0x0053,0x01}, // CRT/TV HRTC Start Position Register
+ {0x0054,0x0B}, // CRT/TV HRTC Pulse Width Register
+ {0x0056,0xDF}, // CRT/TV Vertical Display Height Register 0
+ {0x0057,0x01}, // CRT/TV Vertical Display Height Register 1
+ {0x0058,0x2B}, // CRT/TV Vertical Non-Display Period Register
+ {0x0059,0x09}, // CRT/TV VRTC Start Position Register
+ {0x005A,0x01}, // CRT/TV VRTC Pulse Width Register
+ {0x005B,0x00}, // TV Output Control Register
+ {0x0060,0x05}, // CRT/TV Display Mode Register
+ {0x0062,0x00}, // CRT/TV Display Start Address Register 0
+ {0x0063,0x00}, // CRT/TV Display Start Address Register 1
+ {0x0064,0x00}, // CRT/TV Display Start Address Register 2
+ {0x0066,0x80}, // CRT/TV Memory Address Offset Register 0
+ {0x0067,0x02}, // CRT/TV Memory Address Offset Register 1
+ {0x0068,0x00}, // CRT/TV Pixel Panning Register
+ {0x006A,0x00}, // CRT/TV Display FIFO High Threshold Control Register
+ {0x006B,0x00}, // CRT/TV Display FIFO Low Threshold Control Register
+ {0x0070,0x00}, // LCD Ink/Cursor Control Register
+ {0x0071,0x00}, // LCD Ink/Cursor Start Address Register
+ {0x0072,0x00}, // LCD Cursor X Position Register 0
+ {0x0073,0x00}, // LCD Cursor X Position Register 1
+ {0x0074,0x00}, // LCD Cursor Y Position Register 0
+ {0x0075,0x00}, // LCD Cursor Y Position Register 1
+ {0x0076,0x00}, // LCD Ink/Cursor Blue Color 0 Register
+ {0x0077,0x00}, // LCD Ink/Cursor Green Color 0 Register
+ {0x0078,0x00}, // LCD Ink/Cursor Red Color 0 Register
+ {0x007A,0x1F}, // LCD Ink/Cursor Blue Color 1 Register
+ {0x007B,0x3F}, // LCD Ink/Cursor Green Color 1 Register
+ {0x007C,0x1F}, // LCD Ink/Cursor Red Color 1 Register
+ {0x007E,0x00}, // LCD Ink/Cursor FIFO Threshold Register
+ {0x0080,0x00}, // CRT/TV Ink/Cursor Control Register
+ {0x0081,0x00}, // CRT/TV Ink/Cursor Start Address Register
+ {0x0082,0x00}, // CRT/TV Cursor X Position Register 0
+ {0x0083,0x00}, // CRT/TV Cursor X Position Register 1
+ {0x0084,0x00}, // CRT/TV Cursor Y Position Register 0
+ {0x0085,0x00}, // CRT/TV Cursor Y Position Register 1
+ {0x0086,0x00}, // CRT/TV Ink/Cursor Blue Color 0 Register
+ {0x0087,0x00}, // CRT/TV Ink/Cursor Green Color 0 Register
+ {0x0088,0x00}, // CRT/TV Ink/Cursor Red Color 0 Register
+ {0x008A,0x1F}, // CRT/TV Ink/Cursor Blue Color 1 Register
+ {0x008B,0x3F}, // CRT/TV Ink/Cursor Green Color 1 Register
+ {0x008C,0x1F}, // CRT/TV Ink/Cursor Red Color 1 Register
+ {0x008E,0x00}, // CRT/TV Ink/Cursor FIFO Threshold Register
+ {0x0100,0x00}, // BitBlt Control Register 0
+ {0x0101,0x00}, // BitBlt Control Register 1
+ {0x0102,0x00}, // BitBlt ROP Code/Color Expansion Register
+ {0x0103,0x00}, // BitBlt Operation Register
+ {0x0104,0x00}, // BitBlt Source Start Address Register 0
+ {0x0105,0x00}, // BitBlt Source Start Address Register 1
+ {0x0106,0x00}, // BitBlt Source Start Address Register 2
+ {0x0108,0x00}, // BitBlt Destination Start Address Register 0
+ {0x0109,0x00}, // BitBlt Destination Start Address Register 1
+ {0x010A,0x00}, // BitBlt Destination Start Address Register 2
+ {0x010C,0x00}, // BitBlt Memory Address Offset Register 0
+ {0x010D,0x00}, // BitBlt Memory Address Offset Register 1
+ {0x0110,0x00}, // BitBlt Width Register 0
+ {0x0111,0x00}, // BitBlt Width Register 1
+ {0x0112,0x00}, // BitBlt Height Register 0
+ {0x0113,0x00}, // BitBlt Height Register 1
+ {0x0114,0x00}, // BitBlt Background Color Register 0
+ {0x0115,0x00}, // BitBlt Background Color Register 1
+ {0x0118,0x00}, // BitBlt Foreground Color Register 0
+ {0x0119,0x00}, // BitBlt Foreground Color Register 1
+ {0x01E0,0x01}, // Look-Up Table Mode Register
+ {0x01E2,0x00}, // Look-Up Table Address Register
+ {0x01E4,0x00}, // Look-Up Table Data Register
+ {0x01F0,0x10}, // Power Save Configuration Register
+ {0x01F1,0x00}, // Power Save Status Register
+ {0x01F4,0x00}, // CPU-to-Memory Access Watchdog Timer Register
+ {0x01FC,0x01}, // Display Mode Register
+ {0, 0}
+};
+
+#endif /* CONFIG_VIDEO_SED13806_16BPP */
+#endif /* CONFIG_NEC_NL6448BC20 */
+
+
+
+#ifdef CONFIG_CONSOLE_EXTRA_INFO
+
+/*-----------------------------------------------------------------------------
+ * video_get_info_str -- setup a board string: type, speed, etc.
+ * line_number= location to place info string beside logo
+ * info= buffer for info string
+ *-----------------------------------------------------------------------------
+ */
+void video_get_info_str (int line_number, char *info)
+{
+ if (line_number == 1) {
+ strcpy (info, " RPXClassic board");
+ }
+ else {
+ info [0] = '\0';
+ }
+
+}
+#endif
+
+/*-----------------------------------------------------------------------------
+ * board_video_init -- init de l'EPSON, config du CS
+ *-----------------------------------------------------------------------------
+ */
+unsigned int board_video_init (void)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+ /* Program ECCX registers */
+ *(ECCX_CSR12) |= ECCX_860;
+ *(ECCX_CSR8) |= ECCX_BE | ECCX_CS2;
+ *(ECCX_CSR8) |= ECCX_ENEPSON;
+
+ memctl->memc_or2 = SED13806_OR;
+ memctl->memc_br2 = SED13806_REG_ADDR | SED13806_ACCES;
+
+ return (SED13806_REG_ADDR);
+}
+
+/*-----------------------------------------------------------------------------
+ * board_validate_screen --
+ *-----------------------------------------------------------------------------
+ */
+void board_validate_screen (unsigned int base)
+{
+ /* Activate the panel bias power */
+ *(volatile unsigned char *)(base + REG_GPIO_CTRL) = 0x80;
+}
+/*-----------------------------------------------------------------------------
+ * board_get_regs --
+ *-----------------------------------------------------------------------------
+ */
+const S1D_REGS *board_get_regs (void)
+{
+ return (init_regs);
+}
+/*-----------------------------------------------------------------------------
+ * board_get_width --
+ *-----------------------------------------------------------------------------
+ */
+int board_get_width (void)
+{
+ return (DISPLAY_WIDTH);
+}
+
+/*-----------------------------------------------------------------------------
+ * board_get_height --
+ *-----------------------------------------------------------------------------
+ */
+int board_get_height (void)
+{
+ return (DISPLAY_HEIGHT);
+}
+
+#endif /* CONFIG_VIDEO_SED13806 */
*/
#include <config.h>
-#include <mpc75x.h>
+#include <74xx_7xx.h>
#include <mpc106.h>
#include <version.h>
int board_init ()
{
+#if defined(CONFIG_MODEM_SUPPORT) && defined(CONFIG_VFD)
+ ulong size;
+ unsigned long addr;
+ extern void mem_malloc_init (ulong);
+ extern int drv_vfd_init(void);
+#endif
DECLARE_GLOBAL_DATA_PTR;
/* memory and cpu-speed are setup before relocation */
gd->bd->bi_boot_params = 0x0c000100;
#ifdef CONFIG_MODEM_SUPPORT
- /* This stuff is needed by the CPLD to read keyboard data.
- * (Copied from the LCD initialization routine.)
- */
- if (rLCDCON1 == 0) {
- extern void init_grid_ctrl(void);
-
- rPCCON = (rPCCON & 0xFFFFFF00)| 0x000000AA;
- rPDCON = (rPDCON & 0xFFFFFF03)| 0x000000A8;
-#if 0
- rPDCON = (rPDCON & 0xFFFFFF00)| 0x000000AA;
+#ifdef CONFIG_VFD
+#ifndef PAGE_SIZE
+#define PAGE_SIZE 4096
#endif
- rLCDCON2 = 0x000DC000;
- rLCDCON3 = 0x0051000A;
- rLCDCON4 = 0x00000001;
- rLCDCON5 = 0x00000440;
- rLCDCON1 = 0x00000B75;
-
- init_grid_ctrl();
- }
+ /*
+ * reserve memory for VFD display (always full pages)
+ */
+ /* armboot_real_end is defined in the board-specific linker script */
+ addr = (_armboot_real_end + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
+ size = vfd_setmem (addr);
+ gd->fb_base = addr;
+ /* round to the next page boundary */
+ addr += size;
+ addr = (addr + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
+ mem_malloc_init (addr);
+ /* must do this after the framebuffer is allocated */
+ drv_vfd_init();
+#endif /* CONFIG_VFD */
udelay_no_timer (KBD_MDELAY);
int drv_vfd_init(void)
{
ulong palette;
+ static int vfd_init_done = 0;
DECLARE_GLOBAL_DATA_PTR;
+ if (vfd_init_done != 0)
+ return;
+ vfd_init_done = 1;
+
vfdbase = gd->fb_base;
create_vfd_table();
init_grid_ctrl();
/*
* Power On.
*/
- printf("\n Slot %c:", 'A' + slot);
+ printf("%s Slot %c:", slot ? "" : "\n", 'A' + slot);
mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
reg = pcmp->pcmc_pipr;
debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
#ifdef CONFIG_LCD
drv_lcd_init ();
#endif
-#ifdef CONFIG_VIDEO
+#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
drv_video_init ();
#endif
#ifdef CONFIG_WL_4PPM_KEYBOARD
* MA 02111-1307 USA
*/
+/* #define DEBUG */
+
#include <common.h>
#include <watchdog.h>
#include <command.h>
s = getenv ("bootdelay");
bootdelay = s ? (int)simple_strtol(s, NULL, 10) : CONFIG_BOOTDELAY;
-#if 0
- printf ("### main_loop entered:\n\n");
-#endif
+ debug ("### main_loop entered: bootdelay=%d\n\n", bootdelay);
# ifdef CONFIG_BOOT_RETRY_TIME
s = getenv ("bootretry");
# endif /* CONFIG_BOOT_RETRY_TIME */
s = getenv ("bootcmd");
+
+ debug ("### main_loop: bootcmd=\"%s\"\n", s ? s : "<UNDEFINED>");
+
if (bootdelay >= 0 && s && !abortboot (bootdelay)) {
# ifdef CONFIG_AUTOBOOT_KEYED
int prev = disable_ctrlc(1); /* disable Control C checking */
}
# ifdef CONFIG_MENUKEY
- if (menukey == CONFIG_MENUKEY)
- {
+ if (menukey == CONFIG_MENUKEY) {
s = getenv("menucmd");
- if (s)
- {
+ if (s) {
# ifndef CFG_HUSH_PARSER
run_command (s, bd, 0);
# else
cfb_console.o cs8900.o dc2114x.o eepro100.o \
i8042.o natsemi.o ns16550.o ns8382x.o ns87308.o \
pci.o pci_auto.o pci_indirect.o \
- pcnet.o serial.o \
+ pcnet.o sed13806.o serial.o \
smc91111.o smiLynxEM.o sym53c8xx.o \
tigon3.o w83c553f.o ct69000.o
CONFIG_CONSOLE_TIME - display time/date in upper right corner,
needs CFG_CMD_DATE and CONFIG_CONSOLE_CURSOR
CONFIG_VIDEO_LOGO - display Linux Logo in upper left corner
+ CONFIG_VIDEO_BMP_LOGO - use bmp_logo instead of linux_logo
CONFIG_CONSOLE_EXTRA_INFO - display additional board information strings
that normaly goes to serial port. This define
requires a board specific function:
#ifdef CONFIG_CFB_CONSOLE
+#include <malloc.h>
+
/*****************************************************************************/
/* Console device defines with SMI graphic */
/* Any other graphic must change this section */
#define VIDEO_HW_BITBLT
#endif
+/*****************************************************************************/
+/* Defines for the SED13806 driver */
+/*****************************************************************************/
+#ifdef CONFIG_VIDEO_SED13806
+
+#define VIDEO_FB_LITTLE_ENDIAN
+#define VIDEO_HW_RECTFILL
+#define VIDEO_HW_BITBLT
+#endif
+
/*****************************************************************************/
/* Include video_fb.h after definitions of VIDEO_HW_RECTFILL etc */
/*****************************************************************************/
#endif /* CONFIG_VIDEO_HW_CURSOR */
#ifdef CONFIG_VIDEO_LOGO
+#ifdef CONFIG_VIDEO_BMP_LOGO
+#include <bmp_logo.h>
+#define VIDEO_LOGO_WIDTH BMP_LOGO_WIDTH
+#define VIDEO_LOGO_HEIGHT BMP_LOGO_HEIGHT
+#define VIDEO_LOGO_LUT_OFFSET BMP_LOGO_OFFSET
+#define VIDEO_LOGO_COLORS BMP_LOGO_COLORS
+
+#else /* CONFIG_VIDEO_BMP_LOGO */
#define LINUX_LOGO_WIDTH 80
#define LINUX_LOGO_HEIGHT 80
#define LINUX_LOGO_COLORS 214
#include <linux_logo.h>
#define VIDEO_LOGO_WIDTH LINUX_LOGO_WIDTH
#define VIDEO_LOGO_HEIGHT LINUX_LOGO_HEIGHT
-
+#define VIDEO_LOGO_LUT_OFFSET LINUX_LOGO_LUT_OFFSET
+#define VIDEO_LOGO_COLORS LINUX_LOGO_COLORS
+#endif /* CONFIG_VIDEO_BMP_LOGO */
#define VIDEO_INFO_X (VIDEO_LOGO_WIDTH)
#define VIDEO_INFO_Y (VIDEO_FONT_HEIGHT/2)
-#else
+#else /* CONFIG_VIDEO_LOGO */
#define VIDEO_LOGO_WIDTH 0
#define VIDEO_LOGO_HEIGHT 0
-#endif
+#endif /* CONFIG_VIDEO_LOGO */
#define VIDEO_COLS VIDEO_VISIBLE_COLS
#define VIDEO_ROWS VIDEO_VISIBLE_ROWS
static void video_putchar(int xx, int yy, unsigned char c)
{
-#ifdef CONFIG_VIDEO_LOGO
video_drawchars (xx, yy + VIDEO_LOGO_HEIGHT, &c, 1);
-#else
- video_drawchars (xx, yy, &c, 1);
-#endif
}
/*****************************************************************************/
#ifdef CONFIG_VIDEO_LOGO
void logo_plot (void *screen, int width, int x, int y)
{
- int skip = (width - LINUX_LOGO_WIDTH) * VIDEO_PIXEL_SIZE,
+
+ int skip = (width - VIDEO_LOGO_WIDTH) * VIDEO_PIXEL_SIZE,
xcount, i,
- ycount = LINUX_LOGO_HEIGHT;
+ ycount = VIDEO_LOGO_HEIGHT;
unsigned char
- *source = linux_logo,
+ *source,
*dest = (unsigned char *) screen + ((y * width * VIDEO_PIXEL_SIZE) + x),
- r, g, b;
-
+ r, g, b, *logo_red, *logo_blue, *logo_green;
+
+#ifdef CONFIG_VIDEO_BMP_LOGO
+ source = bmp_logo_bitmap;
+
+ /* Allocate temporary space for computing colormap */
+ logo_red = malloc (BMP_LOGO_COLORS);
+ logo_green = malloc (BMP_LOGO_COLORS);
+ logo_blue = malloc (BMP_LOGO_COLORS);
+ /* Compute color map */
+ for (i = 0; i < VIDEO_LOGO_COLORS; i++) {
+ logo_red [i] = (bmp_logo_palette [i] & 0x0f00) >> 4;
+ logo_green [i] = (bmp_logo_palette [i] & 0x00f0);
+ logo_blue [i] = (bmp_logo_palette [i] & 0x000f) << 4;
+ }
+#else
+ source = linux_logo;
+ logo_red = linux_logo_red;
+ logo_green = linux_logo_green;
+ logo_blue = linux_logo_blue;
+#endif
+
if (VIDEO_DATA_FORMAT == GDF__8BIT_INDEX)
{
- for (i = 0; i < LINUX_LOGO_COLORS; i++)
+ for (i = 0; i < VIDEO_LOGO_COLORS; i++)
{
- r = (unsigned char)linux_logo_red [i];
- g = (unsigned char)linux_logo_green[i];
- b = (unsigned char)linux_logo_blue [i];
- video_set_lut (LINUX_LOGO_LUT_OFFSET + i, r, g, b);
+ video_set_lut (i + VIDEO_LOGO_LUT_OFFSET,
+ logo_red [i], logo_green [i], logo_blue [i]);
}
}
while (ycount--)
{
- xcount = LINUX_LOGO_WIDTH;
- while (xcount--)
- {
- r = (unsigned char)linux_logo_red [*source - LINUX_LOGO_LUT_OFFSET];
- g = (unsigned char)linux_logo_green[*source - LINUX_LOGO_LUT_OFFSET];
- b = (unsigned char)linux_logo_blue [*source - LINUX_LOGO_LUT_OFFSET];
-
- switch (VIDEO_DATA_FORMAT)
+ xcount = VIDEO_LOGO_WIDTH;
+ while (xcount--)
{
- case GDF__8BIT_INDEX:
- *dest = *source;
- break;
- case GDF__8BIT_332RGB:
- *dest = ((r>>5)<<5) | ((g>>5)<<2) | (b>>6);
- break;
- case GDF_15BIT_555RGB:
- *(unsigned short *)dest =
- SWAP16((unsigned short)(((r>>3)<<10) | ((g>>3)<<5) | (b>>3)));
- break;
- case GDF_16BIT_565RGB:
- *(unsigned short *)dest =
- SWAP16((unsigned short)(((r>>3)<<11) | ((g>>2)<<5) | (b>>3)));
- break;
- case GDF_32BIT_X888RGB:
- *(unsigned long *)dest =
- SWAP32((unsigned long)((r<<16) | (g<<8) | b));
- break;
- case GDF_24BIT_888RGB:
+ r = logo_red [*source - VIDEO_LOGO_LUT_OFFSET];
+ g = logo_green [*source - VIDEO_LOGO_LUT_OFFSET];
+ b = logo_blue [*source - VIDEO_LOGO_LUT_OFFSET];
+
+ switch (VIDEO_DATA_FORMAT)
+ {
+ case GDF__8BIT_INDEX:
+ *dest = *source;
+ break;
+ case GDF__8BIT_332RGB:
+ *dest = ((r>>5)<<5) | ((g>>5)<<2) | (b>>6);
+ break;
+ case GDF_15BIT_555RGB:
+ *(unsigned short *)dest =
+ SWAP16((unsigned short)(((r>>3)<<10) | ((g>>3)<<5) | (b>>3)));
+ break;
+ case GDF_16BIT_565RGB:
+ *(unsigned short *)dest =
+ SWAP16((unsigned short)(((r>>3)<<11) | ((g>>2)<<5) | (b>>3)));
+ break;
+ case GDF_32BIT_X888RGB:
+ *(unsigned long *)dest =
+ SWAP32((unsigned long)((r<<16) | (g<<8) | b));
+ break;
+ case GDF_24BIT_888RGB:
#ifdef VIDEO_FB_LITTLE_ENDIAN
- dest[0] = b;
- dest[1] = g;
- dest[2] = r;
+ dest[0] = b;
+ dest[1] = g;
+ dest[2] = r;
#else
- dest[0] = r;
- dest[1] = g;
- dest[2] = b;
+ dest[0] = r;
+ dest[1] = g;
+ dest[2] = b;
#endif
- break;
+ break;
+ }
+ source++;
+ dest += VIDEO_PIXEL_SIZE;
}
- source++;
- dest += VIDEO_PIXEL_SIZE;
- }
- dest += skip;
+ dest += skip;
}
+#ifdef CONFIG_VIDEO_BMP_LOGO
+ free (logo_red);
+ free (logo_green);
+ free (logo_blue);
+#endif
}
-
/*****************************************************************************/
static void *video_logo (void)
{
char info[128];
+ extern char version_string;
logo_plot (video_fb_address, VIDEO_COLS, 0, 0);
- sprintf(info, " %s (%s - %s)", U_BOOT_VERSION, __DATE__, __TIME__);
+ sprintf(info, " %s", &version_string);
video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y, info);
#ifdef CONFIG_CONSOLE_EXTRA_INFO
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Stäubli Faverges - <www.staubli.com>
+ * Pierre AUBERT p.aubert@staubli.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+/* Video support for Epson SED13806 chipset */
+
+#include <common.h>
+
+#ifdef CONFIG_VIDEO_SED13806
+
+#include <video_fb.h>
+#include <sed13806.h>
+
+#define readByte(ptrReg) \
+ *(volatile unsigned char *)(sed13806.isaBase + ptrReg)
+
+#define writeByte(ptrReg,value) \
+ *(volatile unsigned char *)(sed13806.isaBase + ptrReg) = value
+
+#define writeWord(ptrReg,value) \
+ (*(volatile unsigned short *)(sed13806.isaBase + ptrReg) = ((value >> 8 ) & 0xff) | ((value << 8) & 0xff00))
+
+
+GraphicDevice sed13806;
+
+/*-----------------------------------------------------------------------------
+ * EpsonSetRegs --
+ *-----------------------------------------------------------------------------
+ */
+static void EpsonSetRegs (void)
+{
+ /* the content of the chipset register depends on the board (clocks, ...)*/
+ const S1D_REGS *preg = board_get_regs ();
+ while (preg -> Index) {
+ writeByte (preg -> Index, preg -> Value);
+ preg ++;
+ }
+}
+
+/*-----------------------------------------------------------------------------
+ * video_hw_init --
+ *-----------------------------------------------------------------------------
+ */
+void *video_hw_init (void)
+{
+ unsigned int *vm, i;
+
+ memset (&sed13806, 0, sizeof (GraphicDevice));
+
+ /* Initialization of the access to the graphic chipset
+ Retreive base address of the chipset
+ (see board/RPXClassic/eccx.c) */
+ if ((sed13806.isaBase = board_video_init ()) == 0) {
+ return (NULL);
+ }
+
+ sed13806.frameAdrs = sed13806.isaBase + FRAME_BUFFER_OFFSET;
+ sed13806.winSizeX = board_get_width ();
+ sed13806.winSizeY = board_get_height ();
+
+#if defined(CONFIG_VIDEO_SED13806_8BPP)
+ sed13806.gdfIndex = GDF__8BIT_INDEX;
+ sed13806.gdfBytesPP = 1;
+
+#elif defined(CONFIG_VIDEO_SED13806_16BPP)
+ sed13806.gdfIndex = GDF_16BIT_565RGB;
+ sed13806.gdfBytesPP = 2;
+
+#else
+#error Unsupported SED13806 BPP
+#endif
+
+ sed13806.memSize = sed13806.winSizeX * sed13806.winSizeY * sed13806.gdfBytesPP;
+
+ /* Load SED registers */
+ EpsonSetRegs ();
+
+ /* (see board/RPXClassic/RPXClassic.c) */
+ board_validate_screen (sed13806.isaBase);
+
+ /* Clear video memory */
+ i = sed13806.memSize/4;
+ vm = (unsigned int *)sed13806.frameAdrs;
+ while(i--)
+ *vm++ = 0;
+
+
+ return (&sed13806);
+}
+/*-----------------------------------------------------------------------------
+ * Epson_wait_idle -- Wait for hardware to become idle
+ *-----------------------------------------------------------------------------
+ */
+static void Epson_wait_idle (void)
+{
+ while (readByte (BLT_CTRL0) & 0x80);
+
+ /* Read a word in the BitBLT memory area to shutdown the BitBLT engine */
+ *(volatile unsigned short *)(sed13806.isaBase + BLT_REG);
+}
+
+/*-----------------------------------------------------------------------------
+ * video_hw_bitblt --
+ *-----------------------------------------------------------------------------
+ */
+void video_hw_bitblt (
+ unsigned int bpp, /* bytes per pixel */
+ unsigned int src_x, /* source pos x */
+ unsigned int src_y, /* source pos y */
+ unsigned int dst_x, /* dest pos x */
+ unsigned int dst_y, /* dest pos y */
+ unsigned int dim_x, /* frame width */
+ unsigned int dim_y /* frame height */
+ )
+{
+ register GraphicDevice *pGD = (GraphicDevice *)&sed13806;
+ unsigned long srcAddr, dstAddr;
+ unsigned int stride = bpp * pGD -> winSizeX;
+
+ srcAddr = (src_y * stride) + (src_x * bpp);
+ dstAddr = (dst_y * stride) + (dst_x * bpp);
+
+ Epson_wait_idle ();
+
+ writeByte(BLT_ROP,0x0C); // source
+ writeByte(BLT_OP,0x02);// move blit in positive direction with ROP
+ writeWord(BLT_MEM_OFF0, stride / 2);
+ if (pGD -> gdfIndex == GDF__8BIT_INDEX) {
+ writeByte(BLT_CTRL1,0x00);
+ }
+ else {
+ writeByte(BLT_CTRL1,0x01);
+ }
+
+ writeWord(BLT_WIDTH0,(dim_x - 1));
+ writeWord(BLT_HEIGHT0,(dim_y - 1));
+
+ /* set up blit registers */
+ writeByte(BLT_SRC_ADDR0,srcAddr);
+ writeByte(BLT_SRC_ADDR1,srcAddr>>8);
+ writeByte(BLT_SRC_ADDR2,srcAddr>>16);
+
+ writeByte(BLT_DST_ADDR0,dstAddr);
+ writeByte(BLT_DST_ADDR1,dstAddr>>8);
+ writeByte(BLT_DST_ADDR2,dstAddr>>16);
+
+ /* Engage the blt engine */
+ /* rectangular region for src and dst */
+ writeByte(BLT_CTRL0,0x80);
+
+ /* wait untill current blits finished */
+ Epson_wait_idle ();
+}
+/*-----------------------------------------------------------------------------
+ * video_hw_rectfill --
+ *-----------------------------------------------------------------------------
+ */
+void video_hw_rectfill (
+ unsigned int bpp, /* bytes per pixel */
+ unsigned int dst_x, /* dest pos x */
+ unsigned int dst_y, /* dest pos y */
+ unsigned int dim_x, /* frame width */
+ unsigned int dim_y, /* frame height */
+ unsigned int color /* fill color */
+ )
+{
+ register GraphicDevice *pGD = (GraphicDevice *)&sed13806;
+ unsigned long dstAddr;
+ unsigned int stride = bpp * pGD -> winSizeX;
+
+ dstAddr = (dst_y * stride) + (dst_x * bpp);
+
+ Epson_wait_idle ();
+
+ /* set up blit registers */
+ writeByte(BLT_DST_ADDR0,dstAddr);
+ writeByte(BLT_DST_ADDR1,dstAddr>>8);
+ writeByte(BLT_DST_ADDR2,dstAddr>>16);
+
+ writeWord(BLT_WIDTH0,(dim_x - 1));
+ writeWord(BLT_HEIGHT0,(dim_y - 1));
+ writeWord(BLT_FGCOLOR0,color);
+
+ writeByte(BLT_OP,0x0C); /* solid fill */
+ writeWord(BLT_MEM_OFF0,stride / 2);
+
+ if (pGD -> gdfIndex == GDF__8BIT_INDEX) {
+ writeByte(BLT_CTRL1,0x00);
+ }
+ else {
+ writeByte(BLT_CTRL1,0x01);
+ }
+
+ /* Engage the blt engine */
+ /* rectangular region for src and dst */
+ writeByte(BLT_CTRL0,0x80);
+
+ /* wait untill current blits finished */
+ Epson_wait_idle ();
+}
+
+/*-----------------------------------------------------------------------------
+ * video_set_lut --
+ *-----------------------------------------------------------------------------
+ */
+void video_set_lut (
+ unsigned int index, /* color number */
+ unsigned char r, /* red */
+ unsigned char g, /* green */
+ unsigned char b /* blue */
+ )
+{
+ writeByte(REG_LUT_ADDR, index );
+ writeByte(REG_LUT_DATA, r);
+ writeByte(REG_LUT_DATA, g);
+ writeByte(REG_LUT_DATA, b);
+}
+#ifdef CONFIG_VIDEO_HW_CURSOR
+/*-----------------------------------------------------------------------------
+ * video_set_hw_cursor --
+ *-----------------------------------------------------------------------------
+ */
+void video_set_hw_cursor (int x, int y)
+{
+ writeByte (LCD_CURSOR_XL, (x & 0xff));
+ writeByte (LCD_CURSOR_XM, (x >> 8));
+ writeByte (LCD_CURSOR_YL, (y & 0xff));
+ writeByte (LCD_CURSOR_YM, (y >> 8));
+}
+
+/*-----------------------------------------------------------------------------
+ * video_init_hw_cursor --
+ *-----------------------------------------------------------------------------
+ */
+void video_init_hw_cursor (int font_width, int font_height)
+{
+ volatile unsigned char *ptr;
+ unsigned char pattern;
+ int i;
+
+
+ /* Init cursor content
+ Cursor size is 64x64 pixels
+ Start of the cursor memory depends on panel type (dual panel ...) */
+ if ((i = readByte (LCD_CURSOR_START)) == 0) {
+ ptr = (unsigned char *)(sed13806.frameAdrs + DEFAULT_VIDEO_MEMORY_SIZE - HWCURSORSIZE);
+ }
+ else {
+ ptr = (unsigned char *)(sed13806.frameAdrs + DEFAULT_VIDEO_MEMORY_SIZE - (i * 8192));
+ }
+
+ /* Fill the first line and the first empty line after cursor */
+ for (i = 0, pattern = 0; i < 64; i++) {
+ if (i < font_width) {
+ /* Invert background */
+ pattern |= 0x3;
+
+ }
+ else {
+ /* Background */
+ pattern |= 0x2;
+ }
+ if ((i & 3) == 3) {
+ *ptr = pattern;
+ *(ptr + font_height * 16) = 0xaa;
+ ptr ++;
+ pattern = 0;
+ }
+ pattern <<= 2;
+ }
+
+ /* Duplicate this line */
+ for (i = 1; i < font_height; i++) {
+ memcpy ((void *)ptr, (void *)(ptr - 16), 16);
+ ptr += 16;
+ }
+
+ for (; i < 64; i++) {
+ memcpy ((void *)(ptr + 16), (void *)ptr, 16);
+ ptr += 16;
+ }
+
+ /* Select cursor mode */
+ writeByte (LCD_CURSOR_CNTL, 1);
+}
+#endif
+#endif
#if 0
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
#else
-#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
+#define CONFIG_BOOTDELAY 5 /* autoboot after 1 second */
#endif
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
+#if NOT_USED_FOR_NOW
#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
#if 0
#define CONFIG_AUTOBOOT_PROMPT "Boote in %d Sekunden - stop mit \"2\"\n"
#endif
#define CONFIG_AUTOBOOT_STOP_STR "2" /* easy to stop for now */
+#endif /* NOT_USED_FOR_NOW */
#endif /* __CONFIG_H */
#undef CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */
-
/* Define CONFIG_FEC_ENET to use Fast ethernet instead of ethernet on SCC1 */
-#undef CONFIG_FEC_ENET
+#define CONFIG_FEC_ENET
#ifdef CONFIG_FEC_ENET
#define CFG_DISCOVER_PHY 1
+#define CONFIG_MII 1
#endif /* CONFIG_FEC_ENET */
+/* Video console (graphic: Epson SED13806 on ECCX board, no keyboard */
+#if 1
+#define CONFIG_VIDEO_SED13806
+#define CONFIG_NEC_NL6448BC20
+#define CONFIG_VIDEO_SED13806_16BPP
+
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_CONSOLE_EXTRA_INFO
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_VIDEO_SW_CURSOR
+#endif
+
#if 0
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
#else
#define CFG_SDRAM_BASE 0x00000000
#define CFG_FLASH_BASE 0xFF000000
-#if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE)
+#if defined(DEBUG) || defined (CONFIG_VIDEO_SED13806) || (CONFIG_COMMANDS & CFG_CMD_IDE)
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#else
#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
#if 0
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x20000 /* Offset of Environment Sector */
-#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+#define CFG_ENV_SECT_SIZE 0x8000
+#define CFG_ENV_SIZE 0x8000 /* Total Size of Environment Sector */
#else
#define CFG_ENV_IS_IN_NVRAM 1
#define CFG_ENV_ADDR 0xfa000100
#define CFG_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */
#define CFG_OR4_PRELIM 0xFFF80970
+/* ECCX CS settings */
+#define SED13806_OR 0xFFC00108 /* - 4 Mo
+ - Burst inhibit
+ - external TA */
+#define SED13806_REG_ADDR 0xa0000000
+#define SED13806_ACCES 0x801 /* 16 bit access */
+
+
+/* Global definitions for the ECCX board */
+#define ECCX_CSR_ADDR (0xfac00000)
+#define ECCX_CSR8_OFFSET (0x8)
+#define ECCX_CSR11_OFFSET (0xB)
+#define ECCX_CSR12_OFFSET (0xC)
+
+#define ECCX_CSR8 (volatile unsigned char *)(ECCX_CSR_ADDR + ECCX_CSR8_OFFSET)
+#define ECCX_CSR11 (volatile unsigned char *)(ECCX_CSR_ADDR + ECCX_CSR11_OFFSET)
+#define ECCX_CSR12 (volatile unsigned char *)(ECCX_CSR_ADDR + ECCX_CSR12_OFFSET)
+
+
+#define REG_GPIO_CTRL 0x008
+
+/* Definitions for CSR8 */
+#define ECCX_ENEPSON 0x80 /* Bit 0:
+ 0= disable and reset SED1386
+ 1= enable SED1386 */
+/* Bit 1: 0= SED1386 in Big Endian mode */
+/* 1= SED1386 in little endian mode */
+#define ECCX_LE 0x40
+#define ECCX_BE 0x00
+
+/* Bit 2,3: Selection */
+/* 00 = Disabled */
+/* 01 = CS2 is used for the SED1386 */
+/* 10 = CS5 is used for the SED1386 */
+/* 11 = reserved */
+#define ECCX_CS2 0x10
+#define ECCX_CS5 0x20
+
+/* Definitions for CSR12 */
+#define ECCX_ID 0x02
+#define ECCX_860 0x01
+
/*
* Memory Periodic Timer Prescaler
*/
#ifdef CONFIG_VFD
int drv_vfd_init (void);
#endif
-#ifdef CONFIG_VIDEO
+#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
int drv_video_init (void);
#endif
#ifdef CONFIG_WL_4PPM_KEYBOARD
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Stäubli Faverges - <www.staubli.com>
+ * Pierre AUBERT p.aubert@staubli.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+/* Video support for Epson SED13806 chipset */
+
+
+#ifndef _SED13806_H_
+#define _SED13806_H_
+
+
+/* General definitions */
+#define FRAME_BUFFER_OFFSET 0x200000 /* Frame buffer offset */
+#define TOTAL_SPACE_SIZE 0x400000
+
+#define DEFAULT_VIDEO_MEMORY_SIZE 0x140000 /* Video Memory Size */
+
+#define HWCURSORSIZE 1024 /* Size of memory reserved
+ for HW cursor*/
+
+/* Offset of chipset registers */
+#define BLT_CTRL0 (0x0100)
+#define BLT_CTRL1 (0x0101)
+#define BLT_ROP (0x0102)
+#define BLT_OP (0x0103)
+#define BLT_SRC_ADDR0 (0x0104)
+#define BLT_SRC_ADDR1 (0x0105)
+#define BLT_SRC_ADDR2 (0x0106)
+#define BLT_DST_ADDR0 (0x0108)
+#define BLT_DST_ADDR1 (0x0109)
+#define BLT_DST_ADDR2 (0x010A)
+#define BLT_MEM_OFF0 (0x010C)
+#define BLT_MEM_OFF1 (0x010D)
+#define BLT_WIDTH0 (0x0110)
+#define BLT_WIDTH1 (0x0111)
+#define BLT_HEIGHT0 (0x0112)
+#define BLT_HEIGHT1 (0x0113)
+#define BLT_BGCOLOR0 (0x0114)
+#define BLT_BGCOLOR1 (0x0115)
+#define BLT_FGCOLOR0 (0x0118)
+#define BLT_FGCOLOR1 (0x0119)
+
+#define BLT_REG (0x100000)
+
+/* Lookup table registers */
+#define REG_LUT_ADDR 0x1e2
+#define REG_LUT_DATA 0x1e4
+
+/* Cursor/Ink registers */
+#define LCD_CURSOR_CNTL (0x0070)
+#define LCD_CURSOR_START (0x0071)
+#define LCD_CURSOR_XL (0x0072)
+#define LCD_CURSOR_XM (0x0073)
+#define LCD_CURSOR_YL (0x0074)
+#define LCD_CURSOR_YM (0x0075)
+#define LCD_CURSOR_COL0_B (0x0076)
+#define LCD_CURSOR_COL0_G (0x0077)
+#define LCD_CURSOR_COL0_R (0x0078)
+#define LCD_CURSOR_COL1_B (0x007A)
+#define LCD_CURSOR_COL1_G (0x007B)
+#define LCD_CURSOR_COL1_R (0x007C)
+#define LCD_CURSOR_FIFO (0x007E)
+
+typedef struct
+{
+ unsigned short Index;
+ unsigned char Value;
+} S1D_REGS;
+
+
+
+/* Board specific functions */
+unsigned int board_video_init (void);
+void board_validate_screen (unsigned int base);
+const S1D_REGS *board_get_regs (void);
+int board_get_width (void);
+int board_get_height (void);
+
+#endif /* _SED13806_H_ */
static ulong mem_malloc_end = 0;
static ulong mem_malloc_brk = 0;
-static void mem_malloc_init (ulong dest_addr)
+#if !defined(CONFIG_MODEM_SUPPORT)
+static
+#endif
+void mem_malloc_init (ulong dest_addr)
{
mem_malloc_start = dest_addr;
mem_malloc_end = dest_addr + CFG_MALLOC_LEN;
gd_t gd_data;
bd_t bd_data;
init_fnc_t **init_fnc_ptr;
-#ifdef CONFIG_VFD
+#if defined(CONFIG_VFD) && !defined(CONFIG_MODEM_SUPPORT)
unsigned long addr;
#endif
display_flash_config (size);
#ifdef CONFIG_VFD
+#ifndef CONFIG_MODEM_SUPPORT
#ifndef PAGE_SIZE
#define PAGE_SIZE 4096
#endif
addr += size;
addr = (addr + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
mem_malloc_init (addr);
+#endif /* CONFIG_MODEM_SUPPORT */
#else
/* armboot_real_end is defined in the board-specific linker script */
mem_malloc_init (_armboot_real_end);
#endif /* CONFIG_VFD */
#ifdef CONFIG_VFD
+#ifndef CONFIG_MODEM_SUPPORT
/* must do this after the framebuffer is allocated */
drv_vfd_init();
+#endif /* CONFIG_MODEM_SUPPORT */
#endif
/* initialize environment */
env_relocate ();
ulong xor;
int ret = 0;
- end = base + size;
+ end = (ulong *)((ulong)base + size); /* pointer arith! */
xor = 0;
for(xor = sizeof(ulong); xor > 0; xor <<= 1) {
target = (ulong *)((ulong)testaddr ^ xor);
*/
if (xflag) {
if (ep != addr + sizeof(image_header_t)) {
- fprintf (stderr, "%s: For XIP, the entry point must be the load addr + %d\n",
- cmdname, sizeof(image_header_t));
+ fprintf (stderr, "%s: For XIP, the entry point must be the load addr + %lu\n",
+ cmdname,
+ (unsigned long)sizeof(image_header_t));
exit (EXIT_FAILURE);
}
}
projects / u-boot / commitdiff