]> git.sur5r.net Git - u-boot/commitdiff
arc: add AXS101 board support
authorAlexey Brodkin <Alexey.Brodkin@synopsys.com>
Tue, 4 Feb 2014 08:56:19 +0000 (12:56 +0400)
committerTom Rini <trini@ti.com>
Fri, 7 Feb 2014 13:14:33 +0000 (08:14 -0500)
AXS101 is a new generation of devlopment boards from Synopsys that houses
ASIC with ARC700 and lots of DesignWare peripherals:

 * DW APB UART
 * DW Mobile Storage (MMC/SD)
 * DW I2C
 * DW GMAC

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Vineet Gupta <vgupta@synopsys.com>
Cc: Francois Bedard <fbedard@synopsys.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Heiko Schocher <hs@denx.de>
board/synopsys/axs101/Makefile [new file with mode: 0644]
board/synopsys/axs101/axs101.c [new file with mode: 0644]
board/synopsys/axs101/nand.c [new file with mode: 0644]
boards.cfg
include/configs/axs101.h [new file with mode: 0644]

diff --git a/board/synopsys/axs101/Makefile b/board/synopsys/axs101/Makefile
new file mode 100644 (file)
index 0000000..f0965f7
--- /dev/null
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y  += axs101.o
+obj-$(CONFIG_CMD_NAND) += nand.o
diff --git a/board/synopsys/axs101/axs101.c b/board/synopsys/axs101/axs101.c
new file mode 100644 (file)
index 0000000..4dbeaea
--- /dev/null
@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <dwmmc.h>
+#include <malloc.h>
+#include <netdev.h>
+#include <phy.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_mmc_init(bd_t *bis)
+{
+       struct dwmci_host *host = NULL;
+
+       host = malloc(sizeof(struct dwmci_host));
+       if (!host) {
+               printf("dwmci_host malloc fail!\n");
+               return 1;
+       }
+
+       memset(host, 0, sizeof(struct dwmci_host));
+       host->name = "Synopsys Mobile storage";
+       host->ioaddr = (void *)ARC_DWMMC_BASE;
+       host->buswidth = 4;
+       host->dev_index = 0;
+       host->bus_hz = 25000000;
+
+       add_dwmci(host, 52000000, 400000);
+
+       return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+       if (designware_initialize(0, ARC_DWGMAC_BASE, 0,
+                                 PHY_INTERFACE_MODE_RGMII) >= 0)
+               return 1;
+
+       return 0;
+}
diff --git a/board/synopsys/axs101/nand.c b/board/synopsys/axs101/nand.c
new file mode 100644 (file)
index 0000000..8672803
--- /dev/null
@@ -0,0 +1,226 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <bouncebuf.h>
+#include <common.h>
+#include <malloc.h>
+#include <nand.h>
+#include <asm/io.h>
+
+#define BUS_WIDTH      8               /* AXI data bus width in bytes  */
+
+/* DMA buffer descriptor bits & masks */
+#define BD_STAT_OWN                    (1 << 31)
+#define BD_STAT_BD_FIRST               (1 << 3)
+#define BD_STAT_BD_LAST                        (1 << 2)
+#define BD_SIZES_BUFFER1_MASK          0xfff
+
+#define BD_STAT_BD_COMPLETE    (BD_STAT_BD_FIRST | BD_STAT_BD_LAST)
+
+/* Controller command flags */
+#define B_WFR          (1 << 19)       /* 1b - Wait for ready          */
+#define B_LC           (1 << 18)       /* 1b - Last cycle              */
+#define B_IWC          (1 << 13)       /* 1b - Interrupt when complete */
+
+/* NAND cycle types */
+#define B_CT_ADDRESS   (0x0 << 16)     /* Address operation            */
+#define B_CT_COMMAND   (0x1 << 16)     /* Command operation            */
+#define B_CT_WRITE     (0x2 << 16)     /* Write operation              */
+#define B_CT_READ      (0x3 << 16)     /* Write operation              */
+
+enum nand_isr_t {
+       NAND_ISR_DATAREQUIRED = 0,
+       NAND_ISR_TXUNDERFLOW,
+       NAND_ISR_TXOVERFLOW,
+       NAND_ISR_DATAAVAILABLE,
+       NAND_ISR_RXUNDERFLOW,
+       NAND_ISR_RXOVERFLOW,
+       NAND_ISR_TXDMACOMPLETE,
+       NAND_ISR_RXDMACOMPLETE,
+       NAND_ISR_DESCRIPTORUNAVAILABLE,
+       NAND_ISR_CMDDONE,
+       NAND_ISR_CMDAVAILABLE,
+       NAND_ISR_CMDERROR,
+       NAND_ISR_DATATRANSFEROVER,
+       NAND_ISR_NONE
+};
+
+enum nand_regs_t {
+       AC_FIFO = 0,            /* address and command fifo */
+       IDMAC_BDADDR = 0x18,    /* idmac descriptor list base address */
+       INT_STATUS = 0x118,     /* interrupt status register */
+       INT_CLR_STATUS = 0x120, /* interrupt clear status register */
+};
+
+struct nand_bd {
+       uint32_t status;        /* DES0 */
+       uint32_t sizes;         /* DES1 */
+       uint32_t buffer_ptr0;   /* DES2 */
+       uint32_t buffer_ptr1;   /* DES3 */
+};
+
+#define NAND_REG_WRITE(r, v)   writel(v, CONFIG_SYS_NAND_BASE + r)
+#define NAND_REG_READ(r)       readl(CONFIG_SYS_NAND_BASE + r)
+
+static struct nand_bd *bd;     /* DMA buffer descriptors       */
+
+/**
+ * axs101_nand_write_buf -  write buffer to chip
+ * @mtd:       MTD device structure
+ * @buf:       data buffer
+ * @len:       number of bytes to write
+ */
+static uint32_t nand_flag_is_set(uint32_t flag)
+{
+       uint32_t reg = NAND_REG_READ(INT_STATUS);
+
+       if (reg & (1 << NAND_ISR_CMDERROR))
+               return 0;
+
+       if (reg & (1 << flag)) {
+               NAND_REG_WRITE(INT_CLR_STATUS, 1 << flag);
+               return 1;
+       }
+
+       return 0;
+}
+
+/**
+ * axs101_nand_write_buf -  write buffer to chip
+ * @mtd:       MTD device structure
+ * @buf:       data buffer
+ * @len:       number of bytes to write
+ */
+static void axs101_nand_write_buf(struct mtd_info *mtd, const u_char *buf,
+                                  int len)
+{
+       struct bounce_buffer bbstate;
+
+       bounce_buffer_start(&bbstate, (void *)buf, len, GEN_BB_READ);
+
+       /* Setup buffer descriptor */
+       writel(BD_STAT_OWN | BD_STAT_BD_COMPLETE, &bd->status);
+       writel(ALIGN(len, BUS_WIDTH) & BD_SIZES_BUFFER1_MASK, &bd->sizes);
+       writel(bbstate.bounce_buffer, &bd->buffer_ptr0);
+       writel(0, &bd->buffer_ptr1);
+
+       /* Issue "write" command */
+       NAND_REG_WRITE(AC_FIFO, B_CT_WRITE | B_WFR | B_IWC | B_LC | (len-1));
+
+       /* Wait for NAND command and DMA to complete */
+       while (!nand_flag_is_set(NAND_ISR_CMDDONE))
+               ;
+       while (!nand_flag_is_set(NAND_ISR_TXDMACOMPLETE))
+               ;
+
+       bounce_buffer_stop(&bbstate);
+}
+
+/**
+ * axs101_nand_read_buf -  read chip data into buffer
+ * @mtd:       MTD device structure
+ * @buf:       buffer to store data
+ * @len:       number of bytes to read
+ */
+static void axs101_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
+{
+       struct bounce_buffer bbstate;
+
+       bounce_buffer_start(&bbstate, buf, len, GEN_BB_WRITE);
+
+       /* Setup buffer descriptor */
+       writel(BD_STAT_OWN | BD_STAT_BD_COMPLETE, &bd->status);
+       writel(ALIGN(len, BUS_WIDTH) & BD_SIZES_BUFFER1_MASK, &bd->sizes);
+       writel(bbstate.bounce_buffer, &bd->buffer_ptr0);
+       writel(0, &bd->buffer_ptr1);
+
+       /* Issue "read" command */
+       NAND_REG_WRITE(AC_FIFO, B_CT_READ | B_WFR | B_IWC | B_LC | (len - 1));
+
+       /* Wait for NAND command and DMA to complete */
+       while (!nand_flag_is_set(NAND_ISR_CMDDONE))
+               ;
+       while (!nand_flag_is_set(NAND_ISR_RXDMACOMPLETE))
+               ;
+
+       bounce_buffer_stop(&bbstate);
+}
+
+/**
+ * axs101_nand_read_byte -  read one byte from the chip
+ * @mtd:       MTD device structure
+ */
+static u_char axs101_nand_read_byte(struct mtd_info *mtd)
+{
+       u8 byte;
+
+       axs101_nand_read_buf(mtd, (uchar *)&byte, sizeof(byte));
+       return byte;
+}
+
+/**
+ * axs101_nand_read_word -  read one word from the chip
+ * @mtd:       MTD device structure
+ */
+static u16 axs101_nand_read_word(struct mtd_info *mtd)
+{
+       u16 word;
+
+       axs101_nand_read_buf(mtd, (uchar *)&word, sizeof(word));
+       return word;
+}
+
+/**
+ * axs101_nand_hwcontrol - NAND control functions wrapper.
+ * @mtd:       MTD device structure
+ * @cmd:       Command
+ */
+static void axs101_nand_hwcontrol(struct mtd_info *mtdinfo, int cmd,
+                                  unsigned int ctrl)
+{
+       if (cmd == NAND_CMD_NONE)
+               return;
+
+       cmd = cmd & 0xff;
+
+       switch (ctrl & (NAND_ALE | NAND_CLE)) {
+       /* Address */
+       case NAND_ALE:
+               cmd |= B_CT_ADDRESS;
+               break;
+
+       /* Command */
+       case NAND_CLE:
+               cmd |= B_CT_COMMAND | B_WFR;
+
+               break;
+
+       default:
+               debug("%s: unknown ctrl %#x\n", __func__, ctrl);
+       }
+
+       NAND_REG_WRITE(AC_FIFO, cmd | B_LC);
+       while (!nand_flag_is_set(NAND_ISR_CMDDONE))
+               ;
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+       bd = (struct nand_bd *)memalign(ARCH_DMA_MINALIGN,
+                                       sizeof(struct nand_bd));
+
+       /* Set buffer descriptor address in IDMAC */
+       NAND_REG_WRITE(IDMAC_BDADDR, bd);
+
+       nand->ecc.mode = NAND_ECC_SOFT;
+       nand->cmd_ctrl = axs101_nand_hwcontrol;
+       nand->read_byte = axs101_nand_read_byte;
+       nand->read_word = axs101_nand_read_word;
+       nand->write_buf = axs101_nand_write_buf;
+       nand->read_buf = axs101_nand_read_buf;
+
+       return 0;
+}
index de39bfaa0dc88b1be983a430c6d16842a421ad2f..c97c4bdd5d5a24a63c07dc69e6c6abd9262a1001 100644 (file)
@@ -1230,6 +1230,7 @@ Active  sparc       leon3          -           gaisler         -
 Active  sparc       leon3          -           gaisler         -                   gr_xc3s_1500                         -                                                                                                                                 -
 Active  sparc       leon3          -           gaisler         -                   grsim                                -                                                                                                                                 -
 Active  x86         x86            coreboot    chromebook-x86  coreboot            coreboot-x86                         coreboot:SYS_TEXT_BASE=0x01110000                                                                                                 -
+Active  arc         arc700         -           synopsys        -                   axs101                               -                                                                                                                                 Alexey Brodkin <abrodkin@synopsys.com>
 Active  arc         arc700         -           synopsys        -                   arcangel4                            -                                                                                                                                 Alexey Brodkin <abrodkin@synopsys.com>
 Active  arc         arc700         -           synopsys        arcangel4           arcangel4-be                            -                                                                                                                              Alexey Brodkin <abrodkin@synopsys.com>
 Orphan  arm         arm1136        mx31        -               imx31_phycore       imx31_phycore_eet                    imx31_phycore:IMX31_PHYCORE_EET                                                                                                   (resigned) Guennadi Liakhovetski <g.liakhovetski@gmx.de>
diff --git a/include/configs/axs101.h b/include/configs/axs101.h
new file mode 100644 (file)
index 0000000..af2e63b
--- /dev/null
@@ -0,0 +1,181 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef _CONFIG_AXS101_H_
+#define _CONFIG_AXS101_H_
+
+/*
+ *  CPU configuration
+ */
+#define CONFIG_ARC700
+#define CONFIG_ARC_MMU_VER             3
+#define CONFIG_SYS_CACHELINE_SIZE      32
+#define CONFIG_SYS_CLK_FREQ            750000000
+#define CONFIG_SYS_TIMER_RATE          CONFIG_SYS_CLK_FREQ
+
+/* dwgmac doesn't work with D$ enabled now */
+#define CONFIG_SYS_DCACHE_OFF
+
+/*
+ * Board configuration
+ */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_SKIP_LOWLEVEL_INIT      /* U-Boot is in RAM already */
+
+#define CONFIG_ARCH_EARLY_INIT_R
+
+#define ARC_FPGA_PERIPHERAL_BASE       0xE0000000
+#define ARC_APB_PERIPHERAL_BASE                0xF0000000
+#define ARC_DWMMC_BASE                 (ARC_FPGA_PERIPHERAL_BASE + 0x15000)
+#define ARC_DWGMAC_BASE                        (ARC_FPGA_PERIPHERAL_BASE + 0x18000)
+
+/*
+ * Memory configuration
+ */
+#define CONFIG_SYS_TEXT_BASE           0x81000000
+#define CONFIG_SYS_MONITOR_BASE                CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_DDR_SDRAM_BASE      0x80000000
+#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_SYS_SDRAM_SIZE          0x10000000      /* 256 Mb */
+
+#define CONFIG_SYS_INIT_SP_ADDR                \
+       (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_MALLOC_LEN          0x200000        /* 2 MB */
+#define CONFIG_SYS_BOOTM_LEN           0x2000000       /* 32 MB */
+#define CONFIG_SYS_LOAD_ADDR           0x82000000
+
+/*
+ * NAND Flash configuration
+ */
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_NAND_BASE           (ARC_FPGA_PERIPHERAL_BASE + 0x16000)
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+
+/*
+ * UART configuration
+ *
+ * CONFIG_CONS_INDEX = 1 - Debug UART
+ * CONFIG_CONS_INDEX = 4 - FPGA UART connected to FTDI/USB
+ */
+#define CONFIG_CONS_INDEX              4
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE    -4
+#if (CONFIG_CONS_INDEX == 1)
+       /* Debug UART */
+#      define CONFIG_SYS_NS16550_CLK           33333000
+#else
+       /* FPGA UARTs use different clock */
+#      define CONFIG_SYS_NS16550_CLK           33333333
+#endif
+#define CONFIG_SYS_NS16550_COM1                (ARC_APB_PERIPHERAL_BASE + 0x5000)
+#define CONFIG_SYS_NS16550_COM2                (ARC_FPGA_PERIPHERAL_BASE + 0x20000)
+#define CONFIG_SYS_NS16550_COM3                (ARC_FPGA_PERIPHERAL_BASE + 0x21000)
+#define CONFIG_SYS_NS16550_COM4                (ARC_FPGA_PERIPHERAL_BASE + 0x22000)
+#define CONFIG_SYS_NS16550_MEM32
+
+#define CONFIG_BAUDRATE                        115200
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C
+#define CONFIG_DW_I2C
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_ENV_EEPROM_BUS      2
+#define CONFIG_SYS_I2C_SPEED           100000
+#define CONFIG_SYS_I2C_SLAVE           0
+#define CONFIG_SYS_I2C_BASE            0xE001D000
+#define CONFIG_SYS_I2C_BASE1           0xE001E000
+#define CONFIG_SYS_I2C_BASE2           0xE001F000
+#define CONFIG_SYS_I2C_BUS_MAX         3
+#define IC_CLK                         50
+
+/*
+ * EEPROM configuration
+ */
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR             (0xA8 >> 1)
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN         1
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW    1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS      3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS  32
+
+/*
+ * SD/MMC configuration
+ */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DWMMC
+#define CONFIG_DOS_PARTITION
+
+/*
+ * Ethernet PHY configuration
+ */
+#define CONFIG_PHYLIB
+#define CONFIG_MII
+#define CONFIG_PHY_GIGE
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_DESIGNWARE_ETH
+#define CONFIG_DW_AUTONEG
+#define CONFIG_DW_SEARCH_PHY
+#define CONFIG_NET_MULTI
+
+/*
+ * Command line configuration
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_RARP
+
+#define CONFIG_OF_LIBFDT
+
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_MAXARGS             16
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_IS_IN_EEPROM
+#define CONFIG_ENV_SIZE                        0x00200         /* 512 bytes */
+#define CONFIG_ENV_OFFSET              0
+
+/*
+ * Environment configuration
+ */
+#define CONFIG_BOOTDELAY               3
+#define CONFIG_BOOTFILE                        "uImage"
+#define CONFIG_BOOTARGS                        "console=ttyS3,115200n8"
+#define CONFIG_LOADADDR                        CONFIG_SYS_LOAD_ADDR
+
+/*
+ * Console configuration
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT              "axs# "
+#define CONFIG_SYS_CBSIZE              256
+#define CONFIG_SYS_BARGSIZE            CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE + \
+                                               sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/*
+ * Misc utility configuration
+ */
+#define CONFIG_BOUNCE_BUFFER
+
+#endif /* _CONFIG_AXS101_H_ */