]> git.sur5r.net Git - u-boot/commitdiff
ARM: am335x: Add support for chiliSOM
authorMarcin Niestroj <m.niestroj@grinn-global.com>
Wed, 25 Jan 2017 08:53:07 +0000 (09:53 +0100)
committerTom Rini <trini@konsulko.com>
Sat, 28 Jan 2017 19:04:36 +0000 (14:04 -0500)
chiliSOM is a System On Module (http://http://grinn-global.com/chilisom/).
It can't exists on its own, but will be used as part of other boards.

Hardware specification:
 * TI AM335x processor
 * 128M, 256M or 512M DDR3 memory
 * up to 256M NAND

We place source inside arch/arm/mach-omap2/ directory and make it
possible to reuse initialization code (i.e. DDR, NAND init) for all
boards that use it.

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
arch/arm/include/asm/arch-am33xx/chilisom.h [new file with mode: 0644]
arch/arm/mach-omap2/am33xx/Kconfig
arch/arm/mach-omap2/am33xx/Makefile
arch/arm/mach-omap2/am33xx/chilisom.c [new file with mode: 0644]

diff --git a/arch/arm/include/asm/arch-am33xx/chilisom.h b/arch/arm/include/asm/arch-am33xx/chilisom.h
new file mode 100644 (file)
index 0000000..bd0016e
--- /dev/null
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2017 Grinn
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __ARCH_ARM_MACH_CHILISOM_SOM_H__
+#define __ARCH_ARM_MACH_CHILISOM_SOM_H__
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+void chilisom_enable_pin_mux(void);
+void chilisom_spl_board_init(void);
+#endif
+
+#endif
index ae1c3cf5edb41970071bb34270e393af5465184b..82e9541feff6b7a9ce8118a326d3ae72ec637690 100644 (file)
@@ -1,5 +1,9 @@
 if AM33XX
 
+config AM33XX_CHILISOM
+       bool
+       select SUPPORT_SPL
+
 choice
        prompt "AM33xx board select"
        optional
index 6fda4825fcecd9a224360c65e9f35479d5e35078..05cc8a11c5cbf644bd1d2c7ac5753d1c3559fedb 100644 (file)
@@ -20,3 +20,5 @@ obj-y += board.o
 obj-y  += mux.o
 
 obj-$(CONFIG_CLOCK_SYNTHESIZER)        += clk_synthesizer.o
+
+obj-$(CONFIG_AM33XX_CHILISOM) += chilisom.o
diff --git a/arch/arm/mach-omap2/am33xx/chilisom.c b/arch/arm/mach-omap2/am33xx/chilisom.c
new file mode 100644 (file)
index 0000000..a594f6c
--- /dev/null
@@ -0,0 +1,185 @@
+/*
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2017, Grinn - http://grinn-global.com/
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/clk_synthesizer.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/emif.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <i2c.h>
+#include <power/tps65217.h>
+#include <spl.h>
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+static struct module_pin_mux i2c0_pin_mux[] = {
+       {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
+                       PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
+       {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
+                       PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
+       {-1},
+};
+
+static struct module_pin_mux nand_pin_mux[] = {
+       {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)},   /* NAND AD0 */
+       {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)},   /* NAND AD1 */
+       {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)},   /* NAND AD2 */
+       {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)},   /* NAND AD3 */
+       {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)},   /* NAND AD4 */
+       {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)},   /* NAND AD5 */
+       {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)},   /* NAND AD6 */
+       {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)},   /* NAND AD7 */
+       {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
+       {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)},   /* NAND_WPN */
+       {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)},      /* NAND_CS0 */
+       {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
+       {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)},   /* NAND_OE */
+       {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)},       /* NAND_WEN */
+       {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)},  /* NAND_BE_CLE */
+       {-1},
+};
+
+static void enable_i2c0_pin_mux(void)
+{
+       configure_module_pin_mux(i2c0_pin_mux);
+}
+
+void chilisom_enable_pin_mux(void)
+{
+       /* chilisom pin mux */
+       configure_module_pin_mux(nand_pin_mux);
+}
+
+static const struct ddr_data ddr3_chilisom_data = {
+       .datardsratio0 = MT41K256M16HA125E_RD_DQS,
+       .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
+       .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
+       .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
+};
+
+static const struct cmd_control ddr3_chilisom_cmd_ctrl_data = {
+       .cmd0csratio = MT41K256M16HA125E_RATIO,
+       .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+       .cmd1csratio = MT41K256M16HA125E_RATIO,
+       .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+       .cmd2csratio = MT41K256M16HA125E_RATIO,
+       .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_chilisom_emif_reg_data = {
+       .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
+       .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
+       .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
+       .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
+       .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
+       .ocp_config = 0x00141414,
+       .zq_config = MT41K256M16HA125E_ZQ_CFG,
+       .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
+};
+
+void chilisom_spl_board_init(void)
+{
+       int mpu_vdd;
+       int usb_cur_lim;
+
+       enable_i2c0_pin_mux();
+
+       /* Get the frequency */
+       dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
+
+
+       if (i2c_probe(TPS65217_CHIP_PM))
+               return;
+
+       /*
+        * Increase USB current limit to 1300mA or 1800mA and set
+        * the MPU voltage controller as needed.
+        */
+       if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
+               usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
+               mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
+       } else {
+               usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
+               mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
+       }
+
+       if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
+                              TPS65217_POWER_PATH,
+                              usb_cur_lim,
+                              TPS65217_USB_INPUT_CUR_LIMIT_MASK))
+               puts("tps65217_reg_write failure\n");
+
+       /* Set DCDC3 (CORE) voltage to 1.125V */
+       if (tps65217_voltage_update(TPS65217_DEFDCDC3,
+                                   TPS65217_DCDC_VOLT_SEL_1125MV)) {
+               puts("tps65217_voltage_update failure\n");
+               return;
+       }
+       /* Set CORE Frequencies to OPP100 */
+       do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+
+       /* Set DCDC2 (MPU) voltage */
+       if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
+               puts("tps65217_voltage_update failure\n");
+               return;
+       }
+
+       /* Set LDO3 to 1.8V and LDO4 to 3.3V */
+       if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
+                              TPS65217_DEFLS1,
+                              TPS65217_LDO_VOLTAGE_OUT_1_8,
+                              TPS65217_LDO_MASK))
+               puts("tps65217_reg_write failure\n");
+
+       if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
+                              TPS65217_DEFLS2,
+                              TPS65217_LDO_VOLTAGE_OUT_3_3,
+                              TPS65217_LDO_MASK))
+               puts("tps65217_reg_write failure\n");
+
+       /* Set MPU Frequency to what we detected now that voltages are set */
+       do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
+}
+
+#define OSC    (V_OSCK/1000000)
+const struct dpll_params dpll_ddr_chilisom = {
+               400, OSC-1, 1, -1, -1, -1, -1};
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+       return &dpll_ddr_chilisom;
+}
+
+const struct ctrl_ioregs ioregs_chilisom = {
+       .cm0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
+       .cm1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
+       .cm2ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
+       .dt0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
+       .dt1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
+};
+
+void sdram_init(void)
+{
+       config_ddr(400, &ioregs_chilisom,
+                  &ddr3_chilisom_data,
+                  &ddr3_chilisom_cmd_ctrl_data,
+                  &ddr3_chilisom_emif_reg_data, 0);
+}
+
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */