RC=1
fi
+ OBJS=${output_dir}/u-boot
+ if [ -e ${output_dir}/spl/u-boot-spl ]; then
+ OBJS="${OBJS} ${output_dir}/spl/u-boot-spl"
+ fi
+
+ ${CROSS_COMPILE}size ${OBJS} | tee -a ${LOG_DIR}/$target.MAKELOG
+
if [ $BUILD_MANY == 1 ] ; then
trap - TERM
fi
fi
- OBJS=${output_dir}/u-boot
- if [ -e ${output_dir}/spl/u-boot-spl ]; then
- OBJS="${OBJS} ${output_dir}/spl/u-boot-spl"
- fi
-
- ${CROSS_COMPILE}size ${OBJS} | tee -a ${LOG_DIR}/$target.MAKELOG
-
[ -e "${LOG_DIR}/${target}.ERR" ] && cat "${LOG_DIR}/${target}.ERR"
touch "${donep}${build_idx}"
exists, unlike the similar options in the Linux kernel. Do not
set these options unless they apply!
+ NOTE: The following can be machine specific errata. These
+ do have ability to provide rudimentary version and machine
+ specific checks, but expect no product checks.
+ CONFIG_ARM_ERRATA_430973
+ CONFIG_ARM_ERRATA_454179
+ CONFIG_ARM_ERRATA_621766
+ CONFIG_ARM_ERRATA_798870
+
- Tegra SoC options:
CONFIG_TEGRA_SUPPORT_NON_SECURE
impossible actions will be skipped if the CPU is in NS mode,
such as ARM architectural timer initialization.
-- Driver Model
- Driver model is a new framework for devices in U-Boot
- introduced in early 2014. U-Boot is being progressively
- moved over to this. It offers a consistent device structure,
- supports grouping devices into classes and has built-in
- handling of platform data and device tree.
-
- To enable transition to driver model in a relatively
- painful fashion, each subsystem can be independently
- switched between the legacy/ad-hoc approach and the new
- driver model using the options below. Also, many uclass
- interfaces include compatibility features which may be
- removed once the conversion of that subsystem is complete.
- As a result, the API provided by the subsystem may in fact
- not change with driver model.
-
- See doc/driver-model/README.txt for more information.
-
- CONFIG_DM
-
- Enable driver model. This brings in the core support,
- including scanning of platform data on start-up. If
- CONFIG_OF_CONTROL is enabled, the device tree will be
- scanned also when available.
-
- CONFIG_CMD_DM
-
- Enable driver model test commands. These allow you to print
- out the driver model tree and the uclasses.
-
- CONFIG_DM_DEMO
-
- Enable some demo devices and the 'demo' command. These are
- really only useful for playing around while trying to
- understand driver model in sandbox.
-
- CONFIG_SPL_DM
-
- Enable driver model in SPL. You will need to provide a
- suitable malloc() implementation. If you are not using the
- full malloc() enabled by CONFIG_SYS_SPL_MALLOC_START,
- consider using CONFIG_SYS_MALLOC_SIMPLE. In that case you
- must provide CONFIG_SYS_MALLOC_F_LEN to set the size.
- In most cases driver model will only allocate a few uclasses
- and devices in SPL, so 1KB should be enable. See
- CONFIG_SYS_MALLOC_F_LEN for more details on how to enable
- it.
-
- CONFIG_DM_SERIAL
-
- Enable driver model for serial. This replaces
- drivers/serial/serial.c with the serial uclass, which
- implements serial_putc() etc. The uclass interface is
- defined in include/serial.h.
-
- CONFIG_DM_GPIO
-
- Enable driver model for GPIO access. The standard GPIO
- interface (gpio_get_value(), etc.) is then implemented by
- the GPIO uclass. Drivers provide methods to query the
- particular GPIOs that they provide. The uclass interface
- is defined in include/asm-generic/gpio.h.
-
- CONFIG_DM_SPI
-
- Enable driver model for SPI. The SPI slave interface
- (spi_setup_slave(), spi_xfer(), etc.) is then implemented by
- the SPI uclass. Drivers provide methods to access the SPI
- buses that they control. The uclass interface is defined in
- include/spi.h. The existing spi_slave structure is attached
- as 'parent data' to every slave on each bus. Slaves
- typically use driver-private data instead of extending the
- spi_slave structure.
-
- CONFIG_DM_SPI_FLASH
-
- Enable driver model for SPI flash. This SPI flash interface
- (spi_flash_probe(), spi_flash_write(), etc.) is then
- implemented by the SPI flash uclass. There is one standard
- SPI flash driver which knows how to probe most chips
- supported by U-Boot. The uclass interface is defined in
- include/spi_flash.h, but is currently fully compatible
- with the old interface to avoid confusion and duplication
- during the transition parent. SPI and SPI flash must be
- enabled together (it is not possible to use driver model
- for one and not the other).
-
- CONFIG_DM_CROS_EC
-
- Enable driver model for the Chrome OS EC interface. This
- allows the cros_ec SPI driver to operate with CONFIG_DM_SPI
- but otherwise makes few changes. Since cros_ec also supports
- I2C and LPC (which don't support driver model yet), a full
- conversion is not yet possible.
-
-
- ** Code size options: The following options are enabled by
- default except in SPL. Enable them explicitly to get these
- features in SPL.
-
- CONFIG_DM_WARN
-
- Enable the dm_warn() function. This can use up quite a bit
- of space for its strings.
-
- CONFIG_DM_STDIO
-
- Enable registering a serial device with the stdio library.
-
- CONFIG_DM_DEVICE_REMOVE
-
- Enable removing of devices.
-
- Linux Kernel Interface:
CONFIG_CLOCKS_IN_MHZ
obj-y += cache_v7.o
-obj-y += cpu.o
+obj-y += cpu.o cp15.o
obj-y += syslib.o
ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI),)
--- /dev/null
+/*
+ * (C) Copyright 2015 Texas Insturments
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * CP15 specific code
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/system.h>
+#include <asm/cache.h>
+#include <asm/armv7.h>
+#include <linux/compiler.h>
+
+void __weak v7_arch_cp15_set_l2aux_ctrl(u32 l2actlr, u32 cpu_midr,
+ u32 cpu_rev_comb, u32 cpu_variant,
+ u32 cpu_rev)
+{
+ asm volatile ("mcr p15, 1, %0, c15, c0, 0\n\t" : : "r"(l2actlr));
+}
+
+void __weak v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
+ u32 cpu_variant, u32 cpu_rev)
+{
+ asm volatile ("mcr p15, 0, %0, c1, c0, 1\n\t" : : "r"(acr));
+}
ifeq ($(CONFIG_OMAP34XX),)
obj-y += boot-common.o
-obj-y += lowlevel_init.o
endif
+obj-y += lowlevel_init.o
obj-y += mem-common.o
#include <asm/arch/spl.h>
#include <linux/linkage.h>
+#ifndef CONFIG_OMAP34XX
ENTRY(save_boot_params)
ldr r1, =OMAP_SRAM_SCRATCH_BOOT_PARAMS
str r0, [r1]
b save_boot_params_ret
ENDPROC(save_boot_params)
+#endif
-ENTRY(set_pl310_ctrl_reg)
- PUSH {r4-r11, lr} @ save registers - ROM code may pollute
+ENTRY(omap_smc1)
+ PUSH {r4-r12, lr} @ save registers - ROM code may pollute
@ our registers
- LDR r12, =0x102 @ Set PL310 control register - value in R0
- .word 0xe1600070 @ SMC #0 - hand assembled because -march=armv5
- @ call ROM Code API to set control register
- POP {r4-r11, pc}
-ENDPROC(set_pl310_ctrl_reg)
+ MOV r12, r0 @ Service
+ MOV r0, r1 @ Argument
+ DSB
+ DMB
+ .word 0xe1600070 @ SMC #0 - hand assembled for GCC versions
+ @ call ROM Code API for the service requested
+
+ POP {r4-r12, pc}
+ENDPROC(omap_smc1)
/* Declarations */
extern omap3_sysinfo sysinfo;
-static void omap3_setup_aux_cr(void);
#ifndef CONFIG_SYS_L2CACHE_OFF
static void omap3_invalidate_l2_cache_secure(void);
#endif
try_unlock_memory();
- /* Errata workarounds */
- omap3_setup_aux_cr();
-
#ifndef CONFIG_SYS_L2CACHE_OFF
/* Invalidate L2-cache from secure mode */
omap3_invalidate_l2_cache_secure();
do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
}
-static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits)
+void __weak omap3_set_aux_cr_secure(u32 acr)
{
- u32 acr;
-
- /* Read ACR */
- asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
- acr &= ~clear_bits;
- acr |= set_bits;
+ struct emu_hal_params emu_romcode_params;
- if (get_device_type() == GP_DEVICE) {
- omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_WRITE_ACR,
- acr);
- } else {
- struct emu_hal_params emu_romcode_params;
- emu_romcode_params.num_params = 1;
- emu_romcode_params.param1 = acr;
- omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
- (u32 *)&emu_romcode_params);
- }
+ emu_romcode_params.num_params = 1;
+ emu_romcode_params.param1 = acr;
+ omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
+ (u32 *)&emu_romcode_params);
}
-static void omap3_setup_aux_cr(void)
+void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
+ u32 cpu_variant, u32 cpu_rev)
{
- /* Workaround for Cortex-A8 errata: #454179 #430973
- * Set "IBE" bit
- * Set "Disable Branch Size Mispredicts" bit
- * Workaround for erratum #621766
- * Enable L1NEON bit
- * ACR |= (IBE | DBSM | L1NEON) => ACR |= 0xE0
- */
- omap3_update_aux_cr_secure(0xE0, 0);
+ /* Write ACR - affects secure banked bits */
+ if (get_device_type() == GP_DEVICE)
+ omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_ACR, acr);
+ else
+ omap3_set_aux_cr_secure(acr);
+
+ /* Write ACR - affects non-secure banked bits - some erratas need it */
+ asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
}
+
#ifndef CONFIG_SYS_L2CACHE_OFF
static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
{
asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
acr &= ~clear_bits;
acr |= set_bits;
+ v7_arch_cp15_set_acr(acr, 0, 0, 0, 0);
- /* Write ACR - affects non-secure banked bits */
- asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
}
/* Invalidate the entire L2 cache from secure mode */
static void omap3_invalidate_l2_cache_secure(void)
{
if (get_device_type() == GP_DEVICE) {
- omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_L2_INVAL,
- 0);
+ omap_smc1(OMAP3_GP_ROMCODE_API_L2_INVAL, 0);
} else {
struct emu_hal_params emu_romcode_params;
emu_romcode_params.num_params = 1;
void v7_outer_cache_enable(void)
{
- /* Set L2EN */
- omap3_update_aux_cr_secure(0x2, 0);
/*
+ * Set L2EN
* On some revisions L2EN bit is banked on some revisions it's not
* No harm in setting both banked bits(in fact this is required
* by an erratum)
void omap3_outer_cache_disable(void)
{
- /* Clear L2EN */
- omap3_update_aux_cr_secure(0, 0x2);
-
/*
+ * Clear L2EN
* On some revisions L2EN bit is banked on some revisions it's not
* No harm in clearing both banked bits(in fact this is required
* by an erratum)
ENDPROC(save_boot_params)
#endif
-ENTRY(omap3_gp_romcode_call)
- PUSH {r4-r12, lr} @ Save all registers from ROM code!
- MOV r12, r0 @ Copy the Service ID in R12
- MOV r0, r1 @ Copy parameter to R0
- mcr p15, 0, r0, c7, c10, 4 @ DSB
- mcr p15, 0, r0, c7, c10, 5 @ DMB
- .word 0xe1600070 @ SMC #0 to enter monitor - hand assembled
- @ because we use -march=armv5
- POP {r4-r12, pc}
-ENDPROC(omap3_gp_romcode_call)
-
/*
* Funtion for making PPA HAL API calls in secure devices
* Input:
#ifndef CONFIG_SYS_L2CACHE_OFF
void v7_outer_cache_enable(void)
{
- set_pl310_ctrl_reg(1);
+ omap_smc1(OMAP4_SERVICE_PL310_CONTROL_REG_SET, 1);
}
void v7_outer_cache_disable(void)
{
- set_pl310_ctrl_reg(0);
+ omap_smc1(OMAP4_SERVICE_PL310_CONTROL_REG_SET, 0);
}
#endif /* !CONFIG_SYS_L2CACHE_OFF */
(*ctrl)->control_emif2_sdram_config_ext);
}
+void init_cpu_configuration(void)
+{
+ u32 l2actlr;
+
+ asm volatile("mrc p15, 1, %0, c15, c0, 0" : "=r"(l2actlr));
+ /*
+ * L2ACTLR: Ensure to enable the following:
+ * 3: Disable clean/evict push to external
+ * 4: Disable WriteUnique and WriteLineUnique transactions from master
+ * 8: Disable DVM/CMO message broadcast
+ */
+ l2actlr |= 0x118;
+ omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2actlr);
+}
+
void init_omap_revision(void)
{
/*
default:
*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
}
+ init_cpu_configuration();
}
void reset_cpu(ulong ignored)
rst_val |= rst_time;
writel(rst_val, (*prcm)->prm_rsttime);
}
+
+void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
+ u32 cpu_rev_comb, u32 cpu_variant,
+ u32 cpu_rev)
+{
+ omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2auxctrl);
+}
mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
#endif
- mov pc, lr @ back to my caller
+ mov r5, lr @ Store my Caller
+ mrc p15, 0, r1, c0, c0, 0 @ r1 has Read Main ID Register (MIDR)
+ mov r3, r1, lsr #20 @ get variant field
+ and r3, r3, #0xf @ r3 has CPU variant
+ and r4, r1, #0xf @ r4 has CPU revision
+ mov r2, r3, lsl #4 @ shift variant field for combined value
+ orr r2, r4, r2 @ r2 has combined CPU variant + revision
+
+#ifdef CONFIG_ARM_ERRATA_798870
+ cmp r2, #0x30 @ Applies to lower than R3p0
+ bge skip_errata_798870 @ skip if not affected rev
+ cmp r2, #0x20 @ Applies to including and above R2p0
+ blt skip_errata_798870 @ skip if not affected rev
+
+ mrc p15, 1, r0, c15, c0, 0 @ read l2 aux ctrl reg
+ orr r0, r0, #1 << 7 @ Enable hazard-detect timeout
+ push {r1-r5} @ Save the cpu info registers
+ bl v7_arch_cp15_set_l2aux_ctrl
+ isb @ Recommended ISB after l2actlr update
+ pop {r1-r5} @ Restore the cpu info - fall through
+skip_errata_798870:
+#endif
+
+#ifdef CONFIG_ARM_ERRATA_454179
+ cmp r2, #0x21 @ Only on < r2p1
+ bge skip_errata_454179
+
+ mrc p15, 0, r0, c1, c0, 1 @ Read ACR
+ orr r0, r0, #(0x3 << 6) @ Set DBSM(BIT7) and IBE(BIT6) bits
+ push {r1-r5} @ Save the cpu info registers
+ bl v7_arch_cp15_set_acr
+ pop {r1-r5} @ Restore the cpu info - fall through
+
+skip_errata_454179:
+#endif
+
+#ifdef CONFIG_ARM_ERRATA_430973
+ cmp r2, #0x21 @ Only on < r2p1
+ bge skip_errata_430973
+
+ mrc p15, 0, r0, c1, c0, 1 @ Read ACR
+ orr r0, r0, #(0x1 << 6) @ Set IBE bit
+ push {r1-r5} @ Save the cpu info registers
+ bl v7_arch_cp15_set_acr
+ pop {r1-r5} @ Restore the cpu info - fall through
+
+skip_errata_430973:
+#endif
+
+#ifdef CONFIG_ARM_ERRATA_621766
+ cmp r2, #0x21 @ Only on < r2p1
+ bge skip_errata_621766
+
+ mrc p15, 0, r0, c1, c0, 1 @ Read ACR
+ orr r0, r0, #(0x1 << 5) @ Set L1NEON bit
+ push {r1-r5} @ Save the cpu info registers
+ bl v7_arch_cp15_set_acr
+ pop {r1-r5} @ Restore the cpu info - fall through
+
+skip_errata_621766:
+#endif
+
+ mov pc, r5 @ back to my caller
ENDPROC(cpu_init_cp15)
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
--- /dev/null
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <x0khasim@ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _OMAP3_H_
+#define _OMAP3_H_
+
+/* Stuff on L3 Interconnect */
+#define SMX_APE_BASE 0x68000000
+
+/* GPMC */
+#define OMAP34XX_GPMC_BASE 0x6E000000
+
+/* SMS */
+#define OMAP34XX_SMS_BASE 0x6C000000
+
+/* SDRC */
+#define OMAP34XX_SDRC_BASE 0x6D000000
+
+/*
+ * L4 Peripherals - L4 Wakeup and L4 Core now
+ */
+#define OMAP34XX_CORE_L4_IO_BASE 0x48000000
+#define OMAP34XX_WAKEUP_L4_IO_BASE 0x48300000
+#define OMAP34XX_ID_L4_IO_BASE 0x4830A200
+#define OMAP34XX_L4_PER 0x49000000
+#define OMAP34XX_L4_IO_BASE OMAP34XX_CORE_L4_IO_BASE
+
+/* DMA4/SDMA */
+#define OMAP34XX_DMA4_BASE 0x48056000
+
+/* CONTROL */
+#define OMAP34XX_CTRL_BASE (OMAP34XX_L4_IO_BASE + 0x2000)
+
+#ifndef __ASSEMBLY__
+/* Signal Integrity Parameter Control Registers */
+struct control_prog_io {
+ unsigned char res[0x408];
+ unsigned int io2; /* 0x408 */
+ unsigned char res2[0x38];
+ unsigned int io0; /* 0x444 */
+ unsigned int io1; /* 0x448 */
+};
+#endif /* __ASSEMBLY__ */
+
+/* Bit definition for CONTROL_PROG_IO1 */
+#define PRG_I2C2_PULLUPRESX 0x00000001
+
+/* UART */
+#define OMAP34XX_UART1 (OMAP34XX_L4_IO_BASE + 0x6a000)
+#define OMAP34XX_UART2 (OMAP34XX_L4_IO_BASE + 0x6c000)
+#define OMAP34XX_UART3 (OMAP34XX_L4_PER + 0x20000)
+#define OMAP34XX_UART4 (OMAP34XX_L4_PER + 0x42000)
+
+/* General Purpose Timers */
+#define OMAP34XX_GPT1 0x48318000
+#define OMAP34XX_GPT2 0x49032000
+#define OMAP34XX_GPT3 0x49034000
+#define OMAP34XX_GPT4 0x49036000
+#define OMAP34XX_GPT5 0x49038000
+#define OMAP34XX_GPT6 0x4903A000
+#define OMAP34XX_GPT7 0x4903C000
+#define OMAP34XX_GPT8 0x4903E000
+#define OMAP34XX_GPT9 0x49040000
+#define OMAP34XX_GPT10 0x48086000
+#define OMAP34XX_GPT11 0x48088000
+#define OMAP34XX_GPT12 0x48304000
+
+/* WatchDog Timers (1 secure, 3 GP) */
+#define WD1_BASE 0x4830C000
+#define WD2_BASE 0x48314000
+#define WD3_BASE 0x49030000
+
+/* 32KTIMER */
+#define SYNC_32KTIMER_BASE 0x48320000
+
+#ifndef __ASSEMBLY__
+
+struct s32ktimer {
+ unsigned char res[0x10];
+ unsigned int s32k_cr; /* 0x10 */
+};
+
+#endif /* __ASSEMBLY__ */
+
+#ifndef __ASSEMBLY__
+struct gpio {
+ unsigned char res1[0x34];
+ unsigned int oe; /* 0x34 */
+ unsigned int datain; /* 0x38 */
+ unsigned char res2[0x54];
+ unsigned int cleardataout; /* 0x90 */
+ unsigned int setdataout; /* 0x94 */
+};
+#endif /* __ASSEMBLY__ */
+
+#define GPIO0 (0x1 << 0)
+#define GPIO1 (0x1 << 1)
+#define GPIO2 (0x1 << 2)
+#define GPIO3 (0x1 << 3)
+#define GPIO4 (0x1 << 4)
+#define GPIO5 (0x1 << 5)
+#define GPIO6 (0x1 << 6)
+#define GPIO7 (0x1 << 7)
+#define GPIO8 (0x1 << 8)
+#define GPIO9 (0x1 << 9)
+#define GPIO10 (0x1 << 10)
+#define GPIO11 (0x1 << 11)
+#define GPIO12 (0x1 << 12)
+#define GPIO13 (0x1 << 13)
+#define GPIO14 (0x1 << 14)
+#define GPIO15 (0x1 << 15)
+#define GPIO16 (0x1 << 16)
+#define GPIO17 (0x1 << 17)
+#define GPIO18 (0x1 << 18)
+#define GPIO19 (0x1 << 19)
+#define GPIO20 (0x1 << 20)
+#define GPIO21 (0x1 << 21)
+#define GPIO22 (0x1 << 22)
+#define GPIO23 (0x1 << 23)
+#define GPIO24 (0x1 << 24)
+#define GPIO25 (0x1 << 25)
+#define GPIO26 (0x1 << 26)
+#define GPIO27 (0x1 << 27)
+#define GPIO28 (0x1 << 28)
+#define GPIO29 (0x1 << 29)
+#define GPIO30 (0x1 << 30)
+#define GPIO31 (0x1 << 31)
+
+/* base address for indirect vectors (internal boot mode) */
+#define SRAM_OFFSET0 0x40000000
+#define SRAM_OFFSET1 0x00200000
+#define SRAM_OFFSET2 0x0000F800
+#define SRAM_VECT_CODE (SRAM_OFFSET0 | SRAM_OFFSET1 | \
+ SRAM_OFFSET2)
+#define SRAM_CLK_CODE (SRAM_VECT_CODE + 64)
+
+#define NON_SECURE_SRAM_START 0x40208000 /* Works for GP & EMU */
+#define NON_SECURE_SRAM_END 0x40210000
+
+#define LOW_LEVEL_SRAM_STACK 0x4020FFFC
+
+/* scratch area - accessible on both EMU and GP */
+#define OMAP3_PUBLIC_SRAM_SCRATCH_AREA NON_SECURE_SRAM_START
+
+#define DEBUG_LED1 149 /* gpio */
+#define DEBUG_LED2 150 /* gpio */
+
+#define XDR_POP 5 /* package on package part */
+#define SDR_DISCRETE 4 /* 128M memory SDR module */
+#define DDR_STACKED 3 /* stacked part on 2422 */
+#define DDR_COMBO 2 /* combo part on cpu daughter card */
+#define DDR_DISCRETE 1 /* 2x16 parts on daughter card */
+
+#define DDR_100 100 /* type found on most mem d-boards */
+#define DDR_111 111 /* some combo parts */
+#define DDR_133 133 /* most combo, some mem d-boards */
+#define DDR_165 165 /* future parts */
+
+#define CPU_3430 0x3430
+
+/*
+ * 343x real hardware:
+ * ES1 = rev 0
+ *
+ * ES2 onwards, the value maps to contents of IDCODE register [31:28].
+ *
+ * Note : CPU_3XX_ES20 is used in cache.S. Please review before changing.
+ */
+#define CPU_3XX_ES10 0
+#define CPU_3XX_ES20 1
+#define CPU_3XX_ES21 2
+#define CPU_3XX_ES30 3
+#define CPU_3XX_ES31 4
+#define CPU_3XX_ES312 7
+#define CPU_3XX_MAX_REV 8
+
+/*
+ * 37xx real hardware:
+ * ES1.0 onwards, the value maps to contents of IDCODE register [31:28].
+ */
+
+#define CPU_37XX_ES10 0
+#define CPU_37XX_ES11 1
+#define CPU_37XX_ES12 2
+#define CPU_37XX_MAX_REV 3
+
+#define CPU_3XX_ID_SHIFT 28
+
+#define WIDTH_8BIT 0x0000
+#define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */
+
+/*
+ * Hawkeye values
+ */
+#define HAWKEYE_OMAP34XX 0xb7ae
+#define HAWKEYE_AM35XX 0xb868
+#define HAWKEYE_OMAP36XX 0xb891
+
+#define HAWKEYE_SHIFT 12
+
+/*
+ * Define CPU families
+ */
+#define CPU_OMAP34XX 0x3400 /* OMAP34xx/OMAP35 devices */
+#define CPU_AM35XX 0x3500 /* AM35xx devices */
+#define CPU_OMAP36XX 0x3600 /* OMAP36xx devices */
+
+/*
+ * Control status register values corresponding to cpu variants
+ */
+#define OMAP3503 0x5c00
+#define OMAP3515 0x1c00
+#define OMAP3525 0x4c00
+#define OMAP3530 0x0c00
+
+#define AM3505 0x5c00
+#define AM3517 0x1c00
+
+#define OMAP3730 0x0c00
+
+/*
+ * ROM code API related flags
+ */
+#define OMAP3_GP_ROMCODE_API_L2_INVAL 1
+#define OMAP3_GP_ROMCODE_API_WRITE_ACR 3
+
+/*
+ * EMU device PPA HAL related flags
+ */
+#define OMAP3_EMU_HAL_API_L2_INVAL 40
+#define OMAP3_EMU_HAL_API_WRITE_ACR 42
+
+#define OMAP3_EMU_HAL_START_HAL_CRITICAL 4
+
+/* ABB settings */
+#define OMAP_ABB_SETTLING_TIME 30
+#define OMAP_ABB_CLOCK_CYCLES 8
+
+/* ABB tranxdone mask */
+#define OMAP_ABB_MPU_TXDONE_MASK (0x1 << 26)
+
+#endif
+++ /dev/null
-/*
- * (C) Copyright 2006-2008
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Mohammed Khasim <x0khasim@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _OMAP3_H_
-#define _OMAP3_H_
-
-/* Stuff on L3 Interconnect */
-#define SMX_APE_BASE 0x68000000
-
-/* GPMC */
-#define OMAP34XX_GPMC_BASE 0x6E000000
-
-/* SMS */
-#define OMAP34XX_SMS_BASE 0x6C000000
-
-/* SDRC */
-#define OMAP34XX_SDRC_BASE 0x6D000000
-
-/*
- * L4 Peripherals - L4 Wakeup and L4 Core now
- */
-#define OMAP34XX_CORE_L4_IO_BASE 0x48000000
-#define OMAP34XX_WAKEUP_L4_IO_BASE 0x48300000
-#define OMAP34XX_ID_L4_IO_BASE 0x4830A200
-#define OMAP34XX_L4_PER 0x49000000
-#define OMAP34XX_L4_IO_BASE OMAP34XX_CORE_L4_IO_BASE
-
-/* DMA4/SDMA */
-#define OMAP34XX_DMA4_BASE 0x48056000
-
-/* CONTROL */
-#define OMAP34XX_CTRL_BASE (OMAP34XX_L4_IO_BASE + 0x2000)
-
-#ifndef __ASSEMBLY__
-/* Signal Integrity Parameter Control Registers */
-struct control_prog_io {
- unsigned char res[0x408];
- unsigned int io2; /* 0x408 */
- unsigned char res2[0x38];
- unsigned int io0; /* 0x444 */
- unsigned int io1; /* 0x448 */
-};
-#endif /* __ASSEMBLY__ */
-
-/* Bit definition for CONTROL_PROG_IO1 */
-#define PRG_I2C2_PULLUPRESX 0x00000001
-
-/* UART */
-#define OMAP34XX_UART1 (OMAP34XX_L4_IO_BASE + 0x6a000)
-#define OMAP34XX_UART2 (OMAP34XX_L4_IO_BASE + 0x6c000)
-#define OMAP34XX_UART3 (OMAP34XX_L4_PER + 0x20000)
-#define OMAP34XX_UART4 (OMAP34XX_L4_PER + 0x42000)
-
-/* General Purpose Timers */
-#define OMAP34XX_GPT1 0x48318000
-#define OMAP34XX_GPT2 0x49032000
-#define OMAP34XX_GPT3 0x49034000
-#define OMAP34XX_GPT4 0x49036000
-#define OMAP34XX_GPT5 0x49038000
-#define OMAP34XX_GPT6 0x4903A000
-#define OMAP34XX_GPT7 0x4903C000
-#define OMAP34XX_GPT8 0x4903E000
-#define OMAP34XX_GPT9 0x49040000
-#define OMAP34XX_GPT10 0x48086000
-#define OMAP34XX_GPT11 0x48088000
-#define OMAP34XX_GPT12 0x48304000
-
-/* WatchDog Timers (1 secure, 3 GP) */
-#define WD1_BASE 0x4830C000
-#define WD2_BASE 0x48314000
-#define WD3_BASE 0x49030000
-
-/* 32KTIMER */
-#define SYNC_32KTIMER_BASE 0x48320000
-
-#ifndef __ASSEMBLY__
-
-struct s32ktimer {
- unsigned char res[0x10];
- unsigned int s32k_cr; /* 0x10 */
-};
-
-#endif /* __ASSEMBLY__ */
-
-#ifndef __ASSEMBLY__
-struct gpio {
- unsigned char res1[0x34];
- unsigned int oe; /* 0x34 */
- unsigned int datain; /* 0x38 */
- unsigned char res2[0x54];
- unsigned int cleardataout; /* 0x90 */
- unsigned int setdataout; /* 0x94 */
-};
-#endif /* __ASSEMBLY__ */
-
-#define GPIO0 (0x1 << 0)
-#define GPIO1 (0x1 << 1)
-#define GPIO2 (0x1 << 2)
-#define GPIO3 (0x1 << 3)
-#define GPIO4 (0x1 << 4)
-#define GPIO5 (0x1 << 5)
-#define GPIO6 (0x1 << 6)
-#define GPIO7 (0x1 << 7)
-#define GPIO8 (0x1 << 8)
-#define GPIO9 (0x1 << 9)
-#define GPIO10 (0x1 << 10)
-#define GPIO11 (0x1 << 11)
-#define GPIO12 (0x1 << 12)
-#define GPIO13 (0x1 << 13)
-#define GPIO14 (0x1 << 14)
-#define GPIO15 (0x1 << 15)
-#define GPIO16 (0x1 << 16)
-#define GPIO17 (0x1 << 17)
-#define GPIO18 (0x1 << 18)
-#define GPIO19 (0x1 << 19)
-#define GPIO20 (0x1 << 20)
-#define GPIO21 (0x1 << 21)
-#define GPIO22 (0x1 << 22)
-#define GPIO23 (0x1 << 23)
-#define GPIO24 (0x1 << 24)
-#define GPIO25 (0x1 << 25)
-#define GPIO26 (0x1 << 26)
-#define GPIO27 (0x1 << 27)
-#define GPIO28 (0x1 << 28)
-#define GPIO29 (0x1 << 29)
-#define GPIO30 (0x1 << 30)
-#define GPIO31 (0x1 << 31)
-
-/* base address for indirect vectors (internal boot mode) */
-#define SRAM_OFFSET0 0x40000000
-#define SRAM_OFFSET1 0x00200000
-#define SRAM_OFFSET2 0x0000F800
-#define SRAM_VECT_CODE (SRAM_OFFSET0 | SRAM_OFFSET1 | \
- SRAM_OFFSET2)
-#define SRAM_CLK_CODE (SRAM_VECT_CODE + 64)
-
-#define NON_SECURE_SRAM_START 0x40208000 /* Works for GP & EMU */
-#define NON_SECURE_SRAM_END 0x40210000
-
-#define LOW_LEVEL_SRAM_STACK 0x4020FFFC
-
-/* scratch area - accessible on both EMU and GP */
-#define OMAP3_PUBLIC_SRAM_SCRATCH_AREA NON_SECURE_SRAM_START
-
-#define DEBUG_LED1 149 /* gpio */
-#define DEBUG_LED2 150 /* gpio */
-
-#define XDR_POP 5 /* package on package part */
-#define SDR_DISCRETE 4 /* 128M memory SDR module */
-#define DDR_STACKED 3 /* stacked part on 2422 */
-#define DDR_COMBO 2 /* combo part on cpu daughter card */
-#define DDR_DISCRETE 1 /* 2x16 parts on daughter card */
-
-#define DDR_100 100 /* type found on most mem d-boards */
-#define DDR_111 111 /* some combo parts */
-#define DDR_133 133 /* most combo, some mem d-boards */
-#define DDR_165 165 /* future parts */
-
-#define CPU_3430 0x3430
-
-/*
- * 343x real hardware:
- * ES1 = rev 0
- *
- * ES2 onwards, the value maps to contents of IDCODE register [31:28].
- *
- * Note : CPU_3XX_ES20 is used in cache.S. Please review before changing.
- */
-#define CPU_3XX_ES10 0
-#define CPU_3XX_ES20 1
-#define CPU_3XX_ES21 2
-#define CPU_3XX_ES30 3
-#define CPU_3XX_ES31 4
-#define CPU_3XX_ES312 7
-#define CPU_3XX_MAX_REV 8
-
-/*
- * 37xx real hardware:
- * ES1.0 onwards, the value maps to contents of IDCODE register [31:28].
- */
-
-#define CPU_37XX_ES10 0
-#define CPU_37XX_ES11 1
-#define CPU_37XX_ES12 2
-#define CPU_37XX_MAX_REV 3
-
-#define CPU_3XX_ID_SHIFT 28
-
-#define WIDTH_8BIT 0x0000
-#define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */
-
-/*
- * Hawkeye values
- */
-#define HAWKEYE_OMAP34XX 0xb7ae
-#define HAWKEYE_AM35XX 0xb868
-#define HAWKEYE_OMAP36XX 0xb891
-
-#define HAWKEYE_SHIFT 12
-
-/*
- * Define CPU families
- */
-#define CPU_OMAP34XX 0x3400 /* OMAP34xx/OMAP35 devices */
-#define CPU_AM35XX 0x3500 /* AM35xx devices */
-#define CPU_OMAP36XX 0x3600 /* OMAP36xx devices */
-
-/*
- * Control status register values corresponding to cpu variants
- */
-#define OMAP3503 0x5c00
-#define OMAP3515 0x1c00
-#define OMAP3525 0x4c00
-#define OMAP3530 0x0c00
-
-#define AM3505 0x5c00
-#define AM3517 0x1c00
-
-#define OMAP3730 0x0c00
-
-/*
- * ROM code API related flags
- */
-#define OMAP3_GP_ROMCODE_API_L2_INVAL 1
-#define OMAP3_GP_ROMCODE_API_WRITE_ACR 3
-
-/*
- * EMU device PPA HAL related flags
- */
-#define OMAP3_EMU_HAL_API_L2_INVAL 40
-#define OMAP3_EMU_HAL_API_WRITE_ACR 42
-
-#define OMAP3_EMU_HAL_START_HAL_CRITICAL 4
-
-/* ABB settings */
-#define OMAP_ABB_SETTLING_TIME 30
-#define OMAP_ABB_CLOCK_CYCLES 8
-
-/* ABB tranxdone mask */
-#define OMAP_ABB_MPU_TXDONE_MASK (0x1 << 26)
-
-#endif
void dieid_num_r(void);
void get_dieid(u32 *id);
void do_omap3_emu_romcode_call(u32 service_id, u32 parameters);
-void omap3_gp_romcode_call(u32 service_id, u32 parameter);
+void omap3_set_aux_cr_secure(u32 acr);
u32 warm_reset(void);
#endif
void set_muxconf_regs_essential(void);
u32 wait_on_value(u32, u32, void *, u32);
void sdelay(unsigned long);
-void set_pl310_ctrl_reg(u32 val);
void setup_clocks_for_console(void);
void prcm_init(void);
void bypass_dpll(u32 const base);
u32 warm_reset(void);
void force_emif_self_refresh(void);
void setup_warmreset_time(void);
+
+#define OMAP4_SERVICE_PL310_CONTROL_REG_SET 0x102
+
#endif
{
return div_round_up(32768 * usec, 1000000);
}
+
+#define OMAP5_SERVICE_L2ACTLR_SET 0x104
+
#endif
#endif /* CONFIG_ARMV7_NONSEC || CONFIG_ARMV7_VIRT */
+void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
+ u32 cpu_rev_comb, u32 cpu_variant,
+ u32 cpu_rev);
+void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
+ u32 cpu_variant, u32 cpu_rev);
#endif /* ! __ASSEMBLY__ */
#endif
void usb_fake_mac_from_die_id(u32 *id);
+void omap_smc1(u32 service, u32 val);
+
/* ABB */
#define OMAP_ABB_NOMINAL_OPP 0
#define OMAP_ABB_FAST_OPP 1
do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
}
+void omap3_set_aux_cr_secure(u32 acr)
+{
+ struct emu_hal_params_rx51 emu_romcode_params = { 0, };
+
+ emu_romcode_params.num_params = 2;
+ emu_romcode_params.param1 = acr;
+
+ omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
+ (u32 *)&emu_romcode_params);
+}
+
/*
* Routine: omap3_update_aux_cr_secure_rx51
* Description: Modify the contents Auxiliary Control Register.
*/
static void omap3_update_aux_cr_secure_rx51(u32 set_bits, u32 clear_bits)
{
- struct emu_hal_params_rx51 emu_romcode_params = { 0, };
u32 acr;
/* Read ACR */
asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
acr &= ~clear_bits;
acr |= set_bits;
-
- emu_romcode_params.num_params = 2;
- emu_romcode_params.param1 = acr;
-
- omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
- (u32 *)&emu_romcode_params);
+ omap3_set_aux_cr_secure(acr);
}
/*
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPC(3),USB_EHCI"
CONFIG_FDTFILE="sun4i-a10-olinuxino-lime.dtb"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN4I=y
-+S:CONFIG_DRAM_CLK=480
-+S:CONFIG_DRAM_ZQ=123
-+S:CONFIG_DRAM_EMR1=4
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN4I=y
+CONFIG_DRAM_CLK=480
+CONFIG_DRAM_ZQ=123
+CONFIG_DRAM_EMR1=4
CONFIG_FDTFILE="sun5i-a10s-olinuxino-micro.dtb"
CONFIG_MMC_SUNXI_SLOT_EXTRA=1
CONFIG_USB1_VBUS_PIN="PB10"
-+S:CONFIG_MMC0_CD_PIN="PG1"
-+S:CONFIG_MMC1_CD_PIN="PG13"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN5I=y
-+S:CONFIG_DRAM_CLK=432
-+S:CONFIG_DRAM_ZQ=123
-+S:CONFIG_DRAM_EMR1=4
+CONFIG_MMC0_CD_PIN="PG1"
+CONFIG_MMC1_CD_PIN="PG13"
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN5I=y
+CONFIG_DRAM_CLK=432
+CONFIG_DRAM_ZQ=123
+CONFIG_DRAM_EMR1=4
CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:3,vmode:0"
CONFIG_VIDEO_LCD_POWER="PB10"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN5I=y
-+S:CONFIG_DRAM_CLK=408
-+S:CONFIG_DRAM_ZQ=123
-+S:CONFIG_DRAM_EMR1=0
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN5I=y
+CONFIG_DRAM_CLK=408
+CONFIG_DRAM_ZQ=123
+CONFIG_DRAM_EMR1=0
CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:3,vmode:0"
CONFIG_VIDEO_LCD_POWER="AXP0-0"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN5I=y
-+S:CONFIG_DRAM_CLK=408
-+S:CONFIG_DRAM_ZQ=123
-+S:CONFIG_DRAM_EMR1=0
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN5I=y
+CONFIG_DRAM_CLK=408
+CONFIG_DRAM_ZQ=123
+CONFIG_DRAM_EMR1=0
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPC(3),USB_EHCI"
CONFIG_FDTFILE="sun7i-a20-olinuxino-lime2.dtb"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN7I=y
-+S:CONFIG_DRAM_CLK=480
-+S:CONFIG_DRAM_ZQ=127
-+S:CONFIG_DRAM_EMR1=4
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN7I=y
+CONFIG_DRAM_CLK=480
+CONFIG_DRAM_ZQ=127
+CONFIG_DRAM_EMR1=4
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPC(3),USB_EHCI"
CONFIG_FDTFILE="sun7i-a20-olinuxino-lime.dtb"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN7I=y
-+S:CONFIG_DRAM_CLK=480
-+S:CONFIG_DRAM_ZQ=127
-+S:CONFIG_DRAM_EMR1=4
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN7I=y
+CONFIG_DRAM_CLK=480
+CONFIG_DRAM_ZQ=127
+CONFIG_DRAM_EMR1=4
CONFIG_FDTFILE="sun7i-a20-olinuxino-micro.dtb"
CONFIG_MMC_SUNXI_SLOT_EXTRA=3
CONFIG_VIDEO_VGA=y
-+S:CONFIG_MMC0_CD_PIN="PH1"
-+S:CONFIG_MMC3_CD_PIN="PH11"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN7I=y
-+S:CONFIG_DRAM_CLK=384
-+S:CONFIG_DRAM_ZQ=127
-+S:CONFIG_DRAM_EMR1=4
+CONFIG_MMC0_CD_PIN="PH1"
+CONFIG_MMC3_CD_PIN="PH11"
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN7I=y
+CONFIG_DRAM_CLK=384
+CONFIG_DRAM_ZQ=127
+CONFIG_DRAM_EMR1=4
CONFIG_VIDEO_LCD_POWER="AXP0-0"
CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN5I=y
-+S:CONFIG_DRAM_CLK=432
-+S:CONFIG_DRAM_ZQ=123
-+S:CONFIG_DRAM_EMR1=4
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN5I=y
+CONFIG_DRAM_CLK=432
+CONFIG_DRAM_ZQ=123
+CONFIG_DRAM_EMR1=4
CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER,USB_EHCI"
CONFIG_FDTFILE="sun5i-a10s-auxtek-t004.dtb"
CONFIG_USB1_VBUS_PIN="PG13"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN5I=y
-+S:CONFIG_DRAM_CLK=432
-+S:CONFIG_DRAM_ZQ=123
-+S:CONFIG_DRAM_EMR1=4
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN5I=y
+CONFIG_DRAM_CLK=432
+CONFIG_DRAM_ZQ=123
+CONFIG_DRAM_EMR1=4
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_B4420,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_B4860QDS=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_B4860QDS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_B4860QDS=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_B4860QDS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,NAND,SYS_CLK_100"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_BSC9131RDB=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_BSC9131RDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,NAND"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_BSC9131RDB=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_BSC9131RDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND,SYS_CLK_100_DDR_100"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_BSC9132QDS=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_BSC9132QDS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND,SYS_CLK_100_DDR_133"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_BSC9132QDS=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_BSC9132QDS=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI,USB_EHCI"
CONFIG_FDTFILE="sun7i-a20-bananapi.dtb"
CONFIG_GMAC_TX_DELAY=3
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN7I=y
-+S:CONFIG_DRAM_CLK=432
-+S:CONFIG_DRAM_ZQ=127
-+S:CONFIG_DRAM_EMR1=4
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN7I=y
+CONFIG_DRAM_CLK=432
+CONFIG_DRAM_ZQ=127
+CONFIG_DRAM_EMR1=4
CONFIG_USB1_VBUS_PIN="PH0"
CONFIG_USB2_VBUS_PIN="PH1"
CONFIG_GMAC_TX_DELAY=3
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN7I=y
-+S:CONFIG_DRAM_CLK=432
-+S:CONFIG_DRAM_ZQ=127
-+S:CONFIG_DRAM_EMR1=4
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN7I=y
+CONFIG_DRAM_CLK=432
+CONFIG_DRAM_ZQ=127
+CONFIG_DRAM_EMR1=4
CONFIG_SPL=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,NAND"
-+ST:CONFIG_PPC=y
-+ST:CONFIG_MPC85xx=y
-+ST:CONFIG_TARGET_C29XPCIE=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_C29XPCIE=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI,SUNXI_GMAC"
CONFIG_FDTFILE="sun6i-a31s-cs908.dtb"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN6I=y
-+S:CONFIG_DRAM_CLK=432
-+S:CONFIG_DRAM_ZQ=123
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN6I=y
+CONFIG_DRAM_CLK=432
+CONFIG_DRAM_ZQ=123
# Ethernet phy power
-+S:CONFIG_AXP221_DLDO1_VOLT=3300
+CONFIG_AXP221_DLDO1_VOLT=3300
# Wifi power
-+S:CONFIG_AXP221_ALDO1_VOLT=3300
+CONFIG_AXP221_ALDO1_VOLT=3300
# No Vbus gpio for either usb
-+S:CONFIG_USB1_VBUS_PIN=""
-+S:CONFIG_USB2_VBUS_PIN=""
+CONFIG_USB1_VBUS_PIN=""
+CONFIG_USB2_VBUS_PIN=""
CONFIG_VIDEO_LCD_SPI_SCLK="PA1"
CONFIG_VIDEO_LCD_SPI_MOSI="PA2"
CONFIG_VIDEO_LCD_PANEL_HITACHI_TX18D42VM=y
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN4I=y
-+S:CONFIG_DRAM_CLK=408
-+S:CONFIG_DRAM_ZQ=123
-+S:CONFIG_DRAM_EMR1=4
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN4I=y
+CONFIG_DRAM_CLK=408
+CONFIG_DRAM_ZQ=123
+CONFIG_DRAM_EMR1=4
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI,SUNXI_GMAC"
CONFIG_FDTFILE="sun6i-a31-colombus.dtb"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN6I=y
-+S:CONFIG_DRAM_CLK=240
-+S:CONFIG_DRAM_ZQ=251
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN6I=y
+CONFIG_DRAM_CLK=240
+CONFIG_DRAM_ZQ=251
# Wifi power
-+S:CONFIG_AXP221_ALDO1_VOLT=3300
+CONFIG_AXP221_ALDO1_VOLT=3300
# No Vbus gpio for usb1
-+S:CONFIG_USB1_VBUS_PIN=""
+CONFIG_USB1_VBUS_PIN=""
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8),USB_EHCI"
CONFIG_FDTFILE="sun7i-a20-cubieboard2.dtb"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN7I=y
-+S:CONFIG_DRAM_CLK=480
-+S:CONFIG_DRAM_ZQ=127
-+S:CONFIG_DRAM_EMR1=4
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN7I=y
+CONFIG_DRAM_CLK=480
+CONFIG_DRAM_ZQ=127
+CONFIG_DRAM_EMR1=4
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPB(8),USB_EHCI"
CONFIG_FDTFILE="sun4i-a10-cubieboard.dtb"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN4I=y
-+S:CONFIG_DRAM_CLK=480
-+S:CONFIG_DRAM_ZQ=123
-+S:CONFIG_DRAM_EMR1=0
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN4I=y
+CONFIG_DRAM_CLK=480
+CONFIG_DRAM_ZQ=123
+CONFIG_DRAM_EMR1=0
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(12),USB_EHCI"
CONFIG_FDTFILE="sun7i-a20-cubietruck.dtb"
CONFIG_VIDEO_VGA=y
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN7I=y
-+S:CONFIG_DRAM_CLK=432
-+S:CONFIG_DRAM_ZQ=127
-+S:CONFIG_DRAM_EMR1=4
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN7I=y
+CONFIG_DRAM_CLK=432
+CONFIG_DRAM_ZQ=127
+CONFIG_DRAM_EMR1=4
CONFIG_FDTFILE="sun6i-a31-hummingbird.dtb"
CONFIG_VIDEO_VGA_VIA_LCD=y
CONFIG_VIDEO_VGA_EXTERNAL_DAC_EN="PH25"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN6I=y
-+S:CONFIG_DRAM_CLK=312
-+S:CONFIG_DRAM_ZQ=251
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN6I=y
+CONFIG_DRAM_CLK=312
+CONFIG_DRAM_ZQ=251
# Wifi power
-+S:CONFIG_AXP221_ALDO1_VOLT=3300
+CONFIG_AXP221_ALDO1_VOLT=3300
# Vbus gpio for usb1
-+S:CONFIG_USB1_VBUS_PIN="PH24"
+CONFIG_USB1_VBUS_PIN="PH24"
# No Vbus gpio for usb2
-+S:CONFIG_USB2_VBUS_PIN=""
+CONFIG_USB2_VBUS_PIN=""
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_VIDEO_LCD_BL_PWM_ACTIVE_LOW=n
CONFIG_VIDEO_LCD_PANEL_LVDS=y
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN4I=y
-+S:CONFIG_DRAM_CLK=360
-+S:CONFIG_DRAM_ZQ=123
-+S:CONFIG_DRAM_EMR1=4
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN4I=y
+CONFIG_DRAM_CLK=360
+CONFIG_DRAM_ZQ=123
+CONFIG_DRAM_EMR1=4
CONFIG_VIDEO_LCD_POWER="AXP0-0"
CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN5I=y
-+S:CONFIG_DRAM_CLK=408
-+S:CONFIG_DRAM_ZQ=123
-+S:CONFIG_DRAM_EMR1=4
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN5I=y
+CONFIG_DRAM_CLK=408
+CONFIG_DRAM_ZQ=123
+CONFIG_DRAM_EMR1=4
CONFIG_VIDEO_LCD_POWER="PH7"
CONFIG_VIDEO_LCD_BL_EN="PH6"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN8I=y
-+S:CONFIG_DRAM_CLK=432
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I=y
+CONFIG_DRAM_CLK=432
# zq = 0xf74a
-+S:CONFIG_DRAM_ZQ=63306
+CONFIG_DRAM_ZQ=63306
# Wifi power
-+S:CONFIG_AXP221_DLDO1_VOLT=3300
+CONFIG_AXP221_DLDO1_VOLT=3300
# aldo1 is connected to VCC-IO, VCC-PD, VCC-USB and VCC-HP
-+S:CONFIG_AXP221_ALDO1_VOLT=3000
+CONFIG_AXP221_ALDO1_VOLT=3000
CONFIG_VIDEO_LCD_POWER="PH7"
CONFIG_VIDEO_LCD_BL_EN="PH6"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN8I=y
-+S:CONFIG_DRAM_CLK=480
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I=y
+CONFIG_DRAM_CLK=480
# zq = 0xf777
-+S:CONFIG_DRAM_ZQ=63351
+CONFIG_DRAM_ZQ=63351
# Wifi power
-+S:CONFIG_AXP221_DLDO1_VOLT=3300
+CONFIG_AXP221_DLDO1_VOLT=3300
# aldo1 is connected to VCC-IO, VCC-PD, VCC-USB and VCC-HP
-+S:CONFIG_AXP221_ALDO1_VOLT=3000
+CONFIG_AXP221_ALDO1_VOLT=3000
CONFIG_FDTFILE="sun7i-a20-pcduino3-nano.dtb"
CONFIG_GMAC_TX_DELAY=3
CONFIG_USB1_VBUS_PIN="PH11"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN7I=y
-+S:CONFIG_DRAM_CLK=408
-+S:CONFIG_DRAM_ZQ=122
-+S:CONFIG_DRAM_EMR1=4
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN7I=y
+CONFIG_DRAM_CLK=408
+CONFIG_DRAM_ZQ=122
+CONFIG_DRAM_EMR1=4
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPH(2),USB_EHCI"
CONFIG_FDTFILE="sun7i-a20-pcduino3.dtb"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN7I=y
-+S:CONFIG_DRAM_CLK=480
-+S:CONFIG_DRAM_ZQ=122
-+S:CONFIG_DRAM_EMR1=4
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN7I=y
+CONFIG_DRAM_CLK=480
+CONFIG_DRAM_ZQ=122
+CONFIG_DRAM_EMR1=4
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3"
CONFIG_OF_CONTROL=y
CONFIG_OF_SEPARATE=y
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN7I=y
-+S:CONFIG_DRAM_CLK=480
-+S:CONFIG_DRAM_ZQ=122
-+S:CONFIG_DRAM_EMR1=4
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN7I=y
+CONFIG_DRAM_CLK=480
+CONFIG_DRAM_ZQ=122
+CONFIG_DRAM_EMR1=4
CONFIG_SYS_MALLOC_F=y
CONFIG_SYS_MALLOC_F_LEN=0x400
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,USB_EHCI"
CONFIG_FDTFILE="sun4i-a10-pcduino.dtb"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN4I=y
-+S:CONFIG_DRAM_CLK=408
-+S:CONFIG_DRAM_ZQ=123
-+S:CONFIG_DRAM_EMR1=0
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN4I=y
+CONFIG_DRAM_CLK=408
+CONFIG_DRAM_ZQ=123
+CONFIG_DRAM_EMR1=0
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,USB_EHCI"
CONFIG_FDTFILE="sun7i-a20-mk808c.dtb"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN7I=y
-+S:CONFIG_DRAM_CLK=384
-+S:CONFIG_DRAM_ZQ=127
-+S:CONFIG_DRAM_EMR1=4
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN7I=y
+CONFIG_DRAM_CLK=384
+CONFIG_DRAM_ZQ=127
+CONFIG_DRAM_EMR1=4
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ,NAND"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC83xx=y
-+S:CONFIG_TARGET_MPC8313ERDB=y
+CONFIG_PPC=y
+CONFIG_MPC83xx=y
+CONFIG_TARGET_MPC8313ERDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ,NAND"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC83xx=y
-+S:CONFIG_TARGET_MPC8313ERDB=y
+CONFIG_PPC=y
+CONFIG_MPC83xx=y
+CONFIG_TARGET_MPC8313ERDB=y
CONFIG_VIDEO_LCD_BL_EN="PH7"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_USB_KEYBOARD=n
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN7I=y
-+S:CONFIG_DRAM_CLK=384
-+S:CONFIG_DRAM_ZQ=127
-+S:CONFIG_DRAM_EMR1=4
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN7I=y
+CONFIG_DRAM_CLK=384
+CONFIG_DRAM_ZQ=127
+CONFIG_DRAM_EMR1=4
CONFIG_VIDEO_LCD_BL_EN="PA25"
CONFIG_VIDEO_LCD_BL_PWM="PH13"
CONFIG_USB_KEYBOARD=n
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN6I=y
-+S:CONFIG_DRAM_CLK=360
-+S:CONFIG_DRAM_ZQ=122
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN6I=y
+CONFIG_DRAM_CLK=360
+CONFIG_DRAM_ZQ=122
# Wifi power
-+S:CONFIG_AXP221_DLDO1_VOLT=3300
+CONFIG_AXP221_DLDO1_VOLT=3300
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,AHCI,USB_EHCI"
CONFIG_FDTFILE="sun4i-a10-marsboard.dtb"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN4I=y
-+S:CONFIG_DRAM_CLK=360
-+S:CONFIG_DRAM_ZQ=123
-+S:CONFIG_DRAM_EMR1=0
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN4I=y
+CONFIG_DRAM_CLK=360
+CONFIG_DRAM_ZQ=123
+CONFIG_DRAM_EMR1=0
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,MACPWR=SUNXI_GPH(15),AHCI,USB_EHCI"
CONFIG_FDTFILE="sun4i-a10-a1000.dtb"
CONFIG_VIDEO_VGA=y
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN4I=y
-+S:CONFIG_DRAM_CLK=360
-+S:CONFIG_DRAM_ZQ=123
-+S:CONFIG_DRAM_EMR1=0
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN4I=y
+CONFIG_DRAM_CLK=360
+CONFIG_DRAM_ZQ=123
+CONFIG_DRAM_EMR1=0
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI,SUNXI_GMAC"
CONFIG_FDTFILE="sun6i-a31-i7.dtb"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN6I=y
-+S:CONFIG_DRAM_CLK=312
-+S:CONFIG_DRAM_ZQ=120
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN6I=y
+CONFIG_DRAM_CLK=312
+CONFIG_DRAM_ZQ=120
# The Mele I7 uses 3.3V for general IO
-+S:CONFIG_AXP221_DCDC1_VOLT=3300
+CONFIG_AXP221_DCDC1_VOLT=3300
# Ethernet phy power
-+S:CONFIG_AXP221_DLDO1_VOLT=3300
+CONFIG_AXP221_DLDO1_VOLT=3300
# USB hub power
-+S:CONFIG_AXP221_DLDO4_VOLT=3300
+CONFIG_AXP221_DLDO4_VOLT=3300
# Wifi power
-+S:CONFIG_AXP221_ALDO1_VOLT=3300
+CONFIG_AXP221_ALDO1_VOLT=3300
# Vbus gpio for usb1
-+S:CONFIG_USB1_VBUS_PIN="PC27"
+CONFIG_USB1_VBUS_PIN="PC27"
# No Vbus gpio for usb2
-+S:CONFIG_USB2_VBUS_PIN=""
+CONFIG_USB2_VBUS_PIN=""
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,USB_EHCI"
CONFIG_FDTFILE="sun7i-a20-m3.dtb"
CONFIG_VIDEO_VGA=y
-+S:CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-+S:CONFIG_MMC0_CD_PIN="PH1"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN7I=y
-+S:CONFIG_DRAM_CLK=384
-+S:CONFIG_DRAM_ZQ=127
-+S:CONFIG_DRAM_EMR1=4
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_MMC0_CD_PIN="PH1"
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN7I=y
+CONFIG_DRAM_CLK=384
+CONFIG_DRAM_ZQ=127
+CONFIG_DRAM_EMR1=4
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,USB_EHCI,STATUSLED=234"
CONFIG_FDTFILE="sun7i-a20-m5.dtb"
CONFIG_VIDEO_HDMI=y
-+S:CONFIG_MMC0_CD_PIN="PH1"
-+S:CONFIG_USB1_VBUS_PIN="PH6"
-+S:CONFIG_USB2_VBUS_PIN="PH3"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN7I=y
-+S:CONFIG_DRAM_CLK=432
-+S:CONFIG_DRAM_ZQ=122
-+S:CONFIG_DRAM_EMR1=4
+CONFIG_MMC0_CD_PIN="PH1"
+CONFIG_USB1_VBUS_PIN="PH6"
+CONFIG_USB2_VBUS_PIN="PH3"
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN7I=y
+CONFIG_DRAM_CLK=432
+CONFIG_DRAM_ZQ=122
+CONFIG_DRAM_EMR1=4
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI,SUNXI_GMAC"
CONFIG_FDTFILE="sun6i-a31-m9.dtb"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN6I=y
-+S:CONFIG_DRAM_CLK=312
-+S:CONFIG_DRAM_ZQ=120
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN6I=y
+CONFIG_DRAM_CLK=312
+CONFIG_DRAM_ZQ=120
# The Mele M9 uses 3.3V for general IO
-+S:CONFIG_AXP221_DCDC1_VOLT=3300
+CONFIG_AXP221_DCDC1_VOLT=3300
# Ethernet phy power
-+S:CONFIG_AXP221_DLDO1_VOLT=3300
+CONFIG_AXP221_DLDO1_VOLT=3300
# USB hub power
-+S:CONFIG_AXP221_DLDO4_VOLT=3300
+CONFIG_AXP221_DLDO4_VOLT=3300
# Wifi power
-+S:CONFIG_AXP221_ALDO1_VOLT=3300
+CONFIG_AXP221_ALDO1_VOLT=3300
# Vbus gpio for usb1
-+S:CONFIG_USB1_VBUS_PIN="PC27"
+CONFIG_USB1_VBUS_PIN="PC27"
# No Vbus gpio for usb2
-+S:CONFIG_USB2_VBUS_PIN=""
+CONFIG_USB2_VBUS_PIN=""
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,USB_EHCI"
CONFIG_FDTFILE="sun4i-a10-mini-xplus.dtb"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN4I=y
-+S:CONFIG_DRAM_CLK=360
-+S:CONFIG_DRAM_ZQ=123
-+S:CONFIG_DRAM_EMR1=0
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN4I=y
+CONFIG_DRAM_CLK=360
+CONFIG_DRAM_ZQ=123
+CONFIG_DRAM_EMR1=0
CONFIG_USB1_VBUS_PIN="PH26"
CONFIG_USB2_VBUS_PIN="PH22"
CONFIG_VIDEO_VGA=y
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN7I=y
-+S:CONFIG_DRAM_CLK=432
-+S:CONFIG_DRAM_ZQ=127
-+S:CONFIG_DRAM_EMR1=4
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN7I=y
+CONFIG_DRAM_CLK=432
+CONFIG_DRAM_ZQ=127
+CONFIG_DRAM_EMR1=4
CONFIG_GMAC_TX_DELAY=3
CONFIG_USB1_VBUS_PIN="PH26"
CONFIG_USB2_VBUS_PIN="PH22"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN7I=y
-+S:CONFIG_DRAM_CLK=432
-+S:CONFIG_DRAM_ZQ=127
-+S:CONFIG_DRAM_EMR1=4
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN7I=y
+CONFIG_DRAM_CLK=432
+CONFIG_DRAM_ZQ=127
+CONFIG_DRAM_EMR1=4
CONFIG_SPL=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,NAND"
-+ST:CONFIG_PPC=y
-+ST:CONFIG_MPC85xx=y
-+ST:CONFIG_TARGET_P1010RDB=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1010RDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1010RDB=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1010RDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SPIFLASH"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1010RDB=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1010RDB=y
CONFIG_SPL=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,NAND"
-+ST:CONFIG_PPC=y
-+ST:CONFIG_MPC85xx=y
-+ST:CONFIG_TARGET_P1010RDB=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1010RDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1010RDB=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1010RDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SPIFLASH"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1010RDB=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1010RDB=y
CONFIG_SPL=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,NAND"
-+ST:CONFIG_PPC=y
-+ST:CONFIG_MPC85xx=y
-+ST:CONFIG_TARGET_P1010RDB=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1010RDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1010RDB=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1010RDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SPIFLASH"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1010RDB=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1010RDB=y
CONFIG_SPL=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,NAND"
-+ST:CONFIG_PPC=y
-+ST:CONFIG_MPC85xx=y
-+ST:CONFIG_TARGET_P1010RDB=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1010RDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1010RDB=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1010RDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SPIFLASH"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1010RDB=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1010RDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1020MBG,SDCARD,36BIT"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1020MBG,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT,NAND"
-+ST:CONFIG_PPC=y
-+ST:CONFIG_MPC85xx=y
-+ST:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT,SPIFLASH"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,NAND"
-+ST:CONFIG_PPC=y
-+ST:CONFIG_MPC85xx=y
-+ST:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,SPIFLASH"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD,NAND"
-+ST:CONFIG_PPC=y
-+ST:CONFIG_MPC85xx=y
-+ST:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD,SPIFLASH"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1020UTM,36BIT,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1020UTM,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT,NAND"
-+ST:CONFIG_PPC=y
-+ST:CONFIG_MPC85xx=y
-+ST:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT,SPIFLASH"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,NAND"
-+ST:CONFIG_PPC=y
-+ST:CONFIG_MPC85xx=y
-+ST:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,SPIFLASH"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="36BIT,NAND"
-+ST:CONFIG_PPC=y
-+ST:CONFIG_MPC85xx=y
-+ST:CONFIG_TARGET_P1022DS=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1022DS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="36BIT,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1022DS=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1022DS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="36BIT,SPIFLASH"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1022DS=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1022DS=y
CONFIG_SPL=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
-+ST:CONFIG_PPC=y
-+ST:CONFIG_MPC85xx=y
-+ST:CONFIG_TARGET_P1022DS=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1022DS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1022DS=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1022DS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1022DS=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1022DS=y
CONFIG_SPL=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,NAND"
-+ST:CONFIG_PPC=y
-+ST:CONFIG_MPC85xx=y
-+ST:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,SPIFLASH"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,NAND"
-+ST:CONFIG_PPC=y
-+ST:CONFIG_MPC85xx=y
-+ST:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,SPIFLASH"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,NAND"
-+ST:CONFIG_PPC=y
-+ST:CONFIG_MPC85xx=y
-+ST:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,SPIFLASH"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,NAND"
-+ST:CONFIG_PPC=y
-+ST:CONFIG_MPC85xx=y
-+ST:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SPIFLASH"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_P1_P2_RDB_PC=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_T102XQDS=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T102XQDS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_T102XQDS=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T102XQDS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_T102XQDS=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T102XQDS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_T102XRDB=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T102XRDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_T102XRDB=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T102XRDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_T102XRDB=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T102XRDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_T104XRDB=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T104XRDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_T104XRDB=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T104XRDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_T104XRDB=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T104XRDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_T104XRDB=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T104XRDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_T104XRDB=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T104XRDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_T104XRDB=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T104XRDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_T208XQDS=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T208XQDS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_T208XQDS=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T208XQDS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_T208XQDS=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T208XQDS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_T208XRDB=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T208XRDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_T208XRDB=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T208XRDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_T208XRDB=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T208XRDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_T208XQDS=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T208XQDS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_T208XQDS=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T208XQDS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_T208XQDS=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T208XQDS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_T4240QDS=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T4240QDS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_T4240QDS=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T4240QDS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_T4240QDS=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T4240QDS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC85xx=y
-+S:CONFIG_TARGET_T4240QDS=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T4240QDS=y
CONFIG_VIDEO_LCD_POWER="AXP0-0"
CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN5I=y
-+S:CONFIG_DRAM_CLK=408
-+S:CONFIG_DRAM_ZQ=123
-+S:CONFIG_DRAM_EMR1=4
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN5I=y
+CONFIG_DRAM_CLK=408
+CONFIG_DRAM_ZQ=123
+CONFIG_DRAM_EMR1=4
CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_VIDEO_LCD_TL059WV5C0=y
-+S:CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-+S:CONFIG_MMC0_CD_PIN="PG0"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN5I=y
-+S:CONFIG_DRAM_CLK=432
-+S:CONFIG_DRAM_ZQ=123
-+S:CONFIG_DRAM_EMR1=0
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_MMC0_CD_PIN="PG0"
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN5I=y
+CONFIG_DRAM_CLK=432
+CONFIG_DRAM_ZQ=123
+CONFIG_DRAM_EMR1=0
CONFIG_VIDEO_LCD_POWER="PH8"
CONFIG_VIDEO_LCD_BL_EN="PH7"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN7I=y
-+S:CONFIG_DRAM_CLK=384
-+S:CONFIG_DRAM_ZQ=127
-+S:CONFIG_DRAM_EMR1=4
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN7I=y
+CONFIG_DRAM_CLK=384
+CONFIG_DRAM_ZQ=127
+CONFIG_DRAM_EMR1=4
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_VIDEO_LCD_PANEL_LVDS=y
CONFIG_VIDEO_VGA=y
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN7I=y
-+S:CONFIG_DRAM_CLK=384
-+S:CONFIG_DRAM_ZQ=127
-+S:CONFIG_DRAM_EMR1=4
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN7I=y
+CONFIG_DRAM_CLK=384
+CONFIG_DRAM_ZQ=127
+CONFIG_DRAM_EMR1=4
CONFIG_SPL=y
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC5xxx=y
-+S:CONFIG_TARGET_A3M071=y
+CONFIG_PPC=y
+CONFIG_MPC5xxx=y
+CONFIG_TARGET_A3M071=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="A4M2K"
-+S:CONFIG_PPC=y
-+S:CONFIG_MPC5xxx=y
-+S:CONFIG_TARGET_A3M071=y
+CONFIG_PPC=y
+CONFIG_MPC5xxx=y
+CONFIG_TARGET_A3M071=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_AM335X_EVM=y
+CONFIG_ARM=y
+CONFIG_TARGET_AM335X_EVM=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT,ENABLE_VBOOT"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_AM335X_EVM=y
+CONFIG_ARM=y
+CONFIG_TARGET_AM335X_EVM=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-boneblack"
CONFIG_FIT=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SYS_EXTRA_OPTIONS="NAND"
CONFIG_CONS_INDEX=1
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_AM335X_EVM=y
+CONFIG_ARM=y
+CONFIG_TARGET_AM335X_EVM=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SYS_EXTRA_OPTIONS="NAND"
CONFIG_CONS_INDEX=1
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_AM335X_EVM=y
+CONFIG_ARM=y
+CONFIG_TARGET_AM335X_EVM=y
CONFIG_NOR=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SYS_EXTRA_OPTIONS="SPI_BOOT"
CONFIG_CONS_INDEX=1
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_AM335X_EVM=y
+CONFIG_ARM=y
+CONFIG_TARGET_AM335X_EVM=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SYS_EXTRA_OPTIONS="NAND,SPL_USBETH_SUPPORT"
CONFIG_CONS_INDEX=1
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_AM335X_EVM=y
+CONFIG_ARM=y
+CONFIG_TARGET_AM335X_EVM=y
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_AM335X_IGEP0033=y
+CONFIG_ARM=y
+CONFIG_TARGET_AM335X_IGEP0033=y
CONFIG_SYS_MALLOC_F=y
CONFIG_SYS_MALLOC_F_LEN=0x400
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP34XX=y
-+S:CONFIG_TARGET_AM3517_CRANE=y
+CONFIG_ARM=y
+CONFIG_OMAP34XX=y
+CONFIG_TARGET_AM3517_CRANE=y
CONFIG_DM=n
CONFIG_DM_SERIAL=n
CONFIG_DM_GPIO=n
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP34XX=y
-+S:CONFIG_TARGET_AM3517_EVM=y
+CONFIG_ARM=y
+CONFIG_OMAP34XX=y
+CONFIG_TARGET_AM3517_EVM=y
CONFIG_DM=n
CONFIG_DM_SERIAL=n
CONFIG_DM_GPIO=n
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_AM43XX_EVM=y
+CONFIG_ARM=y
+CONFIG_TARGET_AM43XX_EVM=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TEGRA=y
-+S:CONFIG_TEGRA30=y
-+S:CONFIG_TARGET_APALIS_T30=y
+CONFIG_ARM=y
+CONFIG_TEGRA=y
+CONFIG_TEGRA30=y
+CONFIG_TARGET_APALIS_T30=y
CONFIG_DEFAULT_DEVICE_TREE="tegra30-apalis"
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_APF27=y
+CONFIG_ARM=y
+CONFIG_TARGET_APF27=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_APX4DEVKIT=y
+CONFIG_ARM=y
+CONFIG_TARGET_APX4DEVKIT=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_EXYNOS=y
-+S:CONFIG_TARGET_ARNDALE=y
+CONFIG_ARM=y
+CONFIG_ARCH_EXYNOS=y
+CONFIG_TARGET_ARNDALE=y
CONFIG_DEFAULT_DEVICE_TREE="exynos5250-arndale"
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2068,BOARD_AXM"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_AT91=y
-+S:CONFIG_TARGET_TAURUS=y
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_TAURUS=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,USB_EHCI"
CONFIG_FDTFILE="sun4i-a10-ba10-tvbox.dtb"
CONFIG_USB2_VBUS_PIN="PH12"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN4I=y
-+S:CONFIG_DRAM_CLK=384
-+S:CONFIG_DRAM_ZQ=123
-+S:CONFIG_DRAM_EMR1=4
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN4I=y
+CONFIG_DRAM_CLK=384
+CONFIG_DRAM_ZQ=123
+CONFIG_DRAM_EMR1=4
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=3"
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP54XX=y
-+S:CONFIG_TARGET_BEAGLE_X15=y
+CONFIG_ARM=y
+CONFIG_OMAP54XX=y
+CONFIG_TARGET_BEAGLE_X15=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TEGRA=y
-+S:CONFIG_TEGRA30=y
-+S:CONFIG_TARGET_BEAVER=y
+CONFIG_ARM=y
+CONFIG_TEGRA=y
+CONFIG_TEGRA30=y
+CONFIG_TARGET_BEAVER=y
CONFIG_DEFAULT_DEVICE_TREE="tegra30-beaver"
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_BG0900=y
+CONFIG_ARM=y
+CONFIG_TARGET_BG0900=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_BAV335X=y
-+S:CONFIG_BAV_VERSION=1
+CONFIG_ARM=y
+CONFIG_TARGET_BAV335X=y
+CONFIG_BAV_VERSION=1
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_BAV335X=y
-+S:CONFIG_BAV_VERSION=2
+CONFIG_ARM=y
+CONFIG_TARGET_BAV335X=y
+CONFIG_BAV_VERSION=2
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP34XX=y
-+S:CONFIG_TARGET_OMAP3_CAIRO=y
+CONFIG_ARM=y
+CONFIG_OMAP34XX=y
+CONFIG_TARGET_OMAP3_CAIRO=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_DAVINCI=y
-+S:CONFIG_TARGET_CAM_ENC_4XX=y
+CONFIG_ARM=y
+CONFIG_ARCH_DAVINCI=y
+CONFIG_TARGET_CAM_ENC_4XX=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TEGRA=y
-+S:CONFIG_TEGRA30=y
-+S:CONFIG_TARGET_CARDHU=y
+CONFIG_ARM=y
+CONFIG_TEGRA=y
+CONFIG_TEGRA30=y
+CONFIG_TARGET_CARDHU=y
CONFIG_DEFAULT_DEVICE_TREE="tegra30-cardhu"
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL,SPL"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_CM_FX6=y
+CONFIG_ARM=y
+CONFIG_TARGET_CM_FX6=y
CONFIG_DM=y
CONFIG_DM_GPIO=y
CONFIG_DM_SERIAL=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_CM_T335=y
+CONFIG_ARM=y
+CONFIG_TARGET_CM_T335=y
CONFIG_SYS_MALLOC_F=y
CONFIG_SYS_MALLOC_F_LEN=0x400
CONFIG_SPL=n
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP34XX=y
-+S:CONFIG_TARGET_CM_T3517=y
+CONFIG_ARM=y
+CONFIG_OMAP34XX=y
+CONFIG_TARGET_CM_T3517=y
CONFIG_DM=n
CONFIG_DM_SERIAL=n
CONFIG_DM_GPIO=n
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP34XX=y
-+S:CONFIG_TARGET_CM_T35=y
+CONFIG_ARM=y
+CONFIG_OMAP34XX=y
+CONFIG_TARGET_CM_T35=y
CONFIG_DM=n
CONFIG_DM_SERIAL=n
CONFIG_DM_GPIO=n
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP54XX=y
-+S:CONFIG_TARGET_CM_T54=y
+CONFIG_ARM=y
+CONFIG_OMAP54XX=y
+CONFIG_TARGET_CM_T54=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TEGRA=y
-+S:CONFIG_TEGRA20=y
-+S:CONFIG_TARGET_COLIBRI_T20_IRIS=y
+CONFIG_ARM=y
+CONFIG_TEGRA=y
+CONFIG_TEGRA20=y
+CONFIG_TARGET_COLIBRI_T20_IRIS=y
CONFIG_DEFAULT_DEVICE_TREE="tegra20-colibri_t20_iris"
-+S:CONFIG_ARM=y
-+S:CONFIG_TEGRA=y
-+S:CONFIG_TEGRA30=y
-+S:CONFIG_TARGET_COLIBRI_T30=y
+CONFIG_ARM=y
+CONFIG_TEGRA=y
+CONFIG_TEGRA30=y
+CONFIG_TARGET_COLIBRI_T30=y
CONFIG_DEFAULT_DEVICE_TREE="tegra30-colibri"
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_NANDFLASH"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_AT91=y
-+S:CONFIG_TARGET_CORVUS=y
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_CORVUS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="DA850_AM18X_EVM,MAC_ADDR_IN_EEPROM,SYS_I2C_EEPROM_ADDR_LEN=2,SYS_I2C_EEPROM_ADDR=0x50"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_DAVINCI=y
-+S:CONFIG_TARGET_DA850EVM=y
+CONFIG_ARM=y
+CONFIG_ARCH_DAVINCI=y
+CONFIG_TARGET_DA850EVM=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_DAVINCI=y
-+S:CONFIG_TARGET_DA850EVM=y
+CONFIG_ARM=y
+CONFIG_ARCH_DAVINCI=y
+CONFIG_TARGET_DA850EVM=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TEGRA=y
-+S:CONFIG_TEGRA114=y
-+S:CONFIG_TARGET_DALMORE=y
+CONFIG_ARM=y
+CONFIG_TEGRA=y
+CONFIG_TEGRA114=y
+CONFIG_TARGET_DALMORE=y
CONFIG_DEFAULT_DEVICE_TREE="tegra114-dalmore"
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_DB_MV784MP_GP=y
+CONFIG_ARM=y
+CONFIG_TARGET_DB_MV784MP_GP=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP34XX=y
-+S:CONFIG_TARGET_DEVKIT8000=y
+CONFIG_ARM=y
+CONFIG_OMAP34XX=y
+CONFIG_TARGET_DEVKIT8000=y
CONFIG_DM=y
CONFIG_DM_SERIAL=y
CONFIG_DM_GPIO=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1"
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP54XX=y
-+S:CONFIG_TARGET_DRA7XX_EVM=y
+CONFIG_ARM=y
+CONFIG_OMAP54XX=y
+CONFIG_TARGET_DRA7XX_EVM=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1,QSPI_BOOT"
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP54XX=y
-+S:CONFIG_TARGET_DRA7XX_EVM=y
+CONFIG_ARM=y
+CONFIG_OMAP54XX=y
+CONFIG_TARGET_DRA7XX_EVM=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=3,SPL_YMODEM_SUPPORT"
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP54XX=y
-+S:CONFIG_TARGET_DRA7XX_EVM=y
+CONFIG_ARM=y
+CONFIG_OMAP54XX=y
+CONFIG_TARGET_DRA7XX_EVM=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_DRACO=y
+CONFIG_ARM=y
+CONFIG_TARGET_DRACO=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP44XX=y
-+S:CONFIG_TARGET_DUOVERO=y
+CONFIG_ARM=y
+CONFIG_OMAP44XX=y
+CONFIG_TARGET_DUOVERO=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_DXR2=y
+CONFIG_ARM=y
+CONFIG_TARGET_DXR2=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP34XX=y
-+S:CONFIG_TARGET_ECO5PK=y
+CONFIG_ARM=y
+CONFIG_OMAP34XX=y
+CONFIG_TARGET_ECO5PK=y
CONFIG_DM=n
CONFIG_DM_SERIAL=n
CONFIG_DM_GPIO=n
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_ORION5X=y
-+S:CONFIG_TARGET_EDMINIV2=y
+CONFIG_ARM=y
+CONFIG_ORION5X=y
+CONFIG_TARGET_EDMINIV2=y
CONFIG_VIDEO_LCD_POWER="AXP0-0"
CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN5I=y
-+S:CONFIG_DRAM_CLK=384
-+S:CONFIG_DRAM_ZQ=123
-+S:CONFIG_DRAM_EMR1=4
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN5I=y
+CONFIG_DRAM_CLK=384
+CONFIG_DRAM_ZQ=123
+CONFIG_DRAM_EMR1=4
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_GW_VENTANA=y
+CONFIG_ARM=y
+CONFIG_TARGET_GW_VENTANA=y
CONFIG_SYS_MALLOC_F=y
CONFIG_SYS_MALLOC_F_LEN=0x400
-+S:CONFIG_ARM=y
-+S:CONFIG_TEGRA=y
-+S:CONFIG_TEGRA20=y
-+S:CONFIG_TARGET_HARMONY=y
+CONFIG_ARM=y
+CONFIG_TEGRA=y
+CONFIG_TEGRA20=y
+CONFIG_TARGET_HARMONY=y
CONFIG_DEFAULT_DEVICE_TREE="tegra20-harmony"
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,MACPWR=SUNXI_GPH(21),USB_EHCI"
CONFIG_FDTFILE="sun7i-a20-i12-tvbox.dtb"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN7I=y
-+S:CONFIG_DRAM_CLK=384
-+S:CONFIG_DRAM_ZQ=127
-+S:CONFIG_DRAM_EMR1=4
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN7I=y
+CONFIG_DRAM_CLK=384
+CONFIG_DRAM_ZQ=127
+CONFIG_DRAM_EMR1=4
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_ONENAND"
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP34XX=y
-+S:CONFIG_TARGET_OMAP3_IGEP00X0=y
+CONFIG_ARM=y
+CONFIG_OMAP34XX=y
+CONFIG_TARGET_OMAP3_IGEP00X0=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_NAND"
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP34XX=y
-+S:CONFIG_TARGET_OMAP3_IGEP00X0=y
+CONFIG_ARM=y
+CONFIG_OMAP34XX=y
+CONFIG_TARGET_OMAP3_IGEP00X0=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_ONENAND"
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP34XX=y
-+S:CONFIG_TARGET_OMAP3_IGEP00X0=y
+CONFIG_ARM=y
+CONFIG_OMAP34XX=y
+CONFIG_TARGET_OMAP3_IGEP00X0=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_NAND"
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP34XX=y
-+S:CONFIG_TARGET_OMAP3_IGEP00X0=y
+CONFIG_ARM=y
+CONFIG_OMAP34XX=y
+CONFIG_TARGET_OMAP3_IGEP00X0=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0032,BOOT_ONENAND"
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP34XX=y
-+S:CONFIG_TARGET_OMAP3_IGEP00X0=y
+CONFIG_ARM=y
+CONFIG_OMAP34XX=y
+CONFIG_TARGET_OMAP3_IGEP00X0=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_DAVINCI=y
-+S:CONFIG_TARGET_IPAM390=y
+CONFIG_ARM=y
+CONFIG_ARCH_DAVINCI=y
+CONFIG_TARGET_IPAM390=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,USB_EHCI,MACPWR=SUNXI_GPH(19)"
CONFIG_FDTFILE="sun4i-a10-jesurun-q5.dtb"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN4I=y
-+S:CONFIG_DRAM_CLK=312
-+S:CONFIG_DRAM_ZQ=123
-+S:CONFIG_DRAM_EMR1=0
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN4I=y
+CONFIG_DRAM_CLK=312
+CONFIG_DRAM_ZQ=123
+CONFIG_DRAM_EMR1=0
-+S:CONFIG_ARM=y
-+S:CONFIG_TEGRA=y
-+S:CONFIG_TEGRA124=y
-+S:CONFIG_TARGET_JETSON_TK1=y
+CONFIG_ARM=y
+CONFIG_TEGRA=y
+CONFIG_TEGRA124=y
+CONFIG_TARGET_JETSON_TK1=y
CONFIG_DEFAULT_DEVICE_TREE="tegra124-jetson-tk1"
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_KEYSTONE=y
-+S:CONFIG_TARGET_K2E_EVM=y
+CONFIG_ARM=y
+CONFIG_ARCH_KEYSTONE=y
+CONFIG_TARGET_K2E_EVM=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_KEYSTONE=y
-+S:CONFIG_TARGET_K2HK_EVM=y
+CONFIG_ARM=y
+CONFIG_ARCH_KEYSTONE=y
+CONFIG_TARGET_K2HK_EVM=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_KEYSTONE=y
-+S:CONFIG_TARGET_K2L_EVM=y
+CONFIG_ARM=y
+CONFIG_ARCH_KEYSTONE=y
+CONFIG_TARGET_K2L_EVM=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_KWB=y
+CONFIG_ARM=y
+CONFIG_TARGET_KWB=y
# CONFIG_CMD_CRC32 is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="LCD4_LWMON5"
-+S:CONFIG_PPC=y
-+S:CONFIG_4xx=y
-+S:CONFIG_TARGET_LWMON5=y
+CONFIG_PPC=y
+CONFIG_4xx=y
+CONFIG_TARGET_LWMON5=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_LS1021AQDS=y
+CONFIG_ARM=y
+CONFIG_TARGET_LS1021AQDS=y
CONFIG_SYS_EXTRA_OPTIONS="LPUART"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_LS1021AQDS=y
+CONFIG_ARM=y
+CONFIG_TARGET_LS1021AQDS=y
CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_LS1021AQDS=y
+CONFIG_ARM=y
+CONFIG_TARGET_LS1021AQDS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_LS1021AQDS=y
+CONFIG_ARM=y
+CONFIG_TARGET_LS1021AQDS=y
CONFIG_SYS_EXTRA_OPTIONS="LPUART"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_LS1021ATWR=y
+CONFIG_ARM=y
+CONFIG_TARGET_LS1021ATWR=y
CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_LS1021ATWR=y
+CONFIG_ARM=y
+CONFIG_TARGET_LS1021ATWR=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_LS1021ATWR=y
+CONFIG_ARM=y
+CONFIG_TARGET_LS1021ATWR=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_M28EVK=y
+CONFIG_ARM=y
+CONFIG_TARGET_M28EVK=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/denx/m53evk/imximage.cfg"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_M53EVK=y
+CONFIG_ARM=y
+CONFIG_TARGET_M53EVK=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_MAXBCM=y
+CONFIG_ARM=y
+CONFIG_TARGET_MAXBCM=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP34XX=y
-+S:CONFIG_TARGET_MCX=y
+CONFIG_ARM=y
+CONFIG_OMAP34XX=y
+CONFIG_TARGET_MCX=y
CONFIG_DM=n
CONFIG_DM_SERIAL=n
CONFIG_DM_GPIO=n
-+S:CONFIG_ARM=y
-+S:CONFIG_TEGRA=y
-+S:CONFIG_TEGRA20=y
-+S:CONFIG_TARGET_MEDCOM_WIDE=y
+CONFIG_ARM=y
+CONFIG_TEGRA=y
+CONFIG_TEGRA20=y
+CONFIG_TARGET_MEDCOM_WIDE=y
CONFIG_DEFAULT_DEVICE_TREE="tegra20-medcom-wide"
CONFIG_SPL=y
-+S:CONFIG_MICROBLAZE=y
-+S:CONFIG_TARGET_MICROBLAZE_GENERIC=y
+CONFIG_MICROBLAZE=y
+CONFIG_TARGET_MICROBLAZE_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic"
CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER,USB_EHCI"
CONFIG_FDTFILE="sun5i-a10s-mk802.dtb"
CONFIG_USB1_VBUS_PIN="PB10"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN5I=y
-+S:CONFIG_DRAM_CLK=432
-+S:CONFIG_DRAM_ZQ=123
-+S:CONFIG_DRAM_EMR1=0
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN5I=y
+CONFIG_DRAM_CLK=432
+CONFIG_DRAM_ZQ=123
+CONFIG_DRAM_EMR1=0
CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI"
CONFIG_FDTFILE="sun4i-a10-mk802.dtb"
CONFIG_USB2_VBUS_PIN="PH12"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN4I=y
-+S:CONFIG_DRAM_CLK=360
-+S:CONFIG_DRAM_ZQ=123
-+S:CONFIG_DRAM_EMR1=0
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN4I=y
+CONFIG_DRAM_CLK=360
+CONFIG_DRAM_ZQ=123
+CONFIG_DRAM_EMR1=0
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,USB_EHCI"
CONFIG_FDTFILE="sun4i-a10-mk802ii.dtb"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN4I=y
-+S:CONFIG_DRAM_CLK=360
-+S:CONFIG_DRAM_ZQ=123
-+S:CONFIG_DRAM_EMR1=0
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN4I=y
+CONFIG_DRAM_CLK=360
+CONFIG_DRAM_ZQ=123
+CONFIG_DRAM_EMR1=0
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP34XX=y
-+S:CONFIG_TARGET_MT_VENTOUX=y
+CONFIG_ARM=y
+CONFIG_OMAP34XX=y
+CONFIG_TARGET_MT_VENTOUX=y
CONFIG_DM=n
CONFIG_DM_SERIAL=n
CONFIG_DM_GPIO=n
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_MX23_OLINUXINO=y
+CONFIG_ARM=y
+CONFIG_TARGET_MX23_OLINUXINO=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_MX23EVK=y
+CONFIG_ARM=y
+CONFIG_TARGET_MX23EVK=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="MXS_AUART,MXS_AUART_BASE=MXS_UARTAPP3_BASE,ENV_IS_IN_MMC"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_MX28EVK=y
+CONFIG_ARM=y
+CONFIG_TARGET_MX28EVK=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_MMC"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_MX28EVK=y
+CONFIG_ARM=y
+CONFIG_TARGET_MX28EVK=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_NAND"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_MX28EVK=y
+CONFIG_ARM=y
+CONFIG_TARGET_MX28EVK=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_SPI_FLASH"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_MX28EVK=y
+CONFIG_ARM=y
+CONFIG_TARGET_MX28EVK=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_MX31PDK=y
+CONFIG_ARM=y
+CONFIG_TARGET_MX31PDK=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6Q"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_MX6SABRESD=y
+CONFIG_ARM=y
+CONFIG_TARGET_MX6SABRESD=y
CONFIG_DM=y
CONFIG_DM_THERMAL=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6SX"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_MX6SXSABRESD=y
+CONFIG_ARM=y
+CONFIG_TARGET_MX6SXSABRESD=y
CONFIG_DM=y
CONFIG_DM_THERMAL=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_KOSAGI_NOVENA=y
+CONFIG_ARM=y
+CONFIG_TARGET_KOSAGI_NOVENA=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TEGRA=y
-+S:CONFIG_TEGRA124=y
-+S:CONFIG_TARGET_NYAN_BIG=y
+CONFIG_ARM=y
+CONFIG_TEGRA=y
+CONFIG_TEGRA124=y
+CONFIG_TARGET_NYAN_BIG=y
CONFIG_DEFAULT_DEVICE_TREE="tegra124-nyan-big"
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP34XX=y
-+S:CONFIG_TARGET_OMAP3_BEAGLE=y
+CONFIG_ARM=y
+CONFIG_OMAP34XX=y
+CONFIG_TARGET_OMAP3_BEAGLE=y
CONFIG_DM=y
CONFIG_DM_GPIO=y
CONFIG_DM_SERIAL=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP34XX=y
-+S:CONFIG_TARGET_OMAP3_EVM=y
+CONFIG_ARM=y
+CONFIG_OMAP34XX=y
+CONFIG_TARGET_OMAP3_EVM=y
CONFIG_DM=n
CONFIG_DM_SERIAL=n
CONFIG_DM_GPIO=n
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP34XX=y
-+S:CONFIG_TARGET_OMAP3_EVM_QUICK_MMC=y
+CONFIG_ARM=y
+CONFIG_OMAP34XX=y
+CONFIG_TARGET_OMAP3_EVM_QUICK_MMC=y
CONFIG_DM=n
CONFIG_DM_SERIAL=n
CONFIG_DM_GPIO=n
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP34XX=y
-+S:CONFIG_TARGET_OMAP3_EVM_QUICK_NAND=y
+CONFIG_ARM=y
+CONFIG_OMAP34XX=y
+CONFIG_TARGET_OMAP3_EVM_QUICK_NAND=y
CONFIG_DM=n
CONFIG_DM_SERIAL=n
CONFIG_DM_GPIO=n
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_BOARD_OMAP3_HA"
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP34XX=y
-+S:CONFIG_TARGET_TAO3530=y
+CONFIG_ARM=y
+CONFIG_OMAP34XX=y
+CONFIG_TARGET_TAO3530=y
CONFIG_DM=n
CONFIG_DM_SERIAL=n
CONFIG_DM_GPIO=n
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP34XX=y
-+S:CONFIG_TARGET_OMAP3_OVERO=y
+CONFIG_ARM=y
+CONFIG_OMAP34XX=y
+CONFIG_TARGET_OMAP3_OVERO=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP44XX=y
-+S:CONFIG_TARGET_OMAP4_PANDA=y
+CONFIG_ARM=y
+CONFIG_OMAP44XX=y
+CONFIG_TARGET_OMAP4_PANDA=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP44XX=y
-+S:CONFIG_TARGET_OMAP4_SDP4430=y
+CONFIG_ARM=y
+CONFIG_OMAP44XX=y
+CONFIG_TARGET_OMAP4_SDP4430=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP54XX=y
-+S:CONFIG_TARGET_OMAP5_UEVM=y
+CONFIG_ARM=y
+CONFIG_OMAP54XX=y
+CONFIG_TARGET_OMAP5_UEVM=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_EXYNOS=y
-+S:CONFIG_TARGET_ORIGEN=y
+CONFIG_ARM=y
+CONFIG_ARCH_EXYNOS=y
+CONFIG_TARGET_ORIGEN=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="exynos4210-origen"
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_OT1200=y
+CONFIG_ARM=y
+CONFIG_TARGET_OT1200=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_PALMTREO680=y
+CONFIG_ARM=y
+CONFIG_TARGET_PALMTREO680=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TEGRA=y
-+S:CONFIG_TEGRA20=y
-+S:CONFIG_TARGET_PAZ00=y
+CONFIG_ARM=y
+CONFIG_TEGRA=y
+CONFIG_TEGRA20=y
+CONFIG_TARGET_PAZ00=y
CONFIG_DEFAULT_DEVICE_TREE="tegra20-paz00"
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="REV1"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_PCM051=y
+CONFIG_ARM=y
+CONFIG_TARGET_PCM051=y
CONFIG_SYS_MALLOC_F=y
CONFIG_SYS_MALLOC_F_LEN=0x400
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="REV3"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_PCM051=y
+CONFIG_ARM=y
+CONFIG_TARGET_PCM051=y
CONFIG_SYS_MALLOC_F=y
CONFIG_SYS_MALLOC_F_LEN=0x400
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_EXYNOS=y
-+S:CONFIG_TARGET_PEACH_PI=y
+CONFIG_ARM=y
+CONFIG_ARCH_EXYNOS=y
+CONFIG_TARGET_PEACH_PI=y
CONFIG_DEFAULT_DEVICE_TREE="exynos5800-peach-pi"
CONFIG_CROS_EC=y
CONFIG_CROS_EC_SPI=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_EXYNOS=y
-+S:CONFIG_TARGET_PEACH_PIT=y
+CONFIG_ARM=y
+CONFIG_ARCH_EXYNOS=y
+CONFIG_TARGET_PEACH_PIT=y
CONFIG_DEFAULT_DEVICE_TREE="exynos5420-peach-pit"
CONFIG_CROS_EC=y
CONFIG_CROS_EC_SPI=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_PENGWYN=y
+CONFIG_ARM=y
+CONFIG_TARGET_PENGWYN=y
CONFIG_SYS_MALLOC_F=y
CONFIG_SYS_MALLOC_F_LEN=0x400
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_PEPPER=y
+CONFIG_ARM=y
+CONFIG_TARGET_PEPPER=y
CONFIG_SYS_MALLOC_F=y
CONFIG_SYS_MALLOC_F_LEN=0x400
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6DL"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_PLATINUM_PICON=y
+CONFIG_ARM=y
+CONFIG_TARGET_PLATINUM_PICON=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_PLATINUM_TITANIUM=y
+CONFIG_ARM=y
+CONFIG_TARGET_PLATINUM_TITANIUM=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TEGRA=y
-+S:CONFIG_TEGRA20=y
-+S:CONFIG_TARGET_PLUTUX=y
+CONFIG_ARM=y
+CONFIG_TEGRA=y
+CONFIG_TEGRA20=y
+CONFIG_TARGET_PLUTUX=y
CONFIG_DEFAULT_DEVICE_TREE="tegra20-plutux"
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_PXM2=y
+CONFIG_ARM=y
+CONFIG_TARGET_PXM2=y
CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER,USB_EHCI"
CONFIG_FDTFILE="sun5i-a10s-r7-tv-dongle.dtb"
CONFIG_USB1_VBUS_PIN="PG13"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN5I=y
-+S:CONFIG_DRAM_CLK=384
-+S:CONFIG_DRAM_ZQ=123
-+S:CONFIG_DRAM_EMR1=4
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN5I=y
+CONFIG_DRAM_CLK=384
+CONFIG_DRAM_ZQ=123
+CONFIG_DRAM_EMR1=4
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_RUT=y
+CONFIG_ARM=y
+CONFIG_TARGET_RUT=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_MMC"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_AT91=y
-+S:CONFIG_TARGET_SAMA5D3_XPLAINED=y
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_SAMA5D3_XPLAINED=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_AT91=y
-+S:CONFIG_TARGET_SAMA5D3_XPLAINED=y
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_SAMA5D3_XPLAINED=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_MMC"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_AT91=y
-+S:CONFIG_TARGET_SAMA5D3XEK=y
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_SAMA5D3XEK=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_AT91=y
-+S:CONFIG_TARGET_SAMA5D3XEK=y
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_SAMA5D3XEK=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_SERIALFLASH"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_AT91=y
-+S:CONFIG_TARGET_SAMA5D3XEK=y
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_SAMA5D3XEK=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_MMC"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_AT91=y
-+S:CONFIG_TARGET_SAMA5D4_XPLAINED=y
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_SAMA5D4_XPLAINED=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_NANDFLASH"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_AT91=y
-+S:CONFIG_TARGET_SAMA5D4_XPLAINED=y
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_SAMA5D4_XPLAINED=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_AT91=y
-+S:CONFIG_TARGET_SAMA5D4_XPLAINED=y
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_SAMA5D4_XPLAINED=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_MMC"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_AT91=y
-+S:CONFIG_TARGET_SAMA5D4EK=y
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_SAMA5D4EK=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_NANDFLASH"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_AT91=y
-+S:CONFIG_TARGET_SAMA5D4EK=y
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_SAMA5D4EK=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_AT91=y
-+S:CONFIG_TARGET_SAMA5D4EK=y
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_SAMA5D4EK=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SANSA_FUZE_PLUS=y
+CONFIG_ARM=y
+CONFIG_TARGET_SANSA_FUZE_PLUS=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SC_SPS_1=y
+CONFIG_ARM=y
+CONFIG_TARGET_SC_SPS_1=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TEGRA=y
-+S:CONFIG_TEGRA20=y
-+S:CONFIG_TARGET_SEABOARD=y
+CONFIG_ARM=y
+CONFIG_TEGRA=y
+CONFIG_TEGRA20=y
+CONFIG_TARGET_SEABOARD=y
CONFIG_DEFAULT_DEVICE_TREE="tegra20-seaboard"
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_EXYNOS=y
-+S:CONFIG_TARGET_SMDK5250=y
+CONFIG_ARM=y
+CONFIG_ARCH_EXYNOS=y
+CONFIG_TARGET_SMDK5250=y
CONFIG_DEFAULT_DEVICE_TREE="exynos5250-smdk5250"
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_EXYNOS=y
-+S:CONFIG_TARGET_SMDK5420=y
+CONFIG_ARM=y
+CONFIG_ARCH_EXYNOS=y
+CONFIG_TARGET_SMDK5420=y
CONFIG_DEFAULT_DEVICE_TREE="exynos5420-smdk5420"
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_EXYNOS=y
-+S:CONFIG_TARGET_SMDKV310=y
+CONFIG_ARM=y
+CONFIG_ARCH_EXYNOS=y
+CONFIG_TARGET_SMDKV310=y
CONFIG_DEFAULT_DEVICE_TREE="exynos4210-smdkv310"
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_EXYNOS=y
-+S:CONFIG_TARGET_SNOW=y
+CONFIG_ARM=y
+CONFIG_ARCH_EXYNOS=y
+CONFIG_TARGET_SNOW=y
CONFIG_DEFAULT_DEVICE_TREE="exynos5250-snow"
CONFIG_CROS_EC=y
CONFIG_DM_CROS_EC=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SOCFPGA_ARRIA5=y
+CONFIG_ARM=y
+CONFIG_TARGET_SOCFPGA_ARRIA5=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_socdk"
CONFIG_DM=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SOCFPGA_CYCLONE5=y
+CONFIG_ARM=y
+CONFIG_TARGET_SOCFPGA_CYCLONE5=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socdk"
CONFIG_DM=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SOCFPGA_CYCLONE5=y
+CONFIG_ARM=y
+CONFIG_TARGET_SOCFPGA_CYCLONE5=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates"
CONFIG_DM=y
CONFIG_VIDEO_LCD_POWER="PH8"
CONFIG_VIDEO_LCD_BL_EN="PH7"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_SUNXI=y
-+S:CONFIG_MACH_SUN4I=y
-+S:CONFIG_DRAM_CLK=432
-+S:CONFIG_DRAM_ZQ=123
-+S:CONFIG_DRAM_EMR1=4
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN4I=y
+CONFIG_DRAM_CLK=432
+CONFIG_DRAM_ZQ=123
+CONFIG_DRAM_EMR1=4
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP34XX=y
-+S:CONFIG_TARGET_TAO3530=y
+CONFIG_ARM=y
+CONFIG_OMAP34XX=y
+CONFIG_TARGET_TAO3530=y
CONFIG_DM=n
CONFIG_DM_SERIAL=n
CONFIG_DM_GPIO=n
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2067,BOARD_TAURUS"
-+S:CONFIG_ARM=y
-+S:CONFIG_ARCH_AT91=y
-+S:CONFIG_TARGET_TAURUS=y
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_TAURUS=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TEGRA=y
-+S:CONFIG_TEGRA30=y
-+S:CONFIG_TARGET_TEC_NG=y
+CONFIG_ARM=y
+CONFIG_TEGRA=y
+CONFIG_TEGRA30=y
+CONFIG_TARGET_TEC_NG=y
CONFIG_DEFAULT_DEVICE_TREE="tegra30-tec-ng"
-+S:CONFIG_ARM=y
-+S:CONFIG_TEGRA=y
-+S:CONFIG_TEGRA20=y
-+S:CONFIG_TARGET_TEC=y
+CONFIG_ARM=y
+CONFIG_TEGRA=y
+CONFIG_TEGRA20=y
+CONFIG_TARGET_TEC=y
CONFIG_DEFAULT_DEVICE_TREE="tegra20-tec"
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_TI814X_EVM=y
+CONFIG_ARM=y
+CONFIG_TARGET_TI814X_EVM=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_TI816X_EVM=y
+CONFIG_ARM=y
+CONFIG_TARGET_TI816X_EVM=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP34XX=y
-+S:CONFIG_TARGET_TRICORDER=y
+CONFIG_ARM=y
+CONFIG_OMAP34XX=y
+CONFIG_TARGET_TRICORDER=y
CONFIG_DM=n
CONFIG_DM_SERIAL=n
CONFIG_DM_GPIO=n
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="FLASHCARD"
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP34XX=y
-+S:CONFIG_TARGET_TRICORDER=y
+CONFIG_ARM=y
+CONFIG_OMAP34XX=y
+CONFIG_TARGET_TRICORDER=y
CONFIG_DM=n
CONFIG_DM_SERIAL=n
CONFIG_DM_GPIO=n
-+S:CONFIG_ARM=y
-+S:CONFIG_TEGRA=y
-+S:CONFIG_TEGRA20=y
-+S:CONFIG_TARGET_TRIMSLICE=y
+CONFIG_ARM=y
+CONFIG_TEGRA=y
+CONFIG_TEGRA20=y
+CONFIG_TARGET_TRIMSLICE=y
CONFIG_DEFAULT_DEVICE_TREE="tegra20-trimslice"
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,EMMC_BOOT"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_TSERIES=y
+CONFIG_ARM=y
+CONFIG_TARGET_TSERIES=y
# CONFIG_CMD_CRC32 is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_TSERIES=y
+CONFIG_ARM=y
+CONFIG_TARGET_TSERIES=y
# CONFIG_CMD_CRC32 is not set
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,SPI_BOOT,EMMC_BOOT"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_TSERIES=y
+CONFIG_ARM=y
+CONFIG_TARGET_TSERIES=y
# CONFIG_CMD_CRC32 is not set
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_OMAP34XX=y
-+S:CONFIG_TARGET_TWISTER=y
+CONFIG_ARM=y
+CONFIG_OMAP34XX=y
+CONFIG_TARGET_TWISTER=y
CONFIG_DM=n
CONFIG_DM_SERIAL=n
CONFIG_DM_GPIO=n
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_TX25=y
+CONFIG_ARM=y
+CONFIG_TARGET_TX25=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TEGRA=y
-+S:CONFIG_TEGRA124=y
-+S:CONFIG_TARGET_VENICE2=y
+CONFIG_ARM=y
+CONFIG_TEGRA=y
+CONFIG_TEGRA124=y
+CONFIG_TARGET_VENICE2=y
CONFIG_DEFAULT_DEVICE_TREE="tegra124-venice2"
-+S:CONFIG_ARM=y
-+S:CONFIG_TEGRA=y
-+S:CONFIG_TEGRA20=y
-+S:CONFIG_TARGET_VENTANA=y
+CONFIG_ARM=y
+CONFIG_TEGRA=y
+CONFIG_TEGRA20=y
+CONFIG_TARGET_VENTANA=y
CONFIG_DEFAULT_DEVICE_TREE="tegra20-ventana"
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="ONENAND,RAM_256M"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_VPAC270=y
+CONFIG_ARM=y
+CONFIG_TARGET_VPAC270=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TEGRA=y
-+S:CONFIG_TEGRA20=y
-+S:CONFIG_TARGET_WHISTLER=y
+CONFIG_ARM=y
+CONFIG_TEGRA=y
+CONFIG_TEGRA20=y
+CONFIG_TARGET_WHISTLER=y
CONFIG_DEFAULT_DEVICE_TREE="tegra20-whistler"
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/woodburn/imximage.cfg"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_WOODBURN_SD=y
+CONFIG_ARM=y
+CONFIG_TARGET_WOODBURN_SD=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_X600=y
+CONFIG_ARM=y
+CONFIG_TARGET_X600=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_XFI3=y
+CONFIG_ARM=y
+CONFIG_TARGET_XFI3=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_ZYNQ=y
-+S:CONFIG_TARGET_ZYNQ_MICROZED=y
+CONFIG_ARM=y
+CONFIG_ZYNQ=y
+CONFIG_TARGET_ZYNQ_MICROZED=y
CONFIG_OF_CONTROL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_ZYNQ=y
-+S:CONFIG_TARGET_ZYNQ_ZC70X=y
+CONFIG_ARM=y
+CONFIG_ZYNQ=y
+CONFIG_TARGET_ZYNQ_ZC70X=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc702"
CONFIG_FIT=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM010"
-+S:CONFIG_ARM=y
-+S:CONFIG_ZYNQ=y
-+S:CONFIG_TARGET_ZYNQ_ZC770=y
+CONFIG_ARM=y
+CONFIG_ZYNQ=y
+CONFIG_TARGET_ZYNQ_ZC770=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm010"
CONFIG_FIT=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM012"
-+S:CONFIG_ARM=y
-+S:CONFIG_ZYNQ=y
-+S:CONFIG_TARGET_ZYNQ_ZC770=y
+CONFIG_ARM=y
+CONFIG_ZYNQ=y
+CONFIG_TARGET_ZYNQ_ZC770=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm012"
CONFIG_FIT=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM013"
-+S:CONFIG_ARM=y
-+S:CONFIG_ZYNQ=y
-+S:CONFIG_TARGET_ZYNQ_ZC770=y
+CONFIG_ARM=y
+CONFIG_ZYNQ=y
+CONFIG_TARGET_ZYNQ_ZC770=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm013"
CONFIG_FIT=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_ZYNQ=y
-+S:CONFIG_TARGET_ZYNQ_ZED=y
+CONFIG_ARM=y
+CONFIG_ZYNQ=y
+CONFIG_TARGET_ZYNQ_ZED=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-zed"
CONFIG_FIT=y
CONFIG_SPL=y
-+S:CONFIG_ARM=y
-+S:CONFIG_ZYNQ=y
-+S:CONFIG_TARGET_ZYNQ_ZYBO=y
+CONFIG_ARM=y
+CONFIG_ZYNQ=y
+CONFIG_TARGET_ZYNQ_ZYBO=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-zybo"
CONFIG_FIT=y
#ifndef _CONFIG_CMD_DISTRO_BOOTCMD_H
#define _CONFIG_CMD_DISTRO_BOOTCMD_H
+/*
+ * A note on error handling: It is possible for BOOT_TARGET_DEVICES to
+ * reference a device that is not enabled in the U-Boot configuration, e.g.
+ * it may include MMC in the list without CONFIG_CMD_MMC being enabled. Given
+ * that BOOT_TARGET_DEVICES is a macro that's expanded by the C pre-processor
+ * at compile time, it's not possible to detect and report such problems via
+ * a simple #ifdef/#error combination. Still, the code needs to report errors.
+ * The best way I've found to do this is to make BOOT_TARGET_DEVICES expand to
+ * reference a non-existent symbol, and have the name of that symbol encode
+ * the error message. Consequently, this file contains references to e.g.
+ * BOOT_TARGET_DEVICES_references_MMC_without_CONFIG_CMD_MMC. Given the
+ * prevalence of capitals here, this looks like a pre-processor macro and
+ * hence seems like it should be all capitals, but it's really an error
+ * message that includes some other pre-processor symbols in the text.
+ */
+
/* We need the part command */
#define CONFIG_PARTITION_UUIDS
#define CONFIG_CMD_PART
#endif /* CONFIG_MUSB_GADGET */
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT)
+/* Remove other SPL modes. */
+#undef CONFIG_SPL_YMODEM_SUPPORT
+#undef CONFIG_SPL_NAND_SUPPORT
+#undef CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_ENV_IS_NOWHERE
+#undef CONFIG_ENV_IS_IN_NAND
/* disable host part of MUSB in SPL */
#undef CONFIG_MUSB_HOST
/* disable EFI partitions and partition UUID support */
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP3_AM3517CRANE 1 /* working with CRANEBOARD */
#define CONFIG_OMAP_COMMON
+/* Common ARM Erratas */
+#define CONFIG_ARM_ERRATA_454179
+#define CONFIG_ARM_ERRATA_430973
+#define CONFIG_ARM_ERRATA_621766
#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
#include <asm/arch/cpu.h> /* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
/*
* Display CPU and Board information
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP3_AM3517EVM 1 /* working with AM3517EVM */
#define CONFIG_OMAP_COMMON
+/* Common ARM Erratas */
+#define CONFIG_ARM_ERRATA_454179
+#define CONFIG_ARM_ERRATA_430973
+#define CONFIG_ARM_ERRATA_621766
#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
#include <asm/arch/cpu.h> /* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
/*
* Display CPU and Board information
#define CONFIG_MII /* Required in net/eth.c */
#define CONFIG_PHY_GIGE /* per-board part of CPSW */
#define CONFIG_PHYLIB
+#define PHY_ANEG_TIMEOUT 8000 /* PHY needs longer aneg time at 1G */
#define CONFIG_SUPPORT_EMMC_BOOT
#define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */
#define CONFIG_OMAP_COMMON
#define CONFIG_SYS_GENERIC_BOARD
+/* Common ARM Erratas */
+#define CONFIG_ARM_ERRATA_454179
+#define CONFIG_ARM_ERRATA_430973
+#define CONFIG_ARM_ERRATA_621766
#define CONFIG_SDRC /* The chip has SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
/*
* Display CPU and Board information
#define CONFIG_CM_T3517 /* working with CM-T3517 */
#define CONFIG_OMAP_COMMON
#define CONFIG_SYS_GENERIC_BOARD
+/* Common ARM Erratas */
+#define CONFIG_ARM_ERRATA_454179
+#define CONFIG_ARM_ERRATA_430973
+#define CONFIG_ARM_ERRATA_621766
#define CONFIG_SYS_TEXT_BASE 0x80008000
#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
#include <asm/arch/cpu.h> /* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
/*
* Display CPU and Board information
#define MACH_TYPE_OMAP3_CPS 2751
#endif
#define CONFIG_MACH_TYPE MACH_TYPE_OMAP3_CPS
+/* Common ARM Erratas */
+#define CONFIG_ARM_ERRATA_454179
+#define CONFIG_ARM_ERRATA_430973
+#define CONFIG_ARM_ERRATA_621766
/*
* High Level Configuration Options
#define CONFIG_SDRC /* The chip has SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
/*
* Display CPU and Board information
#define CONFIG_OMAP3_MCX /* working with mcx */
#define CONFIG_OMAP_GPIO
#define CONFIG_OMAP_COMMON
+/* Common ARM Erratas */
+#define CONFIG_ARM_ERRATA_454179
+#define CONFIG_ARM_ERRATA_430973
+#define CONFIG_ARM_ERRATA_621766
#define MACH_TYPE_MCX 3656
#define CONFIG_MACH_TYPE MACH_TYPE_MCX
#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
#include <asm/arch/cpu.h> /* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
#define CONFIG_OF_LIBFDT
#define CONFIG_FIT
#define CONFIG_SYS_L2CACHE_OFF /* pretend there is no L2 CACHE */
#define CONFIG_OMAP_COMMON
#define CONFIG_SYS_GENERIC_BOARD
+/* Common ARM Erratas */
+#define CONFIG_ARM_ERRATA_454179
+#define CONFIG_ARM_ERRATA_430973
+#define CONFIG_ARM_ERRATA_621766
#define CONFIG_MACH_TYPE MACH_TYPE_NOKIA_RX51
#define CONFIG_SDRC /* The chip has SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
#include <asm/arch/mem.h>
#include <linux/stringify.h>
#define __OMAP3EVM_CONFIG_H
#include <asm/arch/cpu.h>
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
/* ----------------------------------------------------------------------------
* Supported U-boot commands
#define CONFIG_OMAP /* This is TI OMAP core */
#define CONFIG_OMAP_GPIO
#define CONFIG_OMAP_COMMON
+/* Common ARM Erratas */
+#define CONFIG_ARM_ERRATA_454179
+#define CONFIG_ARM_ERRATA_430973
+#define CONFIG_ARM_ERRATA_621766
#define CONFIG_SDRC /* The chip has SDRC controller */
#define __OMAP3_EVM_QUICK_MMC_H
#include <asm/arch/cpu.h>
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
/* ----------------------------------------------------------------------------
* Supported U-boot commands
#define __OMAP3_EVM_QUICK_NAND_H
#include <asm/arch/cpu.h>
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
/* ----------------------------------------------------------------------------
* Supported U-boot commands
#define CONFIG_OMAP3_LOGIC /* working with Logic OMAP boards */
#define CONFIG_OMAP_GPIO
#define CONFIG_OMAP_COMMON
+/* Common ARM Erratas */
+#define CONFIG_ARM_ERRATA_454179
+#define CONFIG_ARM_ERRATA_430973
+#define CONFIG_ARM_ERRATA_621766
#define CONFIG_SYS_TEXT_BASE 0x80400000
#define CONFIG_SDRC /* The chip has SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
/*
* Display CPU and Board information
#define CONFIG_MACH_TYPE MACH_TYPE_MVBLX
#define CONFIG_OMAP_GPIO
#define CONFIG_OMAP_COMMON
+/* Common ARM Erratas */
+#define CONFIG_ARM_ERRATA_454179
+#define CONFIG_ARM_ERRATA_430973
+#define CONFIG_ARM_ERRATA_621766
#define CONFIG_SDRC /* The chip has SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
/*
* Display CPU and Board information
#define CONFIG_OMAP3_PANDORA 1 /* working with pandora */
#define CONFIG_OMAP_GPIO
#define CONFIG_OMAP_COMMON
+/* Common ARM Erratas */
+#define CONFIG_ARM_ERRATA_454179
+#define CONFIG_ARM_ERRATA_430973
+#define CONFIG_ARM_ERRATA_621766
#define CONFIG_SDRC /* The chip has SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
/*
* Display CPU and Board information
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP3_3430SDP 1 /* working with SDP Rev2 */
#define CONFIG_OMAP_COMMON
+/* Common ARM Erratas */
+#define CONFIG_ARM_ERRATA_454179
+#define CONFIG_ARM_ERRATA_430973
+#define CONFIG_ARM_ERRATA_621766
#define CONFIG_SDRC /* The chip has SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
/*
* NOTE: these #defines presume standard SDP jumper settings.
#define CONFIG_NAND
#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
#include <asm/arch/cpu.h> /* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
#include <configs/ti_omap3_common.h>
/* Remove SPL boot option - we do not support that on LDP yet */
#define CONFIG_OMAP_GPIO
#define CONFIG_OMAP_COMMON
#define CONFIG_SYS_GENERIC_BOARD
+/* Common ARM Erratas */
+#define CONFIG_ARM_ERRATA_454179
+#define CONFIG_ARM_ERRATA_430973
+#define CONFIG_ARM_ERRATA_621766
#define CONFIG_SYS_TEXT_BASE 0x80008000
#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
#include <asm/arch/cpu.h> /* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
/*
* Display CPU and Board information
#define CONFIG_OMAP_GPIO
#define CONFIG_OMAP_COMMON
#define CONFIG_SYS_GENERIC_BOARD
+/* Common ARM Erratas */
+#define CONFIG_ARM_ERRATA_454179
+#define CONFIG_ARM_ERRATA_430973
+#define CONFIG_ARM_ERRATA_621766
#define MACH_TYPE_OMAP3_TAO3530 2836
#define CONFIG_SDRC /* Has an SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
/*
* Display CPU and Board information
#include <asm/arch/cpu.h>
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
#ifndef CONFIG_SPL_BUILD
# define CONFIG_OMAP_SERIAL
#endif
+/* Common ARM Erratas */
+#define CONFIG_ARM_ERRATA_454179
+#define CONFIG_ARM_ERRATA_430973
+#define CONFIG_ARM_ERRATA_621766
+
/* The chip has SDRC controller */
#define CONFIG_SDRC
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_ARCH_CPU_INIT
+/* Common ARM Erratas */
+#define CONFIG_ARM_ERRATA_798870
+
#define CONFIG_SYS_CACHELINE_SIZE 64
/* Use General purpose timer 1 */
/* High Level Configuration Options */
#define CONFIG_OMAP /* in a TI OMAP core */
#define CONFIG_OMAP_COMMON
+/* Common ARM Erratas */
+#define CONFIG_ARM_ERRATA_454179
+#define CONFIG_ARM_ERRATA_430973
+#define CONFIG_ARM_ERRATA_621766
#define CONFIG_MACH_TYPE MACH_TYPE_TRICORDER
/*
#define CONFIG_SDRC /* The chip has SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
#define CONFIG_SYS_GENERIC_BOARD