reset: stm32: adapt driver for stm32mp1

- move to livetree and allow to get address to parent
- add stm32mp1 compatible for probe

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>

diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 3964b9eb6e18b208c689e731e23edb42c96b4b22..71a786bab51ad8809f6f057e9a81566f9c8c45ad 100644 (file)
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -30,7 +30,7 @@ config STI_RESET
 
 config STM32_RESET
        bool "Enable the STM32 reset"
-       depends on STM32
+       depends on STM32 || ARCH_STM32MP
        help
          Support for reset controllers on STMicroelectronics STM32 family SoCs.
          This resset driver is compatible with STM32 F4/F7 and H7 SoCs.

diff --git a/drivers/reset/stm32-reset.c b/drivers/reset/stm32-reset.c
index b266f46263c55db31fa1c3b0821bb0495ca63e4b..e98f34b0370ec36cb842cc26b59f17897de541fb 100644 (file)
--- a/drivers/reset/stm32-reset.c
+++ b/drivers/reset/stm32-reset.c
@@ -11,7 +11,13 @@
 #include <reset-uclass.h>
 #include <asm/io.h>
 
-DECLARE_GLOBAL_DATA_PTR;
+/* reset clear offset for STM32MP RCC */
+#define RCC_CL 0x4
+
+enum rcc_type {
+       RCC_STM32 = 0,
+       RCC_STM32MP,
+};
 
 struct stm32_reset_priv {
        fdt_addr_t base;
@@ -35,7 +41,11 @@ static int stm32_reset_assert(struct reset_ctl *reset_ctl)
        debug("%s: reset id = %ld bank = %d offset = %d)\n", __func__,
              reset_ctl->id, bank, offset);
 
-       setbits_le32(priv->base + bank, BIT(offset));
+       if (dev_get_driver_data(reset_ctl->dev) == RCC_STM32MP)
+               /* reset assert is done in rcc set register */
+               writel(BIT(offset), priv->base + bank);
+       else
+               setbits_le32(priv->base + bank, BIT(offset));
 
        return 0;
 }
@@ -48,7 +58,11 @@ static int stm32_reset_deassert(struct reset_ctl *reset_ctl)
        debug("%s: reset id = %ld bank = %d offset = %d)\n", __func__,
              reset_ctl->id, bank, offset);
 
-       clrbits_le32(priv->base + bank, BIT(offset));
+       if (dev_get_driver_data(reset_ctl->dev) == RCC_STM32MP)
+               /* reset deassert is done in rcc clr register */
+               writel(BIT(offset), priv->base + bank + RCC_CL);
+       else
+               clrbits_le32(priv->base + bank, BIT(offset));
 
        return 0;
 }
@@ -64,16 +78,26 @@ static int stm32_reset_probe(struct udevice *dev)
 {
        struct stm32_reset_priv *priv = dev_get_priv(dev);
 
-       priv->base = devfdt_get_addr(dev);
-       if (priv->base == FDT_ADDR_T_NONE)
-               return -EINVAL;
+       priv->base = dev_read_addr(dev);
+       if (priv->base == FDT_ADDR_T_NONE) {
+               /* for MFD, get address of parent */
+               priv->base = dev_read_addr(dev->parent);
+               if (priv->base == FDT_ADDR_T_NONE)
+                       return -EINVAL;
+       }
 
        return 0;
 }
 
+static const struct udevice_id stm32_reset_ids[] = {
+       { .compatible = "st,stm32mp1-rcc-rst", .data = RCC_STM32MP },
+       { }
+};
+
 U_BOOT_DRIVER(stm32_rcc_reset) = {
        .name                   = "stm32_rcc_reset",
        .id                     = UCLASS_RESET,
+       .of_match               = stm32_reset_ids,
        .probe                  = stm32_reset_probe,
        .priv_auto_alloc_size   = sizeof(struct stm32_reset_priv),
        .ops                    = &stm32_reset_ops,