LIB = $(obj)libomap-common.a
SOBJS := reset.o
+
COBJS := timer.o
+COBJS += syslib.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
reset_cpu:
ldr r1, rstctl @ get addr for global reset
@ reg
- mov r3, #0x2 @ full reset pll + mpu
+ ldr r3, rstbit @ sw reset bit
str r3, [r1] @ force reset
mov r0, r0
_loop_forever:
b _loop_forever
rstctl:
.word PRM_RSTCTRL
+rstbit:
+ .word PRM_RSTCTRL_RESET
--- /dev/null
+/*
+ * (C) Copyright 2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+
+/************************************************************
+ * sdelay() - simple spin loop. Will be constant time as
+ * its generally used in bypass conditions only. This
+ * is necessary until timers are accessible.
+ *
+ * not inline to increase chances its in cache when called
+ *************************************************************/
+void sdelay(unsigned long loops)
+{
+ __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
+ "bne 1b":"=r" (loops):"0"(loops));
+}
+
+/*****************************************************************
+ * sr32 - clear & set a value in a bit range for a 32 bit address
+ *****************************************************************/
+void sr32(void *addr, u32 start_bit, u32 num_bits, u32 value)
+{
+ u32 tmp, msk = 0;
+ msk = 1 << num_bits;
+ --msk;
+ tmp = readl((u32)addr) & ~(msk << start_bit);
+ tmp |= value << start_bit;
+ writel(tmp, (u32)addr);
+}
+
+/*********************************************************************
+ * wait_on_value() - common routine to allow waiting for changes in
+ * volatile regs.
+ *********************************************************************/
+u32 wait_on_value(u32 read_bit_mask, u32 match_value, void *read_addr,
+ u32 bound)
+{
+ u32 i = 0, val;
+ do {
+ ++i;
+ val = readl((u32)read_addr) & read_bit_mask;
+ if (val == match_value)
+ return 1;
+ if (i == bound)
+ return 0;
+ } while (1);
+}
COBJS += clock.o
COBJS += gpio.o
COBJS += mem.o
-COBJS += syslib.o
COBJS += sys_info.o
COBJS-$(CONFIG_EMIF4) += emif4.o
__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
}
-/******************************************************************************
- * Routine: setup_auxcr()
- * Description: Write to AuxCR desired value using SMI.
- * general use.
- *****************************************************************************/
-void setup_auxcr()
-{
- unsigned long i;
- volatile unsigned int j;
- /* Save r0, r12 and restore them after usage */
- __asm__ __volatile__("mov %0, r12":"=r"(j));
- __asm__ __volatile__("mov %0, r0":"=r"(i));
-
- /*
- * GP Device ROM code API usage here
- * r12 = AUXCR Write function and r0 value
- */
- __asm__ __volatile__("mov r12, #0x3");
- __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
- /* Enabling ASA */
- __asm__ __volatile__("orr r0, r0, #0x10");
- /* Enable L1NEON */
- __asm__ __volatile__("orr r0, r0, #1 << 5");
- /* SMI instruction to call ROM Code API */
- __asm__ __volatile__(".word 0xE1600070");
- /* Set PLD_FWD bit in L2AUXCR (Cortex-A8 erratum 725233 workaround) */
- __asm__ __volatile__("mov r12, #0x2");
- __asm__ __volatile__("mrc p15, 1, r0, c9, c0, 2");
- __asm__ __volatile__("orr r0, r0, #1 << 27");
- /* SMI instruction to call ROM Code API */
- __asm__ __volatile__(".word 0xE1600070");
- __asm__ __volatile__("mov r0, %0":"=r"(i));
- __asm__ __volatile__("mov r12, %0":"=r"(j));
-}
-
/******************************************************************************
* Routine: try_unlock_sram()
* Description: If chip is GP/EMU(special) type, unlock the SRAM for
.global invalidate_dcache
.global l2_cache_enable
.global l2_cache_disable
+.global setup_auxcr
/*
* invalidate_dcache()
ldmfd r13!, {r0 - r5, r7, r9 - r12, pc}
-
-l2_cache_enable:
- stmfd r13!, {r0, r1, r2, lr}
- @ ES2 onwards we can disable/enable L2 ourselves
+l2_cache_set:
+ stmfd r13!, {r4 - r6, lr}
+ mov r5, r0
bl get_cpu_rev
- cmp r0, #CPU_3XX_ES20
- blt l2_cache_disable_EARLIER_THAN_ES2
- mrc 15, 0, r3, cr1, cr0, 1
- orr r3, r3, #2
- mcr 15, 0, r3, cr1, cr0, 1
- b l2_cache_enable_END
-l2_cache_enable_EARLIER_THAN_ES2:
- @ Save r0, r12 and restore them after usage
- mov r3, ip
- str r3, [sp, #4]
- mov r3, r0
- @
+ mov r4, r0
+ bl get_cpu_family
+ @ ES2 onwards we can disable/enable L2 ourselves
+ cmp r0, #CPU_OMAP34XX
+ cmpeq r4, #CPU_3XX_ES10
+ mrc 15, 0, r0, cr1, cr0, 1
+ bic r0, r0, #2
+ orr r0, r0, r5, lsl #1
+ mcreq 15, 0, r0, cr1, cr0, 1
@ GP Device ROM code API usage here
@ r12 = AUXCR Write function and r0 value
- @
mov ip, #3
- mrc 15, 0, r0, cr1, cr0, 1
- orr r0, r0, #2
- @ SMI instruction to call ROM Code API
- .word 0xe1600070
- mov r0, r3
- mov ip, r3
- str r3, [sp, #4]
-l2_cache_enable_END:
- ldmfd r13!, {r1, r2, r3, pc}
+ @ SMCNE instruction to call ROM Code API
+ .word 0x11600070
+ ldmfd r13!, {r4 - r6, pc}
+l2_cache_enable:
+ mov r0, #1
+ b l2_cache_set
l2_cache_disable:
- stmfd r13!, {r0, r1, r2, lr}
- @ ES2 onwards we can disable/enable L2 ourselves
- bl get_cpu_rev
- cmp r0, #CPU_3XX_ES20
- blt l2_cache_disable_EARLIER_THAN_ES2
- mrc 15, 0, r3, cr1, cr0, 1
- bic r3, r3, #2
- mcr 15, 0, r3, cr1, cr0, 1
- b l2_cache_disable_END
-l2_cache_disable_EARLIER_THAN_ES2:
- @ Save r0, r12 and restore them after usage
- mov r3, ip
- str r3, [sp, #4]
- mov r3, r0
- @
- @ GP Device ROM code API usage here
- @ r12 = AUXCR Write function and r0 value
- @
- mov ip, #3
- mrc 15, 0, r0, cr1, cr0, 1
- bic r0, r0, #2
- @ SMI instruction to call ROM Code API
- .word 0xe1600070
- mov r0, r3
- mov ip, r3
- str r3, [sp, #4]
-l2_cache_disable_END:
- ldmfd r13!, {r1, r2, r3, pc}
+ mov r0, #0
+ b l2_cache_set
+
+/******************************************************************************
+ * Routine: setup_auxcr()
+ * Description: Write to AuxCR desired value using SMI.
+ * general use.
+ *****************************************************************************/
+setup_auxcr:
+ mrc p15, 0, r0, c0, c0, 0 @ read main ID register
+ and r2, r0, #0x00f00000 @ variant
+ and r3, r0, #0x0000000f @ revision
+ orr r1, r3, r2, lsr #20-4 @ combine variant and revision
+ mov r12, #0x3
+ mrc p15, 0, r0, c1, c0, 1
+ orr r0, r0, #0x10 @ Enable ASA
+ @ Enable L1NEON on pre-r2p1 (erratum 621766 workaround)
+ cmp r1, #0x21
+ orrlt r0, r0, #1 << 5
+ .word 0xE1600070 @ SMC
+ mov r12, #0x2
+ mrc p15, 1, r0, c9, c0, 2
+ @ Set PLD_FWD bit in L2AUXCR on pre-r2p1 (erratum 725233 workaround)
+ cmp r1, #0x21
+ orrlt r0, r0, #1 << 27
+ .word 0xE1600070 @ SMC
+ bx lr
+
if (val & SYSCLKDIV_2)
cdiv = 2;
- else if (val & SYSCLKDIV_1)
- cdiv = 1;
else
- /*
- * Should never reach here! (Assume divider as 1)
- */
cdiv = 1;
/* enable timer2 */
while (readl(&s32k_base->s32k_cr) < (start + 20)) ;
cend = readl(&gpt1_base->tcrr); /* get end sys_clk count */
cdiff = cend - cstart; /* get elapsed ticks */
-
- if (cdiv == 2)
- {
- cdiff *= 2;
- }
+ cdiff *= cdiv;
/* based on number of ticks assign speed */
if (cdiff > 19000)
}
}
-/******************************************************************************
- * prcm_init() - inits clocks for PRCM as defined in clocks.h
- * called from SRAM, or Flash (using temp SRAM stack).
- *****************************************************************************/
-void prcm_init(void)
+/*
+ * OMAP34XX/35XX specific functions
+ */
+
+static void dpll3_init_34xx(u32 sil_index, u32 clk_index)
{
+ struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+ dpll_param *ptr = (dpll_param *) get_core_dpll_param();
void (*f_lock_pll) (u32, u32, u32, u32);
int xip_safe, p0, p1, p2, p3;
- u32 osc_clk = 0, sys_clkin_sel;
- u32 clk_index, sil_index = 0;
- struct prm *prm_base = (struct prm *)PRM_BASE;
- struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
- dpll_param *dpll_param_p;
-
- f_lock_pll = (void *) ((u32) &_end_vect - (u32) &_start +
- SRAM_VECT_CODE);
xip_safe = is_running_in_sram();
- /*
- * Gauge the input clock speed and find out the sys_clkin_sel
- * value corresponding to the input clock.
- */
- osc_clk = get_osc_clk_speed();
- get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
-
- /* set input crystal speed */
- sr32(&prm_base->clksel, 0, 3, sys_clkin_sel);
+ /* Moving to the right sysclk and ES rev base */
+ ptr = ptr + (3 * clk_index) + sil_index;
- /* If the input clock is greater than 19.2M always divide/2 */
- if (sys_clkin_sel > 2) {
- /* input clock divider */
- sr32(&prm_base->clksrc_ctrl, 6, 2, 2);
- clk_index = sys_clkin_sel / 2;
- } else {
- /* input clock divider */
- sr32(&prm_base->clksrc_ctrl, 6, 2, 1);
- clk_index = sys_clkin_sel;
- }
-
- /*
- * The DPLL tables are defined according to sysclk value and
- * silicon revision. The clk_index value will be used to get
- * the values for that input sysclk from the DPLL param table
- * and sil_index will get the values for that SysClk for the
- * appropriate silicon rev.
- */
- if (get_cpu_rev())
- sil_index = 1;
-
- /* Unlock MPU DPLL (slows things down, and needed later) */
- sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS);
- wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu, LDELAY);
-
- /* Getting the base address of Core DPLL param table */
- dpll_param_p = (dpll_param *) get_core_dpll_param();
-
- /* Moving it to the right sysclk and ES rev base */
- dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
if (xip_safe) {
/*
* CORE DPLL
* work. write another value and then default value.
*/
- /* m3x2 */
- sr32(&prcm_base->clksel1_emu, 16, 5, CORE_M3X2 + 1);
- /* m3x2 */
+ /* CM_CLKSEL1_EMU[DIV_DPLL3] */
+ sr32(&prcm_base->clksel1_emu, 16, 5, (CORE_M3X2 + 1)) ;
sr32(&prcm_base->clksel1_emu, 16, 5, CORE_M3X2);
- /* Set M2 */
- sr32(&prcm_base->clksel1_pll, 27, 2, dpll_param_p->m2);
- /* Set M */
- sr32(&prcm_base->clksel1_pll, 16, 11, dpll_param_p->m);
- /* Set N */
- sr32(&prcm_base->clksel1_pll, 8, 7, dpll_param_p->n);
- /* 96M Src */
+
+ /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
+ sr32(&prcm_base->clksel1_pll, 27, 5, ptr->m2);
+
+ /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
+ sr32(&prcm_base->clksel1_pll, 16, 11, ptr->m);
+
+ /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
+ sr32(&prcm_base->clksel1_pll, 8, 7, ptr->n);
+
+ /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
sr32(&prcm_base->clksel1_pll, 6, 1, 0);
- /* ssi */
+
+ /* SSI */
sr32(&prcm_base->clksel_core, 8, 4, CORE_SSI_DIV);
- /* fsusb */
+ /* FSUSB */
sr32(&prcm_base->clksel_core, 4, 2, CORE_FUSB_DIV);
- /* l4 */
+ /* L4 */
sr32(&prcm_base->clksel_core, 2, 2, CORE_L4_DIV);
- /* l3 */
+ /* L3 */
sr32(&prcm_base->clksel_core, 0, 2, CORE_L3_DIV);
- /* gfx */
- sr32(&prcm_base->clksel_gfx, 0, 3, GFX_DIV);
- /* reset mgr */
+ /* GFX */
+ sr32(&prcm_base->clksel_gfx, 0, 3, GFX_DIV);
+ /* RESET MGR */
sr32(&prcm_base->clksel_wkup, 1, 2, WKUP_RSM);
- /* FREQSEL */
- sr32(&prcm_base->clken_pll, 4, 4, dpll_param_p->fsel);
- /* lock mode */
- sr32(&prcm_base->clken_pll, 0, 3, PLL_LOCK);
+ /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
+ sr32(&prcm_base->clken_pll, 4, 4, ptr->fsel);
+ /* LOCK MODE */
+ sr32(&prcm_base->clken_pll, 0, 3, PLL_LOCK);
wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen,
LDELAY);
* if running from flash, jump to small relocated code
* area in SRAM.
*/
+ f_lock_pll = (void *) ((u32) &_end_vect - (u32) &_start +
+ SRAM_VECT_CODE);
+
p0 = readl(&prcm_base->clken_pll);
sr32(&p0, 0, 3, PLL_FAST_RELOCK_BYPASS);
- sr32(&p0, 4, 4, dpll_param_p->fsel); /* FREQSEL */
+ /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
+ sr32(&p0, 4, 4, ptr->fsel);
p1 = readl(&prcm_base->clksel1_pll);
- sr32(&p1, 27, 2, dpll_param_p->m2); /* Set M2 */
- sr32(&p1, 16, 11, dpll_param_p->m); /* Set M */
- sr32(&p1, 8, 7, dpll_param_p->n); /* Set N */
- sr32(&p1, 6, 1, 0); /* set source for 96M */
+ /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
+ sr32(&p1, 27, 5, ptr->m2);
+ /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
+ sr32(&p1, 16, 11, ptr->m);
+ /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
+ sr32(&p1, 8, 7, ptr->n);
+ /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
+ sr32(&p1, 6, 1, 0);
p2 = readl(&prcm_base->clksel_core);
- sr32(&p2, 8, 4, CORE_SSI_DIV); /* ssi */
- sr32(&p2, 4, 2, CORE_FUSB_DIV); /* fsusb */
- sr32(&p2, 2, 2, CORE_L4_DIV); /* l4 */
- sr32(&p2, 0, 2, CORE_L3_DIV); /* l3 */
+ /* SSI */
+ sr32(&p2, 8, 4, CORE_SSI_DIV);
+ /* FSUSB */
+ sr32(&p2, 4, 2, CORE_FUSB_DIV);
+ /* L4 */
+ sr32(&p2, 2, 2, CORE_L4_DIV);
+ /* L3 */
+ sr32(&p2, 0, 2, CORE_L3_DIV);
p3 = (u32)&prcm_base->idlest_ckgen;
(*f_lock_pll) (p0, p1, p2, p3);
}
+}
- /* PER DPLL */
- sr32(&prcm_base->clken_pll, 16, 3, PLL_STOP);
- wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY);
-
- /* Getting the base address to PER DPLL param table */
-
- /* Set N */
- dpll_param_p = (dpll_param *) get_per_dpll_param();
+static void dpll4_init_34xx(u32 sil_index, u32 clk_index)
+{
+ struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+ dpll_param *ptr = (dpll_param *) get_per_dpll_param();
/* Moving it to the right sysclk base */
- dpll_param_p = dpll_param_p + clk_index;
+ ptr = ptr + clk_index;
+
+ /* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */
+ sr32(&prcm_base->clken_pll, 16, 3, PLL_STOP);
+ wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY);
/*
* Errata 1.50 Workaround for OMAP3 ES1.0 only
* If using default divisors, write default divisor + 1
* and then the actual divisor value
*/
- sr32(&prcm_base->clksel1_emu, 24, 5, PER_M6X2 + 1); /* set M6 */
- sr32(&prcm_base->clksel1_emu, 24, 5, PER_M6X2); /* set M6 */
- sr32(&prcm_base->clksel_cam, 0, 5, PER_M5X2 + 1); /* set M5 */
- sr32(&prcm_base->clksel_cam, 0, 5, PER_M5X2); /* set M5 */
- sr32(&prcm_base->clksel_dss, 0, 5, PER_M4X2 + 1); /* set M4 */
- sr32(&prcm_base->clksel_dss, 0, 5, PER_M4X2); /* set M4 */
- sr32(&prcm_base->clksel_dss, 8, 5, PER_M3X2 + 1); /* set M3 */
- sr32(&prcm_base->clksel_dss, 8, 5, PER_M3X2); /* set M3 */
- sr32(&prcm_base->clksel3_pll, 0, 5, dpll_param_p->m2 + 1); /* set M2 */
- sr32(&prcm_base->clksel3_pll, 0, 5, dpll_param_p->m2); /* set M2 */
+ /* M6 */
+ sr32(&prcm_base->clksel1_emu, 24, 5, (PER_M6X2 + 1));
+ sr32(&prcm_base->clksel1_emu, 24, 5, PER_M6X2);
+ /* M5 */
+ sr32(&prcm_base->clksel_cam, 0, 5, (PER_M5X2 + 1));
+ sr32(&prcm_base->clksel_cam, 0, 5, PER_M5X2);
+ /* M4 */
+ sr32(&prcm_base->clksel_dss, 0, 5, (PER_M4X2 + 1));
+ sr32(&prcm_base->clksel_dss, 0, 5, PER_M4X2);
+ /* M3 */
+ sr32(&prcm_base->clksel_dss, 8, 5, (PER_M3X2 + 1));
+ sr32(&prcm_base->clksel_dss, 8, 5, PER_M3X2);
+ /* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */
+ sr32(&prcm_base->clksel3_pll, 0, 5, (ptr->m2 + 1));
+ sr32(&prcm_base->clksel3_pll, 0, 5, ptr->m2);
/* Workaround end */
- sr32(&prcm_base->clksel2_pll, 8, 11, dpll_param_p->m); /* set m */
- sr32(&prcm_base->clksel2_pll, 0, 7, dpll_param_p->n); /* set n */
- sr32(&prcm_base->clken_pll, 20, 4, dpll_param_p->fsel); /* FREQSEL */
- sr32(&prcm_base->clken_pll, 16, 3, PLL_LOCK); /* lock mode */
+ /* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:18] */
+ sr32(&prcm_base->clksel2_pll, 8, 11, ptr->m);
+
+ /* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */
+ sr32(&prcm_base->clksel2_pll, 0, 7, ptr->n);
+
+ /* FREQSEL (PERIPH_DPLL_FREQSEL): CM_CLKEN_PLL[20:23] */
+ sr32(&prcm_base->clken_pll, 20, 4, ptr->fsel);
+
+ /* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */
+ sr32(&prcm_base->clken_pll, 16, 3, PLL_LOCK);
wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY);
+}
- /* Getting the base address to MPU DPLL param table */
- dpll_param_p = (dpll_param *) get_mpu_dpll_param();
+static void mpu_init_34xx(u32 sil_index, u32 clk_index)
+{
+ struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+ dpll_param *ptr = (dpll_param *) get_mpu_dpll_param();
- /* Moving it to the right sysclk and ES rev base */
- dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
+ /* Moving to the right sysclk and ES rev base */
+ ptr = ptr + (3 * clk_index) + sil_index;
/* MPU DPLL (unlocked already) */
- /* Set M2 */
- sr32(&prcm_base->clksel2_pll_mpu, 0, 5, dpll_param_p->m2);
- /* Set M */
- sr32(&prcm_base->clksel1_pll_mpu, 8, 11, dpll_param_p->m);
- /* Set N */
- sr32(&prcm_base->clksel1_pll_mpu, 0, 7, dpll_param_p->n);
- /* FREQSEL */
- sr32(&prcm_base->clken_pll_mpu, 4, 4, dpll_param_p->fsel);
- /* lock mode */
- sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOCK);
- wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu, LDELAY);
-
- /* Getting the base address to IVA DPLL param table */
- dpll_param_p = (dpll_param *) get_iva_dpll_param();
-
- /* Moving it to the right sysclk and ES rev base */
- dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
-
- /* IVA DPLL (set to 12*20=240MHz) */
+ /* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */
+ sr32(&prcm_base->clksel2_pll_mpu, 0, 5, ptr->m2);
+
+ /* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */
+ sr32(&prcm_base->clksel1_pll_mpu, 8, 11, ptr->m);
+
+ /* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */
+ sr32(&prcm_base->clksel1_pll_mpu, 0, 7, ptr->n);
+
+ /* FREQSEL (MPU_DPLL_FREQSEL) : CM_CLKEN_PLL_MPU[4:7] */
+ sr32(&prcm_base->clken_pll_mpu, 4, 4, ptr->fsel);
+}
+
+static void iva_init_34xx(u32 sil_index, u32 clk_index)
+{
+ struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+ dpll_param *ptr = (dpll_param *) get_iva_dpll_param();
+
+ /* Moving to the right sysclk and ES rev base */
+ ptr = ptr + (3 * clk_index) + sil_index;
+
+ /* IVA DPLL */
+ /* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */
+ sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_STOP);
+ wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY);
+
+ /* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */
+ sr32(&prcm_base->clksel2_pll_iva2, 0, 5, ptr->m2);
+
+ /* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */
+ sr32(&prcm_base->clksel1_pll_iva2, 8, 11, ptr->m);
+
+ /* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */
+ sr32(&prcm_base->clksel1_pll_iva2, 0, 7, ptr->n);
+
+ /* FREQSEL (IVA2_DPLL_FREQSEL) : CM_CLKEN_PLL_IVA2[4:7] */
+ sr32(&prcm_base->clken_pll_iva2, 4, 4, ptr->fsel);
+
+ /* LOCK MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */
+ sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_LOCK);
+
+ wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY);
+}
+
+/*
+ * OMAP3630 specific functions
+ */
+
+static void dpll3_init_36xx(u32 sil_index, u32 clk_index)
+{
+ struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+ dpll_param *ptr = (dpll_param *) get_36x_core_dpll_param();
+ void (*f_lock_pll) (u32, u32, u32, u32);
+ int xip_safe, p0, p1, p2, p3;
+
+ xip_safe = is_running_in_sram();
+
+ /* Moving it to the right sysclk base */
+ ptr += clk_index;
+
+ if (xip_safe) {
+ /* CORE DPLL */
+
+ /* Select relock bypass: CM_CLKEN_PLL[0:2] */
+ sr32(&prcm_base->clken_pll, 0, 3, PLL_FAST_RELOCK_BYPASS);
+ wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen,
+ LDELAY);
+
+ /* CM_CLKSEL1_EMU[DIV_DPLL3] */
+ sr32(&prcm_base->clksel1_emu, 16, 5, CORE_M3X2);
+
+ /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
+ sr32(&prcm_base->clksel1_pll, 27, 5, ptr->m2);
+
+ /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
+ sr32(&prcm_base->clksel1_pll, 16, 11, ptr->m);
+
+ /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
+ sr32(&prcm_base->clksel1_pll, 8, 7, ptr->n);
+
+ /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
+ sr32(&prcm_base->clksel1_pll, 6, 1, 0);
+
+ /* SSI */
+ sr32(&prcm_base->clksel_core, 8, 4, CORE_SSI_DIV);
+ /* FSUSB */
+ sr32(&prcm_base->clksel_core, 4, 2, CORE_FUSB_DIV);
+ /* L4 */
+ sr32(&prcm_base->clksel_core, 2, 2, CORE_L4_DIV);
+ /* L3 */
+ sr32(&prcm_base->clksel_core, 0, 2, CORE_L3_DIV);
+ /* GFX */
+ sr32(&prcm_base->clksel_gfx, 0, 3, GFX_DIV);
+ /* RESET MGR */
+ sr32(&prcm_base->clksel_wkup, 1, 2, WKUP_RSM);
+ /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
+ sr32(&prcm_base->clken_pll, 4, 4, ptr->fsel);
+ /* LOCK MODE */
+ sr32(&prcm_base->clken_pll, 0, 3, PLL_LOCK);
+
+ wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen,
+ LDELAY);
+ } else if (is_running_in_flash()) {
+ /*
+ * if running from flash, jump to small relocated code
+ * area in SRAM.
+ */
+ f_lock_pll = (void *) ((u32) &_end_vect - (u32) &_start +
+ SRAM_VECT_CODE);
+
+ p0 = readl(&prcm_base->clken_pll);
+ sr32(&p0, 0, 3, PLL_FAST_RELOCK_BYPASS);
+ /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
+ sr32(&p0, 4, 4, ptr->fsel);
+
+ p1 = readl(&prcm_base->clksel1_pll);
+ /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
+ sr32(&p1, 27, 5, ptr->m2);
+ /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
+ sr32(&p1, 16, 11, ptr->m);
+ /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
+ sr32(&p1, 8, 7, ptr->n);
+ /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
+ sr32(&p1, 6, 1, 0);
+
+ p2 = readl(&prcm_base->clksel_core);
+ /* SSI */
+ sr32(&p2, 8, 4, CORE_SSI_DIV);
+ /* FSUSB */
+ sr32(&p2, 4, 2, CORE_FUSB_DIV);
+ /* L4 */
+ sr32(&p2, 2, 2, CORE_L4_DIV);
+ /* L3 */
+ sr32(&p2, 0, 2, CORE_L3_DIV);
+
+ p3 = (u32)&prcm_base->idlest_ckgen;
+
+ (*f_lock_pll) (p0, p1, p2, p3);
+ }
+}
+
+static void dpll4_init_36xx(u32 sil_index, u32 clk_index)
+{
+ struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+ struct dpll_per_36x_param *ptr;
+
+ ptr = (struct dpll_per_36x_param *)get_36x_per_dpll_param();
+
+ /* Moving it to the right sysclk base */
+ ptr += clk_index;
+
+ /* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */
+ sr32(&prcm_base->clken_pll, 16, 3, PLL_STOP);
+ wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY);
+
+ /* M6 (DIV_DPLL4): CM_CLKSEL1_EMU[24:29] */
+ sr32(&prcm_base->clksel1_emu, 24, 6, ptr->m6);
+
+ /* M5 (CLKSEL_CAM): CM_CLKSEL1_EMU[0:5] */
+ sr32(&prcm_base->clksel_cam, 0, 6, ptr->m5);
+
+ /* M4 (CLKSEL_DSS1): CM_CLKSEL_DSS[0:5] */
+ sr32(&prcm_base->clksel_dss, 0, 6, ptr->m4);
+
+ /* M3 (CLKSEL_DSS1): CM_CLKSEL_DSS[8:13] */
+ sr32(&prcm_base->clksel_dss, 8, 6, ptr->m3);
+
+ /* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */
+ sr32(&prcm_base->clksel3_pll, 0, 5, ptr->m2);
+
+ /* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:19] */
+ sr32(&prcm_base->clksel2_pll, 8, 12, ptr->m);
+
+ /* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */
+ sr32(&prcm_base->clksel2_pll, 0, 7, ptr->n);
+
+ /* M2DIV (CLKSEL_96M): CM_CLKSEL_CORE[12:13] */
+ sr32(&prcm_base->clksel_core, 12, 2, ptr->m2div);
+
+ /* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */
+ sr32(&prcm_base->clken_pll, 16, 3, PLL_LOCK);
+ wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY);
+}
+
+static void mpu_init_36xx(u32 sil_index, u32 clk_index)
+{
+ struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+ dpll_param *ptr = (dpll_param *) get_36x_mpu_dpll_param();
+
+ /* Moving to the right sysclk */
+ ptr += clk_index;
+
+ /* MPU DPLL (unlocked already */
+
+ /* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */
+ sr32(&prcm_base->clksel2_pll_mpu, 0, 5, ptr->m2);
+
+ /* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */
+ sr32(&prcm_base->clksel1_pll_mpu, 8, 11, ptr->m);
+
+ /* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */
+ sr32(&prcm_base->clksel1_pll_mpu, 0, 7, ptr->n);
+}
+
+static void iva_init_36xx(u32 sil_index, u32 clk_index)
+{
+ struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+ dpll_param *ptr = (dpll_param *)get_36x_iva_dpll_param();
+
+ /* Moving to the right sysclk */
+ ptr += clk_index;
+
+ /* IVA DPLL */
+ /* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */
sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_STOP);
wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY);
- /* set M2 */
- sr32(&prcm_base->clksel2_pll_iva2, 0, 5, dpll_param_p->m2);
- /* set M */
- sr32(&prcm_base->clksel1_pll_iva2, 8, 11, dpll_param_p->m);
- /* set N */
- sr32(&prcm_base->clksel1_pll_iva2, 0, 7, dpll_param_p->n);
- /* FREQSEL */
- sr32(&prcm_base->clken_pll_iva2, 4, 4, dpll_param_p->fsel);
- /* lock mode */
+
+ /* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */
+ sr32(&prcm_base->clksel2_pll_iva2, 0, 5, ptr->m2);
+
+ /* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */
+ sr32(&prcm_base->clksel1_pll_iva2, 8, 11, ptr->m);
+
+ /* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */
+ sr32(&prcm_base->clksel1_pll_iva2, 0, 7, ptr->n);
+
+ /* LOCK (MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */
sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_LOCK);
+
wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY);
+}
+
+/******************************************************************************
+ * prcm_init() - inits clocks for PRCM as defined in clocks.h
+ * called from SRAM, or Flash (using temp SRAM stack).
+ *****************************************************************************/
+void prcm_init(void)
+{
+ u32 osc_clk = 0, sys_clkin_sel;
+ u32 clk_index, sil_index = 0;
+ struct prm *prm_base = (struct prm *)PRM_BASE;
+ struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+
+ /*
+ * Gauge the input clock speed and find out the sys_clkin_sel
+ * value corresponding to the input clock.
+ */
+ osc_clk = get_osc_clk_speed();
+ get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
+
+ /* set input crystal speed */
+ sr32(&prm_base->clksel, 0, 3, sys_clkin_sel);
+
+ /* If the input clock is greater than 19.2M always divide/2 */
+ if (sys_clkin_sel > 2) {
+ /* input clock divider */
+ sr32(&prm_base->clksrc_ctrl, 6, 2, 2);
+ clk_index = sys_clkin_sel / 2;
+ } else {
+ /* input clock divider */
+ sr32(&prm_base->clksrc_ctrl, 6, 2, 1);
+ clk_index = sys_clkin_sel;
+ }
+
+ if (get_cpu_family() == CPU_OMAP36XX) {
+ /* Unlock MPU DPLL (slows things down, and needed later) */
+ sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS);
+ wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu,
+ LDELAY);
+
+ dpll3_init_36xx(0, clk_index);
+ dpll4_init_36xx(0, clk_index);
+ iva_init_36xx(0, clk_index);
+ mpu_init_36xx(0, clk_index);
+
+ /* Lock MPU DPLL to set frequency */
+ sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOCK);
+ wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu,
+ LDELAY);
+ } else {
+ /*
+ * The DPLL tables are defined according to sysclk value and
+ * silicon revision. The clk_index value will be used to get
+ * the values for that input sysclk from the DPLL param table
+ * and sil_index will get the values for that SysClk for the
+ * appropriate silicon rev.
+ */
+ if (((get_cpu_family() == CPU_OMAP34XX)
+ && (get_cpu_rev() >= CPU_3XX_ES20)) ||
+ (get_cpu_family() == CPU_AM35XX))
+ sil_index = 1;
+
+ /* Unlock MPU DPLL (slows things down, and needed later) */
+ sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS);
+ wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu,
+ LDELAY);
+
+ dpll3_init_34xx(sil_index, clk_index);
+ dpll4_init_34xx(sil_index, clk_index);
+ iva_init_34xx(sil_index, clk_index);
+ mpu_init_34xx(sil_index, clk_index);
+
+ /* Lock MPU DPLL to set frequency */
+ sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOCK);
+ wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu,
+ LDELAY);
+ }
/* Set up GPTimers to sys_clk source only */
sr32(&prcm_base->clksel_per, 0, 8, 0xff);
get_per_dpll_param:
adr r0, per_dpll_param
mov pc, lr
+
+/*
+ * Tables for 36XX/37XX devices
+ *
+ */
+mpu_36x_dpll_param:
+/* 12MHz */
+.word 50, 0, 0, 1
+/* 13MHz */
+.word 600, 12, 0, 1
+/* 19.2MHz */
+.word 125, 3, 0, 1
+/* 26MHz */
+.word 300, 12, 0, 1
+/* 38.4MHz */
+.word 125, 7, 0, 1
+
+iva_36x_dpll_param:
+/* 12MHz */
+.word 130, 2, 0, 1
+/* 13MHz */
+.word 20, 0, 0, 1
+/* 19.2MHz */
+.word 325, 11, 0, 1
+/* 26MHz */
+.word 10, 0, 0, 1
+/* 38.4MHz */
+.word 325, 23, 0, 1
+
+core_36x_dpll_param:
+/* 12MHz */
+.word 100, 2, 0, 1
+/* 13MHz */
+.word 400, 12, 0, 1
+/* 19.2MHz */
+.word 375, 17, 0, 1
+/* 26MHz */
+.word 200, 12, 0, 1
+/* 38.4MHz */
+.word 375, 35, 0, 1
+
+per_36x_dpll_param:
+/* SYSCLK M N M2 M3 M4 M5 M6 m2DIV */
+.word 12000, 360, 4, 9, 16, 5, 4, 3, 1
+.word 13000, 864, 12, 9, 16, 9, 4, 3, 1
+.word 19200, 360, 7, 9, 16, 5, 4, 3, 1
+.word 26000, 432, 12, 9, 16, 9, 4, 3, 1
+.word 38400, 360, 15, 9, 16, 5, 4, 3, 1
+
+.globl get_36x_mpu_dpll_param
+get_36x_mpu_dpll_param:
+ adr r0, mpu_36x_dpll_param
+ mov pc, lr
+
+.globl get_36x_iva_dpll_param
+get_36x_iva_dpll_param:
+ adr r0, iva_36x_dpll_param
+ mov pc, lr
+
+.globl get_36x_core_dpll_param
+get_36x_core_dpll_param:
+ adr r0, core_36x_dpll_param
+ mov pc, lr
+
+.globl get_36x_per_dpll_param
+get_36x_per_dpll_param:
+ adr r0, per_36x_dpll_param
+ mov pc, lr
+
/*
* do_sdrc_init -
* - Initialize the SDRAM for use.
- * - Sets up SDRC timings for CS0
* - code called once in C-Stack only context for CS0 and a possible 2nd
* time depending on memory configuration from stack+global context
*/
void do_sdrc_init(u32 cs, u32 early)
{
- struct sdrc_actim *sdrc_actim_base;
-
- if (cs)
- sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
- else
- sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
+ struct sdrc_actim *sdrc_actim_base0, *sdrc_actim_base1;
if (early) {
/* reset sdrc controller */
sdelay(0x20000);
}
- writel(RASWIDTH_13BITS | CASWIDTH_10BITS | ADDRMUXLEGACY |
- RAMSIZE_128 | BANKALLOCATION | B32NOT16 | B32NOT16 |
- DEEPPD | DDR_SDRAM, &sdrc_base->cs[cs].mcfg);
- writel(ARCV | ARE_ARCV_1, &sdrc_base->cs[cs].rfr_ctrl);
- writel(V_ACTIMA_165, &sdrc_actim_base->ctrla);
- writel(V_ACTIMB_165, &sdrc_actim_base->ctrlb);
-
- writel(CMD_NOP, &sdrc_base->cs[cs].manual);
- writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
- writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
- writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
-
/*
- * CAS latency 3, Write Burst = Read Burst, Serial Mode,
- * Burst length = 4
+ * SDRC timings are set up by x-load or config header
+ * We don't need to redo them here.
+ * Older x-loads configure only CS0
+ * configure CS1 to handle this ommission
*/
- writel(CASL3 | BURSTLENGTH4, &sdrc_base->cs[cs].mr);
+ if (cs) {
+ sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
+ sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
+ writel(readl(&sdrc_base->cs[CS0].mcfg),
+ &sdrc_base->cs[CS1].mcfg);
+ writel(readl(&sdrc_base->cs[CS0].rfr_ctrl),
+ &sdrc_base->cs[CS1].rfr_ctrl);
+ writel(readl(&sdrc_actim_base0->ctrla),
+ &sdrc_actim_base1->ctrla);
+ writel(readl(&sdrc_actim_base0->ctrlb),
+ &sdrc_actim_base1->ctrlb);
+ }
+ /*
+ * Test ram in this bank
+ * Disable if bad or not present
+ */
if (!mem_ok(cs))
writel(0, &sdrc_base->cs[cs].mcfg);
}
"2.0",
"2.1",
"3.0",
- "3.1"};
+ "3.1",
+ "UNKNOWN",
+ "UNKNOWN",
+ "3.1.2"};
/*****************************************************************
* dieid_num_r(void) - read and set die ID
}
/******************************************
- * get_cpu_rev(void) - extract version info
+ * get_cpu_id(void) - extract cpu id
+ * returns 0 for ES1.0, cpuid otherwise
******************************************/
-u32 get_cpu_rev(void)
+u32 get_cpu_id(void)
{
- u32 cpuid = 0;
struct ctrl_id *id_base;
+ u32 cpuid = 0;
/*
* On ES1.0 the IDCODE register is not exposed on L4
* so using CPU ID to differentiate between ES1.0 and > ES1.0.
*/
__asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r"(cpuid));
- if ((cpuid & 0xf) == 0x0)
- return CPU_3XX_ES10;
- else {
+ if ((cpuid & 0xf) == 0x0) {
+ return 0;
+ } else {
/* Decode the IDs on > ES1.0 */
id_base = (struct ctrl_id *) OMAP34XX_ID_L4_IO_BASE;
- cpuid = (readl(&id_base->idcode) >> CPU_3XX_ID_SHIFT) & 0xf;
+ cpuid = readl(&id_base->idcode);
+ }
- /* Some early ES2.0 seem to report ID 0, fix this */
- if(cpuid == 0)
- cpuid = CPU_3XX_ES20;
+ return cpuid;
+}
- return cpuid;
+/******************************************
+ * get_cpu_family(void) - extract cpu info
+ ******************************************/
+u32 get_cpu_family(void)
+{
+ u16 hawkeye;
+ u32 cpu_family;
+ u32 cpuid = get_cpu_id();
+
+ if (cpuid == 0)
+ return CPU_OMAP34XX;
+
+ hawkeye = (cpuid >> HAWKEYE_SHIFT) & 0xffff;
+ switch (hawkeye) {
+ case HAWKEYE_OMAP34XX:
+ cpu_family = CPU_OMAP34XX;
+ break;
+ case HAWKEYE_AM35XX:
+ cpu_family = CPU_AM35XX;
+ break;
+ case HAWKEYE_OMAP36XX:
+ cpu_family = CPU_OMAP36XX;
+ break;
+ default:
+ cpu_family = CPU_OMAP34XX;
}
+
+ return cpu_family;
+}
+
+/******************************************
+ * get_cpu_rev(void) - extract version info
+ ******************************************/
+u32 get_cpu_rev(void)
+{
+ u32 cpuid = get_cpu_id();
+
+ if (cpuid == 0)
+ return CPU_3XX_ES10;
+ else
+ return (cpuid >> CPU_3XX_ID_SHIFT) & 0xf;
+}
+
+/*****************************************************************
+ * get_sku_id(void) - read sku_id to get info on max clock rate
+ *****************************************************************/
+u32 get_sku_id(void)
+{
+ struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
+ return readl(&id_base->sku_id) & SKUID_CLK_MASK;
}
/***************************************************************************
*/
int print_cpuinfo (void)
{
- char *cpu_s, *sec_s;
+ char *cpu_family_s, *cpu_s, *sec_s, *max_clk;
+
+ switch (get_cpu_family()) {
+ case CPU_OMAP34XX:
+ cpu_family_s = "OMAP";
+ switch (get_cpu_type()) {
+ case OMAP3503:
+ cpu_s = "3503";
+ break;
+ case OMAP3515:
+ cpu_s = "3515";
+ break;
+ case OMAP3525:
+ cpu_s = "3525";
+ break;
+ case OMAP3530:
+ cpu_s = "3530";
+ break;
+ default:
+ cpu_s = "35XX";
+ break;
+ }
+ if ((get_cpu_rev() >= CPU_3XX_ES31) &&
+ (get_sku_id() == SKUID_CLK_720MHZ))
+ max_clk = "720 mHz";
+ else
+ max_clk = "600 mHz";
- switch (get_cpu_type()) {
- case OMAP3503:
- cpu_s = "3503";
break;
- case OMAP3515:
- cpu_s = "3515";
+ case CPU_AM35XX:
+ cpu_family_s = "AM";
+ switch (get_cpu_type()) {
+ case AM3505:
+ cpu_s = "3505";
+ break;
+ case AM3517:
+ cpu_s = "3517";
+ break;
+ default:
+ cpu_s = "35XX";
+ break;
+ }
+ max_clk = "600 Mhz";
break;
- case OMAP3525:
- cpu_s = "3525";
- break;
- case OMAP3530:
- cpu_s = "3530";
+ case CPU_OMAP36XX:
+ cpu_family_s = "OMAP";
+ switch (get_cpu_type()) {
+ case OMAP3730:
+ cpu_s = "3630/3730";
+ break;
+ default:
+ cpu_s = "36XX/37XX";
+ break;
+ }
+ max_clk = "1 Ghz";
break;
default:
+ cpu_family_s = "OMAP";
cpu_s = "35XX";
- break;
+ max_clk = "600 Mhz";
}
switch (get_device_type()) {
sec_s = "?";
}
- printf("OMAP%s-%s ES%s, CPU-OPP2 L3-165MHz\n",
- cpu_s, sec_s, rev_s[get_cpu_rev()]);
+ printf("%s%s-%s ES%s, CPU-OPP2, L3-165MHz, Max CPU Clock %s\n",
+ cpu_family_s, cpu_s, sec_s,
+ rev_s[get_cpu_rev()], max_clk);
return 0;
}
+++ /dev/null
-/*
- * (C) Copyright 2008
- * Texas Instruments, <www.ti.com>
- *
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Mohammed Khasim <khasim@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/clocks.h>
-#include <asm/arch/sys_proto.h>
-
-/************************************************************
- * sdelay() - simple spin loop. Will be constant time as
- * its generally used in bypass conditions only. This
- * is necessary until timers are accessible.
- *
- * not inline to increase chances its in cache when called
- *************************************************************/
-void sdelay(unsigned long loops)
-{
- __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
- "bne 1b":"=r" (loops):"0"(loops));
-}
-
-/*****************************************************************
- * sr32 - clear & set a value in a bit range for a 32 bit address
- *****************************************************************/
-void sr32(void *addr, u32 start_bit, u32 num_bits, u32 value)
-{
- u32 tmp, msk = 0;
- msk = 1 << num_bits;
- --msk;
- tmp = readl((u32)addr) & ~(msk << start_bit);
- tmp |= value << start_bit;
- writel(tmp, (u32)addr);
-}
-
-/*********************************************************************
- * wait_on_value() - common routine to allow waiting for changes in
- * volatile regs.
- *********************************************************************/
-u32 wait_on_value(u32 read_bit_mask, u32 match_value, void *read_addr,
- u32 bound)
-{
- u32 i = 0, val;
- do {
- ++i;
- val = readl((u32)read_addr) & read_bit_mask;
- if (val == match_value)
- return 1;
- if (i == bound)
- return 0;
- } while (1);
-}
unsigned int m2;
} dpll_param;
+struct dpll_per_36x_param {
+ unsigned int sys_clk;
+ unsigned int m;
+ unsigned int n;
+ unsigned int m2;
+ unsigned int m3;
+ unsigned int m4;
+ unsigned int m5;
+ unsigned int m6;
+ unsigned int m2div;
+};
+
/* Following functions are exported from lowlevel_init.S */
extern dpll_param *get_mpu_dpll_param(void);
extern dpll_param *get_iva_dpll_param(void);
extern dpll_param *get_core_dpll_param(void);
extern dpll_param *get_per_dpll_param(void);
+extern dpll_param *get_36x_mpu_dpll_param(void);
+extern dpll_param *get_36x_iva_dpll_param(void);
+extern dpll_param *get_36x_core_dpll_param(void);
+extern dpll_param *get_36x_per_dpll_param(void);
+
extern void *_end_vect, *_start;
#endif
#define PER_FSEL_38P4 0x07
#define PER_M2_38P4 0x09
+/* 36XX PER DPLL */
+
+#define PER_36XX_M_12 0x1B0
+#define PER_36XX_N_12 0x05
+#define PER_36XX_FSEL_12 0x07
+#define PER_36XX_M2_12 0x09
+
+#define PER_36XX_M_13 0x360
+#define PER_36XX_N_13 0x0C
+#define PER_36XX_FSEL_13 0x03
+#define PER_36XX_M2_13 0x09
+
+#define PER_36XX_M_19P2 0x1C2
+#define PER_36XX_N_19P2 0x09
+#define PER_36XX_FSEL_19P2 0x07
+#define PER_36XX_M2_19P2 0x09
+
+#define PER_36XX_M_26 0x1B0
+#define PER_36XX_N_26 0x0C
+#define PER_36XX_FSEL_26 0x07
+#define PER_36XX_M2_26 0x09
+
+#define PER_36XX_M_38P4 0x1C2
+#define PER_36XX_N_38P4 0x13
+#define PER_36XX_FSEL_38P4 0x07
+#define PER_36XX_M2_38P4 0x09
+
#endif /* endif _CLOCKS_OMAP3_H_ */
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL_STRICT_NAMES */
-/* cpu type */
-#define OMAP3503 0x5c00
-#define OMAP3515 0x1c00
-#define OMAP3525 0x4c00
-#define OMAP3530 0x0c00
-
#ifndef __KERNEL_STRICT_NAMES
#ifndef __ASSEMBLY__
struct ctrl_id {
u8 res1[0x4];
u32 idcode; /* 0x04 */
u32 prod_id; /* 0x08 */
- u8 res2[0x0C];
+ u32 sku_id; /* 0x0c */
+ u8 res2[0x08];
u32 die_id_0; /* 0x18 */
u32 die_id_1; /* 0x1C */
u32 die_id_2; /* 0x20 */
#define HS_DEVICE 0x2
#define GP_DEVICE 0x3
+/* device speed */
+#define SKUID_CLK_MASK 0xf
+#define SKUID_CLK_600MHZ 0x0
+#define SKUID_CLK_720MHZ 0x8
+
#define GPMC_BASE (OMAP34XX_GPMC_BASE)
#define GPMC_CONFIG_CS0 0x60
#define GPMC_CONFIG_CS0_BASE (GPMC_BASE + GPMC_CONFIG_CS0)
};
#else /* __ASSEMBLY__ */
#define PRM_RSTCTRL 0x48307250
+#define PRM_RSTCTRL_RESET 0x04
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL_STRICT_NAMES */
#define CPU_3XX_ES21 2
#define CPU_3XX_ES30 3
#define CPU_3XX_ES31 4
-#define CPU_3XX_MAX_REV (CPU_3XX_ES31 + 1)
+#define CPU_3XX_ES312 7
+#define CPU_3XX_MAX_REV 8
#define CPU_3XX_ID_SHIFT 28
#define WIDTH_8BIT 0x0000
#define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */
+/*
+ * Hawkeye values
+ */
+#define HAWKEYE_OMAP34XX 0xb7ae
+#define HAWKEYE_AM35XX 0xb868
+#define HAWKEYE_OMAP36XX 0xb891
+
+#define HAWKEYE_SHIFT 12
+
+/*
+ * Define CPU families
+ */
+#define CPU_OMAP34XX 0x3400 /* OMAP34xx/OMAP35 devices */
+#define CPU_AM35XX 0x3500 /* AM35xx devices */
+#define CPU_OMAP36XX 0x3600 /* OMAP36xx devices */
+
+/*
+ * Control status register values corresponding to cpu variants
+ */
+#define OMAP3503 0x5c00
+#define OMAP3515 0x1c00
+#define OMAP3525 0x4c00
+#define OMAP3530 0x0c00
+
+#define AM3505 0x5c00
+#define AM3517 0x1c00
+
+#define OMAP3730 0x0c00
+
#endif
void watchdog_init(void);
void set_muxconf_regs(void);
+u32 get_cpu_family(void);
u32 get_cpu_rev(void);
+u32 get_sku_id(void);
u32 get_mem_type(void);
u32 get_sysboot_value(void);
u32 is_gpmc_muxed(void);
#define PRM_DEVICE_BASE (PRM_BASE + 0x1B00)
#define PRM_RSTCTRL PRM_DEVICE_BASE
+#define PRM_RSTCTRL_RESET 0x01
#ifndef __ASSEMBLY__
u32 get_device_type(void);
void invalidate_dcache(u32);
void set_muxconf_regs(void);
+void sr32(void *, u32, u32, u32);
+u32 wait_on_value(u32, u32, void *, u32);
+void sdelay(unsigned long);
extern const struct omap_sysinfo sysinfo;
static void setup_net_chip(void);
#endif
+/* GPMC definitions for LAN9221 chips on Tobi expansion boards */
+static const u32 gpmc_lan_config[] = {
+ NET_LAN9221_GPMC_CONFIG1,
+ NET_LAN9221_GPMC_CONFIG2,
+ NET_LAN9221_GPMC_CONFIG3,
+ NET_LAN9221_GPMC_CONFIG4,
+ NET_LAN9221_GPMC_CONFIG5,
+ NET_LAN9221_GPMC_CONFIG6,
+ /*CONFIG7- computed as params */
+};
+
/*
* Routine: board_init
* Description: Early hardware init.
return 0;
}
+/*
+ * Routine: get_board_revision
+ * Description: Returns the board revision
+ */
+int get_board_revision(void)
+{
+ int revision;
+
+ if (!omap_request_gpio(112) &&
+ !omap_request_gpio(113) &&
+ !omap_request_gpio(115)) {
+
+ omap_set_gpio_direction(112, 1);
+ omap_set_gpio_direction(113, 1);
+ omap_set_gpio_direction(115, 1);
+
+ revision = omap_get_gpio_datain(115) << 2 |
+ omap_get_gpio_datain(113) << 1 |
+ omap_get_gpio_datain(112);
+
+ omap_free_gpio(112);
+ omap_free_gpio(113);
+ omap_free_gpio(115);
+ } else {
+ printf("Error: unable to acquire board revision GPIOs\n");
+ revision = -1;
+ }
+
+ return revision;
+}
+
+/*
+ * Routine: get_sdio2_config
+ * Description: Return information about the wifi module connection
+ * Returns 0 if the module connects though a level translator
+ * Returns 1 if the module connects directly
+ */
+int get_sdio2_config(void)
+{
+ int sdio_direct;
+
+ if (!omap_request_gpio(130) && !omap_request_gpio(139)) {
+
+ omap_set_gpio_direction(130, 0);
+ omap_set_gpio_direction(139, 1);
+
+ sdio_direct = 1;
+ omap_set_gpio_dataout(130, 0);
+ if (omap_get_gpio_datain(139) == 0) {
+ omap_set_gpio_dataout(130, 1);
+ if (omap_get_gpio_datain(139) == 1)
+ sdio_direct = 0;
+ }
+
+ omap_free_gpio(130);
+ omap_free_gpio(139);
+ } else {
+ printf("Error: unable to acquire sdio2 clk GPIOs\n");
+ sdio_direct = -1;
+ }
+
+ return sdio_direct;
+}
+
/*
* Routine: misc_init_r
* Description: Configure board specific parts
setup_net_chip();
#endif
+ printf("Board revision: %d\n", get_board_revision());
+
+ switch (get_sdio2_config()) {
+ case 0:
+ printf("Tranceiver detected on mmc2\n");
+ MUX_OVERO_SDIO2_TRANSCEIVER();
+ break;
+ case 1:
+ printf("Direct connection on mmc2\n");
+ MUX_OVERO_SDIO2_DIRECT();
+ break;
+ default:
+ printf("Unable to detect mmc2 connection type\n");
+ }
+
dieid_num_r();
return 0;
{
struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
- /* Configure GPMC registers */
- writel(NET_LAN9221_GPMC_CONFIG1, &gpmc_cfg->cs[5].config1);
- writel(NET_LAN9221_GPMC_CONFIG2, &gpmc_cfg->cs[5].config2);
- writel(NET_LAN9221_GPMC_CONFIG3, &gpmc_cfg->cs[5].config3);
- writel(NET_LAN9221_GPMC_CONFIG4, &gpmc_cfg->cs[5].config4);
- writel(NET_LAN9221_GPMC_CONFIG5, &gpmc_cfg->cs[5].config5);
- writel(NET_LAN9221_GPMC_CONFIG6, &gpmc_cfg->cs[5].config6);
- writel(NET_LAN9221_GPMC_CONFIG7, &gpmc_cfg->cs[5].config7);
+ /* first lan chip */
+ enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000,
+ GPMC_SIZE_16M);
+
+ /* second lan chip */
+ enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[4], 0x2B000000,
+ GPMC_SIZE_16M);
/* Enable off mode for NWE in PADCONF_GPMC_NWE register */
writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\
/* - SMSC911X_NRES*/\
- MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPMC_nCS3*/\
+ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | DIS | M4)) /*GPIO_65*/\
/*DSS*/\
MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M0)) /*CAM_WEN*/\
MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
- MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\
- MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\
+ MUX_VAL(CP(CSI2_DX0), (IEN | PTD | EN | M4)) /*GPIO_112*/\
+ MUX_VAL(CP(CSI2_DY0), (IEN | PTD | EN | M4)) /*GPIO_113*/\
MUX_VAL(CP(CSI2_DX1), (IEN | PTD | EN | M4)) /*GPIO_114*/\
/* - PEN_DOWN*/\
- MUX_VAL(CP(CSI2_DY1), (IEN | PTU | EN | M4)) /*GPIO_115*/\
+ MUX_VAL(CP(CSI2_DY1), (IEN | PTD | EN | M4)) /*GPIO_115*/\
/*Audio Interface */\
MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\
MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\
MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\
MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
/*Expansion card */\
- MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
+ MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) /*MMC1_CLK*/\
MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\
MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\
/*Wireless LAN */\
- MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\
+ MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\
MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\
MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\
MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\
MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT0*/\
MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT1*/\
MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M1)) /*MMC2_DIR_CMD*/\
- MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M1)) /*MMC2_CLKIN*/\
+ MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\
/*Bluetooth*/\
MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M1)) /*UART2_CTS*/\
MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT1*/\
MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\
- MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M2)) /*MMC3_CLK*/\
+ MUX_VAL(CP(ETK_CLK_ES2), (IEN | PTU | EN | M2)) /*MMC3_CLK*/\
MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M2)) /*MMC3_CMD*/\
MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | EN | M4)) /*GPIO_14*/\
MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M4)) /*GPIO_15 - X_GATE*/\
MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\
MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /*sdrc_cke1*/
+#define MUX_OVERO_SDIO2_DIRECT() \
+ MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\
+ MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\
+ MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\
+ MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\
+ MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\
+ MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\
+ MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M0)) /*MMC2_DAT4*/\
+ MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M0)) /*MMC2_DAT5*/\
+ MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M0)) /*MMC2_DAT6*/\
+ MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M0)) /*MMC2_DAT7*/\
+ MUX_VAL(CP(MMC1_DAT4), (IEN | PTD | EN | M4)) /*GPIO_126*/\
+ MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) /*GPIO_127*/\
+ MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) /*GPIO_128*/\
+ MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) /*GPIO_129*/
+
+#define MUX_OVERO_SDIO2_TRANSCEIVER() \
+ MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\
+ MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\
+ MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\
+ MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\
+ MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\
+ MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\
+ MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT0*/\
+ MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT1*/\
+ MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M1)) /*MMC2_DIR_CMD*/\
+ MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M1)) /*MMC2_CLKIN*/\
+ MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) /*GPIO_126*/\
+ MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) /*GPIO_127*/\
+ MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) /*GPIO_128*/\
+ MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) /*GPIO_129*/
#endif
#include <asm/mach-types.h>
#include "beagle.h"
-static int beagle_revision_c;
-
/*
* Routine: board_init
* Description: Early hardware init.
}
/*
- * Routine: beagle_get_revision
- * Description: Return the revision of the BeagleBoard this code is running on.
- * If it is a revision Ax/Bx board, this function returns 0,
- * on a revision C board you will get a 1.
+ * Routine: get_board_revision
+ * Description: Detect if we are running on a Beagle revision Ax/Bx,
+ * C1/2/3, C4 or xM. This can be done by reading
+ * the level of GPIO173, GPIO172 and GPIO171. This should
+ * result in
+ * GPIO173, GPIO172, GPIO171: 1 1 1 => Ax/Bx
+ * GPIO173, GPIO172, GPIO171: 1 1 0 => C1/2/3
+ * GPIO173, GPIO172, GPIO171: 1 0 1 => C4
+ * GPIO173, GPIO172, GPIO171: 0 0 0 => xM
*/
-int beagle_get_revision(void)
+int get_board_revision(void)
{
- return beagle_revision_c;
-}
+ int revision;
-/*
- * Routine: beagle_identify
- * Description: Detect if we are running on a Beagle revision Ax/Bx or
- * Cx. This can be done by GPIO_171. If this is low, we are
- * running on a revision C board.
- */
-void beagle_identify(void)
-{
- beagle_revision_c = 0;
- if (!omap_request_gpio(171)) {
- unsigned int val;
+ if (!omap_request_gpio(171) &&
+ !omap_request_gpio(172) &&
+ !omap_request_gpio(173)) {
omap_set_gpio_direction(171, 1);
- val = omap_get_gpio_datain(171);
- omap_free_gpio(171);
+ omap_set_gpio_direction(172, 1);
+ omap_set_gpio_direction(173, 1);
- if (val)
- beagle_revision_c = 0;
- else
- beagle_revision_c = 1;
+ revision = omap_get_gpio_datain(173) << 2 |
+ omap_get_gpio_datain(172) << 1 |
+ omap_get_gpio_datain(171);
+
+ omap_free_gpio(171);
+ omap_free_gpio(172);
+ omap_free_gpio(173);
+ } else {
+ printf("Error: unable to acquire board revision GPIOs\n");
+ revision = -1;
}
- printf("Board revision ");
- if (beagle_revision_c)
- printf("C\n");
- else
- printf("Ax/Bx\n");
+ return revision;
}
/*
struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
+ switch (get_board_revision()) {
+ case REVISION_AXBX:
+ printf("Beagle Rev Ax/Bx\n");
+ setenv("beaglerev", "AxBx");
+ setenv("mpurate", "600");
+ break;
+ case REVISION_CX:
+ printf("Beagle Rev C1/C2/C3\n");
+ setenv("beaglerev", "Cx");
+ setenv("mpurate", "600");
+ MUX_BEAGLE_C();
+ break;
+ case REVISION_C4:
+ printf("Beagle Rev C4\n");
+ setenv("beaglerev", "C4");
+ setenv("mpurate", "720");
+ MUX_BEAGLE_C();
+ /* Set VAUX2 to 1.8V for EHCI PHY */
+ twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED,
+ TWL4030_PM_RECEIVER_VAUX2_VSEL_18,
+ TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
+ TWL4030_PM_RECEIVER_DEV_GRP_P1);
+ break;
+ case REVISION_XM:
+ printf("Beagle xM Rev A\n");
+ setenv("beaglerev", "xMA");
+ setenv("mpurate", "1000");
+ MUX_BEAGLE_XM();
+ /* Set VAUX2 to 1.8V for EHCI PHY */
+ twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED,
+ TWL4030_PM_RECEIVER_VAUX2_VSEL_18,
+ TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
+ TWL4030_PM_RECEIVER_DEV_GRP_P1);
+ break;
+ default:
+ printf("Beagle unknown 0x%02x\n", get_board_revision());
+ }
+
twl4030_power_init();
twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
GPIO15 | GPIO14 | GPIO13 | GPIO12, &gpio5_base->setdataout);
- beagle_identify();
-
dieid_num_r();
return 0;
void set_muxconf_regs(void)
{
MUX_BEAGLE();
-
- if (beagle_revision_c) {
- MUX_BEAGLE_C();
- }
}
#endif
};
-#define BOARD_REVISION_MASK (0x1 << 11)
+/* BeagleBoard revisions */
+#define REVISION_AXBX 0x7
+#define REVISION_CX 0x6
+#define REVISION_C4 0x5
+#define REVISION_XM 0x0
/*
* IEN - Input Enable
MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*GPIO_170*/\
MUX_VAL(CP(MCSPI1_CLK), (IEN | PTU | EN | M4)) /*GPIO_171*/\
MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTU | EN | M4)) /*GPIO_172*/\
- MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) /*McSPI1_SOMI*/\
+ MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTU | EN | M4)) /*GPIO_173*/\
MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) /*McSPI1_CS0*/\
MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M0)) /*McSPI1_CS1*/\
MUX_VAL(CP(MCSPI1_CS2), (IDIS | PTD | DIS | M4)) /*GPIO_176*/\
MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /*sdrc_cke1*/
#define MUX_BEAGLE_C() \
- MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M4)) /*GPIO_140*/\
- MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M4)) /*GPIO_142*/\
- MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_141*/\
+ MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M4)) /*GPIO_140*/\
+ MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M4)) /*GPIO_142*/\
+ MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_141*/\
MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) /*UART2_CTS*/\
MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\
MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/
+#define MUX_BEAGLE_XM() \
+ MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M4)) /*GPIO_140*/\
+ MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M4)) /*GPIO_142*/\
+ MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_141*/\
+ MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) /*UART2_CTS*/\
+ MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\
+ MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/\
+ MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M7)) /*safe_mode*/\
+ MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M7)) /*safe_mode*/\
+ MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M7)) /*safe_mode*/\
+ MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M7)) /*safe_mode*/\
+ MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M7)) /*safe_mode*/\
+ MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M7)) /*safe_mode*/\
+ MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M3)) /*DSS_DATA0*/\
+ MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M3)) /*DSS_DATA1*/\
+ MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M3)) /*DSS_DATA2*/\
+ MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M3)) /*DSS_DATA3*/\
+ MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M3)) /*DSS_DATA4*/\
+ MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M3)) /*DSS_DATA5*/\
+ MUX_VAL(CP(SYS_BOOT0), (IDIS | PTD | DIS | M3)) /*DSS_DATA18*/\
+ MUX_VAL(CP(SYS_BOOT1), (IDIS | PTD | DIS | M3)) /*DSS_DATA19*/\
+ MUX_VAL(CP(SYS_BOOT3), (IDIS | PTD | DIS | M3)) /*DSS_DATA20*/\
+ MUX_VAL(CP(SYS_BOOT4), (IDIS | PTD | DIS | M3)) /*DSS_DATA21*/\
+ MUX_VAL(CP(SYS_BOOT5), (IDIS | PTD | DIS | M3)) /*DSS_DATA22*/\
+ MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M3)) /*DSS_DATA23*/
+
#endif
};
const struct pad_conf_entry wkup_padconf_array[] = {
- {PAD0_SIM_IO, (IEN | M0)}, /* sim_io */
- {PAD1_SIM_CLK, (M0)}, /* sim_clk */
- {PAD0_SIM_RESET, (M0)}, /* sim_reset */
- {PAD1_SIM_CD, (PTU | IEN | M0)}, /* sim_cd */
- {PAD0_SIM_PWRCTRL, (M0)}, /* sim_pwrctrl */
- {PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */
- {PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */
- {PAD1_FREF_XTAL_IN, (M0)}, /* # */
- {PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */
- {PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */
- {PAD0_FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */
- {PAD1_FREF_CLK3_REQ, (PTU | IEN | M0)}, /* # */
- {PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */
- {PAD1_FREF_CLK4_REQ, (PTU | IEN | M0)}, /* # */
- {PAD0_FREF_CLK4_OUT, (M0)}, /* # */
- {PAD1_SYS_32K, (IEN | M0)}, /* sys_32k */
- {PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */
- {PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */
- {PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */
- {PAD1_SYS_PWRON_RESET, (M3)}, /* gpio_wk29 */
- {PAD0_SYS_BOOT6, (IEN | M3)}, /* gpio_wk9 */
- {PAD1_SYS_BOOT7, (IEN | M3)}, /* gpio_wk10 */
+ {PAD0_SIM_IO, (IEN | M0)}, /* sim_io */
+ {PAD1_SIM_CLK, (M0)}, /* sim_clk */
+ {PAD0_SIM_RESET, (M0)}, /* sim_reset */
+ {PAD1_SIM_CD, (PTU | IEN | M0)}, /* sim_cd */
+ {PAD0_SIM_PWRCTRL, (M0)}, /* sim_pwrctrl */
+ {PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */
+ {PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */
+ {PAD1_FREF_XTAL_IN, (M0)}, /* # */
+ {PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */
+ {PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */
+ {PAD0_FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */
+ {PAD1_FREF_CLK3_REQ, (PTU | IEN | M0)}, /* # */
+ {PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */
+ {PAD1_FREF_CLK4_REQ, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* led status_1 */
+ {PAD0_FREF_CLK4_OUT, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* led status_2 */
+ {PAD1_SYS_32K, (IEN | M0)}, /* sys_32k */
+ {PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */
+ {PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */
+ {PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */
+ {PAD1_SYS_PWRON_RESET, (M3)}, /* gpio_wk29 */
+ {PAD0_SYS_BOOT6, (IEN | M3)}, /* gpio_wk9 */
+ {PAD1_SYS_BOOT7, (IEN | M3)}, /* gpio_wk10 */
};
#endif
}
if (!type) {
- printk(KERN_INFO "%s: unknown NAND device: Manufacturer ID:"
- " 0x%02x, Chip ID: 0x%02x\n", __func__,
- *maf_id, dev_id);
+ /* supress warning if there is no nand */
+ if (*maf_id != 0x00 && *maf_id != 0xff &&
+ dev_id != 0x00 && dev_id != 0xff)
+ printk(KERN_INFO "%s: unknown NAND device: "
+ "Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
+ __func__, *maf_id, dev_id);
return ERR_PTR(-ENODEV);
}
}
}
-
/*
- * Power Init
+ * Set Device Group and Voltage
*/
-#define DEV_GRP_P1 0x20
-#define VAUX3_VSEL_28 0x03
-#define DEV_GRP_ALL 0xE0
-#define VPLL2_VSEL_18 0x05
-#define VDAC_VSEL_18 0x03
+void twl4030_pmrecv_vsel_cfg(u8 vsel_reg, u8 vsel_val,
+ u8 dev_grp, u8 dev_grp_sel)
+{
+ /* Select the Device Group */
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, dev_grp_sel,
+ dev_grp);
+
+ /* Select the Voltage */
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, vsel_val,
+ vsel_reg);
+}
void twl4030_power_init(void)
{
- unsigned char byte;
-
/* set VAUX3 to 2.8V */
- byte = DEV_GRP_P1;
- twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, byte,
- TWL4030_PM_RECEIVER_VAUX3_DEV_GRP);
- byte = VAUX3_VSEL_28;
- twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, byte,
- TWL4030_PM_RECEIVER_VAUX3_DEDICATED);
+ twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX3_DEDICATED,
+ TWL4030_PM_RECEIVER_VAUX3_VSEL_28,
+ TWL4030_PM_RECEIVER_VAUX3_DEV_GRP,
+ TWL4030_PM_RECEIVER_DEV_GRP_P1);
/* set VPLL2 to 1.8V */
- byte = DEV_GRP_ALL;
- twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, byte,
- TWL4030_PM_RECEIVER_VPLL2_DEV_GRP);
- byte = VPLL2_VSEL_18;
- twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, byte,
- TWL4030_PM_RECEIVER_VPLL2_DEDICATED);
+ twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VPLL2_DEDICATED,
+ TWL4030_PM_RECEIVER_VPLL2_VSEL_18,
+ TWL4030_PM_RECEIVER_VPLL2_DEV_GRP,
+ TWL4030_PM_RECEIVER_DEV_GRP_ALL);
/* set VDAC to 1.8V */
- byte = DEV_GRP_P1;
- twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, byte,
- TWL4030_PM_RECEIVER_VDAC_DEV_GRP);
- byte = VDAC_VSEL_18;
- twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, byte,
- TWL4030_PM_RECEIVER_VDAC_DEDICATED);
+ twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VDAC_DEDICATED,
+ TWL4030_PM_RECEIVER_VDAC_VSEL_18,
+ TWL4030_PM_RECEIVER_VDAC_DEV_GRP,
+ TWL4030_PM_RECEIVER_DEV_GRP_P1);
}
-#define VMMC1_VSEL_30 0x02
-
void twl4030_power_mmc_init(void)
{
- unsigned char byte;
-
- byte = DEV_GRP_P1;
- twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, byte,
- TWL4030_PM_RECEIVER_VMMC1_DEV_GRP);
-
- /* 3 Volts */
- byte = VMMC1_VSEL_30;
- twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, byte,
- TWL4030_PM_RECEIVER_VMMC1_DEDICATED);
+ /* Set VMMC1 to 3 Volts */
+ twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VMMC1_DEDICATED,
+ TWL4030_PM_RECEIVER_VMMC1_VSEL_30,
+ TWL4030_PM_RECEIVER_VMMC1_DEV_GRP,
+ TWL4030_PM_RECEIVER_DEV_GRP_P1);
}
+
/*
* Board NAND Info.
*/
+#define CONFIG_SYS_NAND_QUIET_TEST 1
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
/* to access nand */
"loadaddr=0x82000000\0" \
"usbtty=cdc_acm\0" \
"console=ttyS2,115200n8\0" \
+ "mpurate=500\0" \
"vram=12M\0" \
"dvimode=1024x768MR-16@60\0" \
"defaultdisplay=dvi\0" \
"nandroot=/dev/mtdblock4 rw\0" \
"nandrootfstype=jffs2\0" \
"mmcargs=setenv bootargs console=${console} " \
+ "mpurate=${mpurate} " \
"vram=${vram} " \
"omapfb.mode=dvi:${dvimode} " \
"omapfb.debug=y " \
"root=${mmcroot} " \
"rootfstype=${mmcrootfstype}\0" \
"nandargs=setenv bootargs console=${console} " \
+ "mpurate=${mpurate} " \
"vram=${vram} " \
"omapfb.mode=dvi:${dvimode} " \
"omapfb.debug=y " \
/*
* Board NAND Info.
*/
+#define CONFIG_SYS_NAND_QUIET_TEST 1
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
/* to access nand */
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x82000000\0" \
"console=ttyS2,115200n8\0" \
+ "mpurate=500\0" \
"vram=12M\0" \
"dvimode=1024x768MR-16@60\0" \
"defaultdisplay=dvi\0" \
"nandroot=/dev/mtdblock4 rw\0" \
"nandrootfstype=jffs2\0" \
"mmcargs=setenv bootargs console=${console} " \
+ "mpurate=${mpurate} " \
"vram=${vram} " \
"omapfb.mode=dvi:${dvimode} " \
"omapfb.debug=y " \
"root=${mmcroot} " \
"rootfstype=${mmcrootfstype}\0" \
"nandargs=setenv bootargs console=${console} " \
+ "mpurate=${mpurate} " \
"vram=${vram} " \
"omapfb.mode=dvi:${dvimode} " \
"omapfb.debug=y " \
#define TWL4030_PM_RECEIVER_MAINREF_TYPE 0xF0
#define TWL4030_PM_RECEIVER_MAINREF_REMAP 0xF1
+/* Voltage Selection in PM Receiver Module */
+#define TWL4030_PM_RECEIVER_VAUX2_VSEL_18 0x05
+#define TWL4030_PM_RECEIVER_VAUX3_VSEL_28 0x03
+#define TWL4030_PM_RECEIVER_VPLL2_VSEL_18 0x05
+#define TWL4030_PM_RECEIVER_VDAC_VSEL_18 0x03
+#define TWL4030_PM_RECEIVER_VMMC1_VSEL_30 0x02
+
+/* Device Selection in PM Receiver Module */
+#define TWL4030_PM_RECEIVER_DEV_GRP_P1 0x20
+#define TWL4030_PM_RECEIVER_DEV_GRP_ALL 0xE0
+
/* LED */
#define TWL4030_LED_LEDEN 0xEE
#define TWL4030_LED_LEDEN_LEDAON (1 << 0)
/* For hardware resetting */
void twl4030_power_reset_init(void);
+/* For setting device group and voltage */
+void twl4030_pmrecv_vsel_cfg(u8 vsel_reg, u8 vsel_val,
+ u8 dev_grp, u8 dev_grp_sel);
/* For initializing power device */
void twl4030_power_init(void);
/* For initializing mmc power */
projects / u-boot / commitdiff