#define SDRAM_CFG_32B_MASK (1 << SDRAM_CFG_32B_SHIFT)
#define SDRAM_CFG_BANK_SHIFT 13
#define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT)
+#define SDRAM_6318_SPACE_SHIFT 4
+#define SDRAM_6318_SPACE_MASK (0xf << SDRAM_6318_SPACE_SHIFT)
#define MEMC_CFG_REG 0x4
#define MEMC_CFG_32B_SHIFT 1
const struct bmips_ram_hw *hw;
};
+static ulong bcm6318_get_ram_size(struct bmips_ram_priv *priv)
+{
+ u32 val;
+
+ val = readl_be(priv->regs + SDRAM_CFG_REG);
+ val = (val & SDRAM_6318_SPACE_MASK) >> SDRAM_6318_SPACE_SHIFT;
+
+ return (1 << (val + 20));
+}
+
static ulong bcm6328_get_ram_size(struct bmips_ram_priv *priv)
{
return readl_be(priv->regs + DDR_CSEND_REG) << 24;
.get_info = bmips_ram_get_info,
};
+static const struct bmips_ram_hw bmips_ram_bcm6318 = {
+ .get_ram_size = bcm6318_get_ram_size,
+};
+
static const struct bmips_ram_hw bmips_ram_bcm6328 = {
.get_ram_size = bcm6328_get_ram_size,
};
static const struct udevice_id bmips_ram_ids[] = {
{
+ .compatible = "brcm,bcm6318-mc",
+ .data = (ulong)&bmips_ram_bcm6318,
+ }, {
.compatible = "brcm,bcm6328-mc",
.data = (ulong)&bmips_ram_bcm6328,
}, {