]> git.sur5r.net Git - u-boot/commitdiff
geam6/isiot: Move the spl code common
authorJagan Teki <jagan@amarulasolutions.com>
Sat, 6 May 2017 21:13:13 +0000 (02:43 +0530)
committerStefano Babic <sbabic@denx.de>
Thu, 18 May 2017 09:23:31 +0000 (11:23 +0200)
SPL code for geam6 and isiot are same, so
move them in common area.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
board/engicam/common/Makefile
board/engicam/common/spl.c
board/engicam/geam6ul/geam6ul.c
board/engicam/isiotmx6ul/isiotmx6ul.c

index 11e7fee47d446a4d74a834d76daf0ca5532ce4b6..6fd039cbfc23160e726fb7896325706d901bc3d0 100644 (file)
@@ -3,6 +3,4 @@
 # SPDX-License-Identifier:     GPL-2.0+
 #
 
-ifdef CONFIG_MX6QDL
 obj-$(CONFIG_SPL_BUILD) += spl.o
-endif
index 71e85d5c88152ec855eae339487bf33a7fc88586..ab0ab986bfc8238bd0eed76ba2ccfcabdff6d420 100644 (file)
@@ -29,11 +29,17 @@ DECLARE_GLOBAL_DATA_PTR;
         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
-static iomux_v3_cfg_t const uart4_pads[] = {
+static iomux_v3_cfg_t const uart_pads[] = {
+#ifdef CONFIG_MX6QDL
         IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
         IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+#elif CONFIG_MX6UL
+       IOMUX_PADS(PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL)),
+       IOMUX_PADS(PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL)),
+#endif
 };
 
+#ifdef CONFIG_MX6QDL
 /*
  * Driving strength:
  *   0x30 == 40 Ohm
@@ -234,11 +240,80 @@ static struct mx6_ddr_sysinfo mem_s = {
        .rst_to_cke     = 0x23,
        .sde_to_rst     = 0x10,
 };
+#endif /* CONFIG_MX6QDL */
+
+#ifdef CONFIG_MX6UL
+static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
+       .grp_addds = 0x00000030,
+       .grp_ddrmode_ctl = 0x00020000,
+       .grp_b0ds = 0x00000030,
+       .grp_ctlds = 0x00000030,
+       .grp_b1ds = 0x00000030,
+       .grp_ddrpke = 0x00000000,
+       .grp_ddrmode = 0x00020000,
+       .grp_ddr_type = 0x000c0000,
+};
+
+static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
+       .dram_dqm0 = 0x00000030,
+       .dram_dqm1 = 0x00000030,
+       .dram_ras = 0x00000030,
+       .dram_cas = 0x00000030,
+       .dram_odt0 = 0x00000030,
+       .dram_odt1 = 0x00000030,
+       .dram_sdba2 = 0x00000000,
+       .dram_sdclk_0 = 0x00000008,
+       .dram_sdqs0 = 0x00000038,
+       .dram_sdqs1 = 0x00000030,
+       .dram_reset = 0x00000030,
+};
+
+static struct mx6_mmdc_calibration mx6_mmcd_calib = {
+       .p0_mpwldectrl0 = 0x00070007,
+       .p0_mpdgctrl0 = 0x41490145,
+       .p0_mprddlctl = 0x40404546,
+       .p0_mpwrdlctl = 0x4040524D,
+};
+
+struct mx6_ddr_sysinfo ddr_sysinfo = {
+       .dsize = 0,
+       .cs_density = 20,
+       .ncs = 1,
+       .cs1_mirror = 0,
+       .rtt_wr = 2,
+       .rtt_nom = 1,           /* RTT_Nom = RZQ/2 */
+       .walat = 1,             /* Write additional latency */
+       .ralat = 5,             /* Read additional latency */
+       .mif3_mode = 3,         /* Command prediction working mode */
+       .bi_on = 1,             /* Bank interleaving enabled */
+       .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
+       .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
+       .ddr_type = DDR_TYPE_DDR3,
+};
+
+static struct mx6_ddr3_cfg mem_ddr = {
+       .mem_speed = 800,
+       .density = 4,
+       .width = 16,
+       .banks = 8,
+#ifdef TARGET_MX6UL_ISIOT
+       .rowaddr = 15,
+#else
+       .rowaddr = 13,
+#endif
+       .coladdr = 10,
+       .pagesz = 2,
+       .trcd = 1375,
+       .trcmin = 4875,
+       .trasmin = 3500,
+};
+#endif /* CONFIG_MX6UL */
 
 static void ccgr_init(void)
 {
        struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 
+#ifdef CONFIG_MX6QDL
        writel(0x00003F3F, &ccm->CCGR0);
        writel(0x0030FC00, &ccm->CCGR1);
        writel(0x000FC000, &ccm->CCGR2);
@@ -246,6 +321,15 @@ static void ccgr_init(void)
        writel(0xFF00F300, &ccm->CCGR4);
        writel(0x0F0000C3, &ccm->CCGR5);
        writel(0x000003CC, &ccm->CCGR6);
+#elif CONFIG_MX6UL
+       writel(0x00c03f3f, &ccm->CCGR0);
+       writel(0xfcffff00, &ccm->CCGR1);
+       writel(0x0cffffcc, &ccm->CCGR2);
+       writel(0x3f3c3030, &ccm->CCGR3);
+       writel(0xff00fffc, &ccm->CCGR4);
+       writel(0x033f30ff, &ccm->CCGR5);
+       writel(0x00c00fff, &ccm->CCGR6);
+#endif
 }
 
 static void gpr_init(void)
@@ -261,6 +345,7 @@ static void gpr_init(void)
 
 static void spl_dram_init(void)
 {
+#ifdef CONFIG_MX6QDL
        if (is_mx6solo()) {
                mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
                mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256);
@@ -271,6 +356,10 @@ static void spl_dram_init(void)
                mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
                mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256);
        }
+#elif CONFIG_MX6UL
+       mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+       mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
+#endif
 
        udelay(100);
 }
@@ -285,7 +374,7 @@ void board_init_f(ulong dummy)
        gpr_init();
 
        /* iomux */
-       SETUP_IOMUX_PADS(uart4_pads);
+       SETUP_IOMUX_PADS(uart_pads);
 
        /* setup GP timer */
        timer_init();
index 06a286be82e82d4f220ee2ef9d263e93c9edb180..408b4763658c14f0167b3e4a1dddf7805ff71bc0 100644 (file)
@@ -151,21 +151,6 @@ int dram_init(void)
 }
 
 #ifdef CONFIG_SPL_BUILD
-#include <libfdt.h>
-#include <spl.h>
-
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/mx6-ddr.h>
-
-#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |            \
-       PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
-       PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
-
-static iomux_v3_cfg_t const uart1_pads[] = {
-       IOMUX_PADS(PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL)),
-       IOMUX_PADS(PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL)),
-};
-
 /* MMC board initialization is needed till adding DM support in SPL */
 #if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
 #include <mmc.h>
@@ -243,111 +228,4 @@ int board_mmc_init(bd_t *bis)
        return 0;
 }
 #endif /* CONFIG_FSL_ESDHC */
-
-static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
-       .grp_addds = 0x00000030,
-       .grp_ddrmode_ctl = 0x00020000,
-       .grp_b0ds = 0x00000030,
-       .grp_ctlds = 0x00000030,
-       .grp_b1ds = 0x00000030,
-       .grp_ddrpke = 0x00000000,
-       .grp_ddrmode = 0x00020000,
-       .grp_ddr_type = 0x000c0000,
-};
-
-static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
-       .dram_dqm0 = 0x00000030,
-       .dram_dqm1 = 0x00000030,
-       .dram_ras = 0x00000030,
-       .dram_cas = 0x00000030,
-       .dram_odt0 = 0x00000030,
-       .dram_odt1 = 0x00000030,
-       .dram_sdba2 = 0x00000000,
-       .dram_sdclk_0 = 0x00000008,
-       .dram_sdqs0 = 0x00000038,
-       .dram_sdqs1 = 0x00000030,
-       .dram_reset = 0x00000030,
-};
-
-static struct mx6_mmdc_calibration mx6_mmcd_calib = {
-       .p0_mpwldectrl0 = 0x00070007,
-       .p0_mpdgctrl0 = 0x41490145,
-       .p0_mprddlctl = 0x40404546,
-       .p0_mpwrdlctl = 0x4040524D,
-};
-
-struct mx6_ddr_sysinfo ddr_sysinfo = {
-       .dsize = 0,
-       .cs_density = 20,
-       .ncs = 1,
-       .cs1_mirror = 0,
-       .rtt_wr = 2,
-       .rtt_nom = 1,           /* RTT_Nom = RZQ/2 */
-       .walat = 1,             /* Write additional latency */
-       .ralat = 5,             /* Read additional latency */
-       .mif3_mode = 3,         /* Command prediction working mode */
-       .bi_on = 1,             /* Bank interleaving enabled */
-       .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
-       .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
-       .ddr_type = DDR_TYPE_DDR3,
-};
-
-static struct mx6_ddr3_cfg mem_ddr = {
-       .mem_speed = 800,
-       .density = 4,
-       .width = 16,
-       .banks = 8,
-       .rowaddr = 13,
-       .coladdr = 10,
-       .pagesz = 2,
-       .trcd = 1375,
-       .trcmin = 4875,
-       .trasmin = 3500,
-};
-
-static void ccgr_init(void)
-{
-       struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
-       writel(0xFFFFFFFF, &ccm->CCGR0);
-       writel(0xFFFFFFFF, &ccm->CCGR1);
-       writel(0xFFFFFFFF, &ccm->CCGR2);
-       writel(0xFFFFFFFF, &ccm->CCGR3);
-       writel(0xFFFFFFFF, &ccm->CCGR4);
-       writel(0xFFFFFFFF, &ccm->CCGR5);
-       writel(0xFFFFFFFF, &ccm->CCGR6);
-       writel(0xFFFFFFFF, &ccm->CCGR7);
-}
-
-static void spl_dram_init(void)
-{
-       mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
-       mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
-}
-
-void board_init_f(ulong dummy)
-{
-       /* setup AIPS and disable watchdog */
-       arch_cpu_init();
-
-       ccgr_init();
-
-       /* iomux and setup of i2c */
-       SETUP_IOMUX_PADS(uart1_pads);
-
-       /* setup GP timer */
-       timer_init();
-
-       /* UART clocks enabled and gd valid - init serial console */
-       preloader_console_init();
-
-       /* DDR initialization */
-       spl_dram_init();
-
-       /* Clear the BSS. */
-       memset(__bss_start, 0, __bss_end - __bss_start);
-
-       /* load/boot image from boot device */
-       board_init_r(NULL, 0);
-}
 #endif /* CONFIG_SPL_BUILD */
index d6a63d28950ac4ab59ab4d9d3c253e3a295c31f1..fa365196fcfe2139c255121d1b4abad026407796 100644 (file)
@@ -163,21 +163,8 @@ int dram_init(void)
 }
 
 #ifdef CONFIG_SPL_BUILD
-#include <libfdt.h>
 #include <spl.h>
 
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/mx6-ddr.h>
-
-#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE | \
-                       PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
-                       PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
-
-static iomux_v3_cfg_t const uart1_pads[] = {
-       IOMUX_PADS(PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL)),
-       IOMUX_PADS(PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL)),
-};
-
 /* MMC board initialization is needed till adding DM support in SPL */
 #if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
 #include <mmc.h>
@@ -304,110 +291,4 @@ void board_boot_order(u32 *spl_boot_list)
 }
 #endif
 #endif /* CONFIG_FSL_ESDHC */
-
-static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
-       .grp_addds = 0x00000030,
-       .grp_ddrmode_ctl = 0x00020000,
-       .grp_b0ds = 0x00000030,
-       .grp_ctlds = 0x00000030,
-       .grp_b1ds = 0x00000030,
-       .grp_ddrpke = 0x00000000,
-       .grp_ddrmode = 0x00020000,
-       .grp_ddr_type = 0x000c0000,
-};
-
-static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
-       .dram_dqm0 = 0x00000030,
-       .dram_dqm1 = 0x00000030,
-       .dram_ras = 0x00000030,
-       .dram_cas = 0x00000030,
-       .dram_odt0 = 0x00000030,
-       .dram_odt1 = 0x00000030,
-       .dram_sdba2 = 0x00000000,
-       .dram_sdclk_0 = 0x00000008,
-       .dram_sdqs0 = 0x00000038,
-       .dram_sdqs1 = 0x00000030,
-       .dram_reset = 0x00000030,
-};
-
-static struct mx6_mmdc_calibration mx6_mmcd_calib = {
-       .p0_mpwldectrl0 = 0x00070007,
-       .p0_mpdgctrl0 = 0x41490145,
-       .p0_mprddlctl = 0x40404546,
-       .p0_mpwrdlctl = 0x4040524D,
-};
-
-struct mx6_ddr_sysinfo ddr_sysinfo = {
-       .dsize = 0,
-       .cs_density = 20,
-       .ncs = 1,
-       .cs1_mirror = 0,
-       .rtt_wr = 2,
-       .rtt_nom = 1,           /* RTT_Nom = RZQ/2 */
-       .walat = 1,             /* Write additional latency */
-       .ralat = 5,             /* Read additional latency */
-       .mif3_mode = 3,         /* Command prediction working mode */
-       .bi_on = 1,             /* Bank interleaving enabled */
-       .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
-       .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
-       .ddr_type = DDR_TYPE_DDR3,
-};
-
-static struct mx6_ddr3_cfg mem_ddr = {
-       .mem_speed = 800,
-       .density = 4,
-       .width = 16,
-       .banks = 8,
-       .rowaddr = 15,
-       .coladdr = 10,
-       .pagesz = 2,
-       .trcd = 1375,
-       .trcmin = 4875,
-       .trasmin = 3500,
-};
-
-static void ccgr_init(void)
-{
-       struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
-       writel(0x00c03f3f, &ccm->CCGR0);
-       writel(0xfcffff00, &ccm->CCGR1);
-       writel(0x0cffffcc, &ccm->CCGR2);
-       writel(0x3f3c3030, &ccm->CCGR3);
-       writel(0xff00fffc, &ccm->CCGR4);
-       writel(0x033f30ff, &ccm->CCGR5);
-       writel(0x00c00fff, &ccm->CCGR6);
-}
-
-static void spl_dram_init(void)
-{
-       mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
-       mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
-}
-
-void board_init_f(ulong dummy)
-{
-       /* setup AIPS and disable watchdog */
-       arch_cpu_init();
-
-       ccgr_init();
-
-       /* iomux and setup of i2c */
-       SETUP_IOMUX_PADS(uart1_pads);
-
-       /* setup GP timer */
-       timer_init();
-
-       /* UART clocks enabled and gd valid - init serial console */
-       preloader_console_init();
-
-       /* DDR initialization */
-       spl_dram_init();
-
-       /* Clear the BSS. */
-       memset(__bss_start, 0, __bss_end - __bss_start);
-
-       /* load/boot image from boot device */
-       board_init_r(NULL, 0);
-}
 #endif /* CONFIG_SPL_BUILD */