Changes for U-Boot 1.1.3:
======================================================================
+* Patch by Steven Scholz, 06 Apr 2005:
+ - creating SoC subdir for Atmel AT91RM9200 cpu/arm920t/at91rm9200
+ - moving code out of cpu/at91rm9200 into cpu/arm920t/at91rm9200
+
* Patches by Robert Whaley, 29 Nov 2004:
- update the pxa-regs.h file for PXA27x chips
- add PXA27x based ADSVIX board
xtract_omap730p2 = $(subst _cs0boot,,$(subst _cs3boot,, $(subst _config,,$1)))
+at91rm9200dk_config : unconfig
+ @./mkconfig $(@:_config=) arm arm920t at91rm9200dk NULL at91rm9200
+
+cmc_pu2_config : unconfig
+ @./mkconfig $(@:_config=) arm arm920t cmc_pu2 NULL at91rm9200
+
integratorap_config : unconfig
@./mkconfig $(@:_config=) arm arm926ejs integratorap
evb4510_config : unconfig
@./mkconfig $(@:_config=) arm arm720t evb4510
-#########################################################################
-## AT91RM9200 Systems
-#########################################################################
-
-at91rm9200dk_config : unconfig
- @./mkconfig $(@:_config=) arm at91rm9200 at91rm9200dk
-
-cmc_pu2_config : unconfig
- @./mkconfig $(@:_config=) arm at91rm9200 cmc_pu2
-
#########################################################################
## XScale Systems
#########################################################################
- 74xx_7xx Files specific to Freescale MPC74xx and 7xx CPUs
- arm720t Files specific to ARM 720 CPUs
- arm920t Files specific to ARM 920 CPUs
+ - at91rm9200 Files specific to Atmel AT91RM9200 CPU
- imx Files specific to Freescale MC9328 i.MX CPUs
- s3c24x0 Files specific to Samsung S3C24X0 CPUs
- arm925t Files specific to ARM 925 CPUs
- arm926ejs Files specific to ARM 926 CPUs
- arm1136 Files specific to ARM 1136 CPUs
- - at91rm9200 Files specific to Atmel AT91RM9200 CPUs
- i386 Files specific to i386 CPUs
- ixp Files specific to Intel XScale IXP CPUs
- mcf52x2 Files specific to Freescale ColdFire MCF52x2 CPUs
LIB = lib$(BOARD).a
OBJS := adsvix.o pcmcia.o
-SOBJS := memsetup.o pxavoltage.o
+SOBJS := lowlevel_init.o pxavoltage.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
--- /dev/null
+/*
+ * This was originally from the Lubbock u-boot port.
+ *
+ * Most of this taken from Redboot hal_platform_setup.h with cleanup
+ *
+ * NOTE: I haven't clean this up considerably, just enough to get it
+ * running. See hal_platform_setup.h for the source. See
+ * board/cradle/lowlevel_init.S for another PXA250 setup that is
+ * much cleaner.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+
+/* wait for coprocessor write complete */
+ .macro CPWAIT reg
+ mrc p15,0,\reg,c2,c0,0
+ mov \reg,\reg
+ sub pc,pc,#4
+ .endm
+
+
+/*
+ * Memory setup
+ */
+
+.globl lowlevel_init
+lowlevel_init:
+
+ /* Set up GPIO pins first ----------------------------------------- */
+
+ ldr r0, =GPSR0
+ ldr r1, =CFG_GPSR0_VAL
+ str r1, [r0]
+
+ ldr r0, =GPSR1
+ ldr r1, =CFG_GPSR1_VAL
+ str r1, [r0]
+
+ ldr r0, =GPSR2
+ ldr r1, =CFG_GPSR2_VAL
+ str r1, [r0]
+
+ ldr r0, =GPSR3
+ ldr r1, =CFG_GPSR3_VAL
+ str r1, [r0]
+
+ ldr r0, =GPCR0
+ ldr r1, =CFG_GPCR0_VAL
+ str r1, [r0]
+
+ ldr r0, =GPCR1
+ ldr r1, =CFG_GPCR1_VAL
+ str r1, [r0]
+
+ ldr r0, =GPCR2
+ ldr r1, =CFG_GPCR2_VAL
+ str r1, [r0]
+
+ ldr r0, =GPCR3
+ ldr r1, =CFG_GPCR3_VAL
+ str r1, [r0]
+
+ ldr r0, =GPDR0
+ ldr r1, =CFG_GPDR0_VAL
+ str r1, [r0]
+
+ ldr r0, =GPDR1
+ ldr r1, =CFG_GPDR1_VAL
+ str r1, [r0]
+
+ ldr r0, =GPDR2
+ ldr r1, =CFG_GPDR2_VAL
+ str r1, [r0]
+
+ ldr r0, =GPDR3
+ ldr r1, =CFG_GPDR3_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR0_L
+ ldr r1, =CFG_GAFR0_L_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR0_U
+ ldr r1, =CFG_GAFR0_U_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR1_L
+ ldr r1, =CFG_GAFR1_L_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR1_U
+ ldr r1, =CFG_GAFR1_U_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR2_L
+ ldr r1, =CFG_GAFR2_L_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR2_U
+ ldr r1, =CFG_GAFR2_U_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR3_L
+ ldr r1, =CFG_GAFR3_L_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR3_U
+ ldr r1, =CFG_GAFR3_U_VAL
+ str r1, [r0]
+
+ ldr r0, =PSSR /* enable GPIO pins */
+ ldr r1, =CFG_PSSR_VAL
+ str r1, [r0]
+
+ /* ---------------------------------------------------------------- */
+ /* Enable memory interface */
+ /* */
+ /* The sequence below is based on the recommended init steps */
+ /* detailed in the Intel PXA250 Operating Systems Developers Guide, */
+ /* Chapter 10. */
+ /* ---------------------------------------------------------------- */
+
+ /* ---------------------------------------------------------------- */
+ /* Step 1: Wait for at least 200 microsedonds to allow internal */
+ /* clocks to settle. Only necessary after hard reset... */
+ /* FIXME: can be optimized later */
+ /* ---------------------------------------------------------------- */
+
+ ldr r3, =OSCR /* reset the OS Timer Count to zero */
+ mov r2, #0
+ str r2, [r3]
+ ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
+ /* so 0x300 should be plenty */
+1:
+ ldr r2, [r3]
+ cmp r4, r2
+ bgt 1b
+
+mem_init:
+
+ ldr r1, =MEMC_BASE /* get memory controller base addr. */
+
+ /* ---------------------------------------------------------------- */
+ /* Step 2a: Initialize Asynchronous static memory controller */
+ /* ---------------------------------------------------------------- */
+
+ /* MSC registers: timing, bus width, mem type */
+
+ /* MSC0: nCS(0,1) */
+ ldr r2, =CFG_MSC0_VAL
+ str r2, [r1, #MSC0_OFFSET]
+ ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
+ /* that data latches */
+ /* MSC1: nCS(2,3) */
+ ldr r2, =CFG_MSC1_VAL
+ str r2, [r1, #MSC1_OFFSET]
+ ldr r2, [r1, #MSC1_OFFSET]
+
+ /* MSC2: nCS(4,5) */
+ ldr r2, =CFG_MSC2_VAL
+ str r2, [r1, #MSC2_OFFSET]
+ ldr r2, [r1, #MSC2_OFFSET]
+
+ /* ---------------------------------------------------------------- */
+ /* Step 2b: Initialize Card Interface */
+ /* ---------------------------------------------------------------- */
+
+ /* MECR: Memory Expansion Card Register */
+ ldr r2, =CFG_MECR_VAL
+ str r2, [r1, #MECR_OFFSET]
+ ldr r2, [r1, #MECR_OFFSET]
+
+ /* MCMEM0: Card Interface slot 0 timing */
+ ldr r2, =CFG_MCMEM0_VAL
+ str r2, [r1, #MCMEM0_OFFSET]
+ ldr r2, [r1, #MCMEM0_OFFSET]
+
+ /* MCMEM1: Card Interface slot 1 timing */
+ ldr r2, =CFG_MCMEM1_VAL
+ str r2, [r1, #MCMEM1_OFFSET]
+ ldr r2, [r1, #MCMEM1_OFFSET]
+
+ /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
+ ldr r2, =CFG_MCATT0_VAL
+ str r2, [r1, #MCATT0_OFFSET]
+ ldr r2, [r1, #MCATT0_OFFSET]
+
+ /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
+ ldr r2, =CFG_MCATT1_VAL
+ str r2, [r1, #MCATT1_OFFSET]
+ ldr r2, [r1, #MCATT1_OFFSET]
+
+ /* MCIO0: Card Interface I/O Space Timing, slot 0 */
+ ldr r2, =CFG_MCIO0_VAL
+ str r2, [r1, #MCIO0_OFFSET]
+ ldr r2, [r1, #MCIO0_OFFSET]
+
+ /* MCIO1: Card Interface I/O Space Timing, slot 1 */
+ ldr r2, =CFG_MCIO1_VAL
+ str r2, [r1, #MCIO1_OFFSET]
+ ldr r2, [r1, #MCIO1_OFFSET]
+
+ /* ---------------------------------------------------------------- */
+ /* Step 2c: Write FLYCNFG FIXME: what's that??? */
+ /* ---------------------------------------------------------------- */
+ ldr r2, =CFG_FLYCNFG_VAL
+ str r2, [r1, #FLYCNFG_OFFSET]
+ str r2, [r1, #FLYCNFG_OFFSET]
+
+ /* ---------------------------------------------------------------- */
+ /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
+ /* ---------------------------------------------------------------- */
+
+ /* Before accessing MDREFR we need a valid DRI field, so we set */
+ /* this to power on defaults + DRI field. */
+
+ ldr r4, [r1, #MDREFR_OFFSET]
+ ldr r2, =0xFFF
+ bic r4, r4, r2
+
+ ldr r3, =CFG_MDREFR_VAL
+ and r3, r3, r2
+
+ orr r4, r4, r3
+ str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
+
+ orr r4, r4, #MDREFR_K0RUN
+ orr r4, r4, #MDREFR_K0DB4
+ orr r4, r4, #MDREFR_K0FREE
+ orr r4, r4, #MDREFR_K0DB2
+ orr r4, r4, #MDREFR_K1DB2
+ bic r4, r4, #MDREFR_K1FREE
+ bic r4, r4, #MDREFR_K2FREE
+
+ str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
+ ldr r4, [r1, #MDREFR_OFFSET]
+
+ /* Note: preserve the mdrefr value in r4 */
+
+
+ /* ---------------------------------------------------------------- */
+ /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
+ /* ---------------------------------------------------------------- */
+
+ /* Initialize SXCNFG register. Assert the enable bits */
+
+ /* Write SXMRS to cause an MRS command to all enabled banks of */
+ /* synchronous static memory. Note that SXLCR need not be written */
+ /* at this time. */
+
+ ldr r2, =CFG_SXCNFG_VAL
+ str r2, [r1, #SXCNFG_OFFSET]
+
+ /* ---------------------------------------------------------------- */
+ /* Step 4: Initialize SDRAM */
+ /* ---------------------------------------------------------------- */
+
+ bic r4, r4, #(MDREFR_K2FREE |MDREFR_K1FREE | MDREFR_K0FREE)
+
+ orr r4, r4, #MDREFR_K1RUN
+ bic r4, r4, #MDREFR_K2DB2
+ str r4, [r1, #MDREFR_OFFSET]
+ ldr r4, [r1, #MDREFR_OFFSET]
+
+ bic r4, r4, #MDREFR_SLFRSH
+ str r4, [r1, #MDREFR_OFFSET]
+ ldr r4, [r1, #MDREFR_OFFSET]
+
+ orr r4, r4, #MDREFR_E1PIN
+ str r4, [r1, #MDREFR_OFFSET]
+ ldr r4, [r1, #MDREFR_OFFSET]
+
+ nop
+ nop
+
+
+ /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */
+ /* configure but not enable each SDRAM partition pair. */
+
+ ldr r4, =CFG_MDCNFG_VAL
+ bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
+ bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3)
+
+ str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
+ ldr r4, [r1, #MDCNFG_OFFSET]
+
+
+ /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
+ /* 100..200 µsec. */
+
+ ldr r3, =OSCR /* reset the OS Timer Count to zero */
+ mov r2, #0
+ str r2, [r3]
+ ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
+ /* so 0x300 should be plenty */
+1:
+ ldr r2, [r3]
+ cmp r4, r2
+ bgt 1b
+
+
+ /* Step 4f: Trigger a number (usually 8) refresh cycles by */
+ /* attempting non-burst read or write accesses to disabled */
+ /* SDRAM, as commonly specified in the power up sequence */
+ /* documented in SDRAM data sheets. The address(es) used */
+ /* for this purpose must not be cacheable. */
+
+ ldr r3, =CFG_DRAM_BASE
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+ str r2, [r3]
+
+
+ /* Step 4g: Write MDCNFG with enable bits asserted */
+ /* (MDCNFG:DEx set to 1). */
+
+ ldr r3, [r1, #MDCNFG_OFFSET]
+ mov r4, r3
+ orr r3, r3, #MDCNFG_DE0
+ str r3, [r1, #MDCNFG_OFFSET]
+ mov r0, r3
+
+ /* Step 4h: Write MDMRS. */
+
+ ldr r2, =CFG_MDMRS_VAL
+ str r2, [r1, #MDMRS_OFFSET]
+
+ /* enable APD */
+ ldr r3, [r1, #MDREFR_OFFSET]
+ orr r3, r3, #MDREFR_APD
+ str r3, [r1, #MDREFR_OFFSET]
+
+ /* We are finished with Intel's memory controller initialisation */
+
+setvoltage:
+
+ mov r10, lr
+ bl initPXAvoltage /* In case the board is rebooting with a */
+ mov lr, r10 /* low voltage raise it up to a good one. */
+
+wakeup:
+ /* Are we waking from sleep? */
+ ldr r0, =RCSR
+ ldr r1, [r0]
+ and r1, r1, #(RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR)
+ str r1, [r0]
+ teq r1, #RCSR_SMR
+
+ bne initirqs
+
+ ldr r0, =PSSR
+ mov r1, #PSSR_PH
+ str r1, [r0]
+
+ /* if so, resume at PSPR */
+ ldr r0, =PSPR
+ ldr r1, [r0]
+ mov pc, r1
+
+ /* ---------------------------------------------------------------- */
+ /* Disable (mask) all interrupts at interrupt controller */
+ /* ---------------------------------------------------------------- */
+
+initirqs:
+
+ mov r1, #0 /* clear int. level register (IRQ, not FIQ) */
+ ldr r2, =ICLR
+ str r1, [r2]
+
+ ldr r2, =ICMR /* mask all interrupts at the controller */
+ str r1, [r2]
+
+ /* ---------------------------------------------------------------- */
+ /* Clock initialisation */
+ /* ---------------------------------------------------------------- */
+
+initclks:
+
+ /* Disable the peripheral clocks, and set the core clock frequency */
+
+ /* Turn Off on-chip peripheral clocks (except for memory) */
+ /* for re-configuration. */
+ ldr r1, =CKEN
+ ldr r2, =CFG_CKEN
+ str r2, [r1]
+
+ /* ... and write the core clock config register */
+ ldr r2, =CFG_CCCR
+ ldr r1, =CCCR
+ str r2, [r1]
+
+ /* Turn on turbo mode */
+ mrc p14, 0, r2, c6, c0, 0
+ orr r2, r2, #0xB /* Turbo, Fast-Bus, Freq change**/
+ mcr p14, 0, r2, c6, c0, 0
+
+ /* Re-write MDREFR */
+ ldr r1, =MEMC_BASE
+ ldr r2, [r1, #MDREFR_OFFSET]
+ str r2, [r1, #MDREFR_OFFSET]
+#ifdef RTC
+ /* enable the 32Khz oscillator for RTC and PowerManager */
+ ldr r1, =OSCC
+ mov r2, #OSCC_OON
+ str r2, [r1]
+
+ /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */
+ /* has settled. */
+60:
+ ldr r2, [r1]
+ ands r2, r2, #1
+ beq 60b
+#else
+#error "RTC not defined"
+#endif
+
+ /* Interrupt init: Mask all interrupts */
+ ldr r0, =ICMR /* enable no sources */
+ mov r1, #0
+ str r1, [r0]
+ /* FIXME */
+
+#ifdef NODEBUG
+ /*Disable software and data breakpoints */
+ mov r0,#0
+ mcr p15,0,r0,c14,c8,0 /* ibcr0 */
+ mcr p15,0,r0,c14,c9,0 /* ibcr1 */
+ mcr p15,0,r0,c14,c4,0 /* dbcon */
+
+ /*Enable all debug functionality */
+ mov r0,#0x80000000
+ mcr p14,0,r0,c10,c0,0 /* dcsr */
+#endif
+
+ /* ---------------------------------------------------------------- */
+ /* End lowlevel_init */
+ /* ---------------------------------------------------------------- */
+
+endlowlevel_init:
+
+ mov pc, lr
+++ /dev/null
-/*
- * This was originally from the Lubbock u-boot port.
- *
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * NOTE: I haven't clean this up considerably, just enough to get it
- * running. See hal_platform_setup.h for the source. See
- * board/cradle/memsetup.S for another PXA250 setup that is
- * much cleaner.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/pxa-regs.h>
-
-/* wait for coprocessor write complete */
- .macro CPWAIT reg
- mrc p15,0,\reg,c2,c0,0
- mov \reg,\reg
- sub pc,pc,#4
- .endm
-
-
-/*
- * Memory setup
- */
-
-.globl memsetup
-memsetup:
-
- /* Set up GPIO pins first ----------------------------------------- */
-
- ldr r0, =GPSR0
- ldr r1, =CFG_GPSR0_VAL
- str r1, [r0]
-
- ldr r0, =GPSR1
- ldr r1, =CFG_GPSR1_VAL
- str r1, [r0]
-
- ldr r0, =GPSR2
- ldr r1, =CFG_GPSR2_VAL
- str r1, [r0]
-
- ldr r0, =GPSR3
- ldr r1, =CFG_GPSR3_VAL
- str r1, [r0]
-
- ldr r0, =GPCR0
- ldr r1, =CFG_GPCR0_VAL
- str r1, [r0]
-
- ldr r0, =GPCR1
- ldr r1, =CFG_GPCR1_VAL
- str r1, [r0]
-
- ldr r0, =GPCR2
- ldr r1, =CFG_GPCR2_VAL
- str r1, [r0]
-
- ldr r0, =GPCR3
- ldr r1, =CFG_GPCR3_VAL
- str r1, [r0]
-
- ldr r0, =GPDR0
- ldr r1, =CFG_GPDR0_VAL
- str r1, [r0]
-
- ldr r0, =GPDR1
- ldr r1, =CFG_GPDR1_VAL
- str r1, [r0]
-
- ldr r0, =GPDR2
- ldr r1, =CFG_GPDR2_VAL
- str r1, [r0]
-
- ldr r0, =GPDR3
- ldr r1, =CFG_GPDR3_VAL
- str r1, [r0]
-
- ldr r0, =GAFR0_L
- ldr r1, =CFG_GAFR0_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR0_U
- ldr r1, =CFG_GAFR0_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR1_L
- ldr r1, =CFG_GAFR1_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR1_U
- ldr r1, =CFG_GAFR1_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR2_L
- ldr r1, =CFG_GAFR2_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR2_U
- ldr r1, =CFG_GAFR2_U_VAL
- str r1, [r0]
-
- ldr r0, =GAFR3_L
- ldr r1, =CFG_GAFR3_L_VAL
- str r1, [r0]
-
- ldr r0, =GAFR3_U
- ldr r1, =CFG_GAFR3_U_VAL
- str r1, [r0]
-
- ldr r0, =PSSR /* enable GPIO pins */
- ldr r1, =CFG_PSSR_VAL
- str r1, [r0]
-
- /* ---------------------------------------------------------------- */
- /* Enable memory interface */
- /* */
- /* The sequence below is based on the recommended init steps */
- /* detailed in the Intel PXA250 Operating Systems Developers Guide, */
- /* Chapter 10. */
- /* ---------------------------------------------------------------- */
-
- /* ---------------------------------------------------------------- */
- /* Step 1: Wait for at least 200 microsedonds to allow internal */
- /* clocks to settle. Only necessary after hard reset... */
- /* FIXME: can be optimized later */
- /* ---------------------------------------------------------------- */
-
- ldr r3, =OSCR /* reset the OS Timer Count to zero */
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
- /* so 0x300 should be plenty */
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
-mem_init:
-
- ldr r1, =MEMC_BASE /* get memory controller base addr. */
-
- /* ---------------------------------------------------------------- */
- /* Step 2a: Initialize Asynchronous static memory controller */
- /* ---------------------------------------------------------------- */
-
- /* MSC registers: timing, bus width, mem type */
-
- /* MSC0: nCS(0,1) */
- ldr r2, =CFG_MSC0_VAL
- str r2, [r1, #MSC0_OFFSET]
- ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
- /* that data latches */
- /* MSC1: nCS(2,3) */
- ldr r2, =CFG_MSC1_VAL
- str r2, [r1, #MSC1_OFFSET]
- ldr r2, [r1, #MSC1_OFFSET]
-
- /* MSC2: nCS(4,5) */
- ldr r2, =CFG_MSC2_VAL
- str r2, [r1, #MSC2_OFFSET]
- ldr r2, [r1, #MSC2_OFFSET]
-
- /* ---------------------------------------------------------------- */
- /* Step 2b: Initialize Card Interface */
- /* ---------------------------------------------------------------- */
-
- /* MECR: Memory Expansion Card Register */
- ldr r2, =CFG_MECR_VAL
- str r2, [r1, #MECR_OFFSET]
- ldr r2, [r1, #MECR_OFFSET]
-
- /* MCMEM0: Card Interface slot 0 timing */
- ldr r2, =CFG_MCMEM0_VAL
- str r2, [r1, #MCMEM0_OFFSET]
- ldr r2, [r1, #MCMEM0_OFFSET]
-
- /* MCMEM1: Card Interface slot 1 timing */
- ldr r2, =CFG_MCMEM1_VAL
- str r2, [r1, #MCMEM1_OFFSET]
- ldr r2, [r1, #MCMEM1_OFFSET]
-
- /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
- ldr r2, =CFG_MCATT0_VAL
- str r2, [r1, #MCATT0_OFFSET]
- ldr r2, [r1, #MCATT0_OFFSET]
-
- /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
- ldr r2, =CFG_MCATT1_VAL
- str r2, [r1, #MCATT1_OFFSET]
- ldr r2, [r1, #MCATT1_OFFSET]
-
- /* MCIO0: Card Interface I/O Space Timing, slot 0 */
- ldr r2, =CFG_MCIO0_VAL
- str r2, [r1, #MCIO0_OFFSET]
- ldr r2, [r1, #MCIO0_OFFSET]
-
- /* MCIO1: Card Interface I/O Space Timing, slot 1 */
- ldr r2, =CFG_MCIO1_VAL
- str r2, [r1, #MCIO1_OFFSET]
- ldr r2, [r1, #MCIO1_OFFSET]
-
- /* ---------------------------------------------------------------- */
- /* Step 2c: Write FLYCNFG FIXME: what's that??? */
- /* ---------------------------------------------------------------- */
- ldr r2, =CFG_FLYCNFG_VAL
- str r2, [r1, #FLYCNFG_OFFSET]
- str r2, [r1, #FLYCNFG_OFFSET]
-
- /* ---------------------------------------------------------------- */
- /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
- /* ---------------------------------------------------------------- */
-
- /* Before accessing MDREFR we need a valid DRI field, so we set */
- /* this to power on defaults + DRI field. */
-
- ldr r4, [r1, #MDREFR_OFFSET]
- ldr r2, =0xFFF
- bic r4, r4, r2
-
- ldr r3, =CFG_MDREFR_VAL
- and r3, r3, r2
-
- orr r4, r4, r3
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
-
- orr r4, r4, #MDREFR_K0RUN
- orr r4, r4, #MDREFR_K0DB4
- orr r4, r4, #MDREFR_K0FREE
- orr r4, r4, #MDREFR_K0DB2
- orr r4, r4, #MDREFR_K1DB2
- bic r4, r4, #MDREFR_K1FREE
- bic r4, r4, #MDREFR_K2FREE
-
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
-
- /* Note: preserve the mdrefr value in r4 */
-
-
- /* ---------------------------------------------------------------- */
- /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
- /* ---------------------------------------------------------------- */
-
- /* Initialize SXCNFG register. Assert the enable bits */
-
- /* Write SXMRS to cause an MRS command to all enabled banks of */
- /* synchronous static memory. Note that SXLCR need not be written */
- /* at this time. */
-
- ldr r2, =CFG_SXCNFG_VAL
- str r2, [r1, #SXCNFG_OFFSET]
-
- /* ---------------------------------------------------------------- */
- /* Step 4: Initialize SDRAM */
- /* ---------------------------------------------------------------- */
-
- bic r4, r4, #(MDREFR_K2FREE |MDREFR_K1FREE | MDREFR_K0FREE)
-
- orr r4, r4, #MDREFR_K1RUN
- bic r4, r4, #MDREFR_K2DB2
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
-
- bic r4, r4, #MDREFR_SLFRSH
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
-
- orr r4, r4, #MDREFR_E1PIN
- str r4, [r1, #MDREFR_OFFSET]
- ldr r4, [r1, #MDREFR_OFFSET]
-
- nop
- nop
-
-
- /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */
- /* configure but not enable each SDRAM partition pair. */
-
- ldr r4, =CFG_MDCNFG_VAL
- bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
- bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3)
-
- str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
- ldr r4, [r1, #MDCNFG_OFFSET]
-
-
- /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
- /* 100..200 µsec. */
-
- ldr r3, =OSCR /* reset the OS Timer Count to zero */
- mov r2, #0
- str r2, [r3]
- ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
- /* so 0x300 should be plenty */
-1:
- ldr r2, [r3]
- cmp r4, r2
- bgt 1b
-
-
- /* Step 4f: Trigger a number (usually 8) refresh cycles by */
- /* attempting non-burst read or write accesses to disabled */
- /* SDRAM, as commonly specified in the power up sequence */
- /* documented in SDRAM data sheets. The address(es) used */
- /* for this purpose must not be cacheable. */
-
- ldr r3, =CFG_DRAM_BASE
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
- str r2, [r3]
-
-
- /* Step 4g: Write MDCNFG with enable bits asserted */
- /* (MDCNFG:DEx set to 1). */
-
- ldr r3, [r1, #MDCNFG_OFFSET]
- mov r4, r3
- orr r3, r3, #MDCNFG_DE0
- str r3, [r1, #MDCNFG_OFFSET]
- mov r0, r3
-
- /* Step 4h: Write MDMRS. */
-
- ldr r2, =CFG_MDMRS_VAL
- str r2, [r1, #MDMRS_OFFSET]
-
- /* enable APD */
- ldr r3, [r1, #MDREFR_OFFSET]
- orr r3, r3, #MDREFR_APD
- str r3, [r1, #MDREFR_OFFSET]
-
- /* We are finished with Intel's memory controller initialisation */
-
-setvoltage:
-
- mov r10, lr
- bl initPXAvoltage /* In case the board is rebooting with a */
- mov lr, r10 /* low voltage raise it up to a good one. */
-
-wakeup:
- /* Are we waking from sleep? */
- ldr r0, =RCSR
- ldr r1, [r0]
- and r1, r1, #(RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR)
- str r1, [r0]
- teq r1, #RCSR_SMR
-
- bne initirqs
-
- ldr r0, =PSSR
- mov r1, #PSSR_PH
- str r1, [r0]
-
- /* if so, resume at PSPR */
- ldr r0, =PSPR
- ldr r1, [r0]
- mov pc, r1
-
- /* ---------------------------------------------------------------- */
- /* Disable (mask) all interrupts at interrupt controller */
- /* ---------------------------------------------------------------- */
-
-initirqs:
-
- mov r1, #0 /* clear int. level register (IRQ, not FIQ) */
- ldr r2, =ICLR
- str r1, [r2]
-
- ldr r2, =ICMR /* mask all interrupts at the controller */
- str r1, [r2]
-
- /* ---------------------------------------------------------------- */
- /* Clock initialisation */
- /* ---------------------------------------------------------------- */
-
-initclks:
-
- /* Disable the peripheral clocks, and set the core clock frequency */
-
- /* Turn Off on-chip peripheral clocks (except for memory) */
- /* for re-configuration. */
- ldr r1, =CKEN
- ldr r2, =CFG_CKEN
- str r2, [r1]
-
- /* ... and write the core clock config register */
- ldr r2, =CFG_CCCR
- ldr r1, =CCCR
- str r2, [r1]
-
- /* Turn on turbo mode */
- mrc p14, 0, r2, c6, c0, 0
- orr r2, r2, #0xB /* Turbo, Fast-Bus, Freq change**/
- mcr p14, 0, r2, c6, c0, 0
-
- /* Re-write MDREFR */
- ldr r1, =MEMC_BASE
- ldr r2, [r1, #MDREFR_OFFSET]
- str r2, [r1, #MDREFR_OFFSET]
-#ifdef RTC
- /* enable the 32Khz oscillator for RTC and PowerManager */
- ldr r1, =OSCC
- mov r2, #OSCC_OON
- str r2, [r1]
-
- /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */
- /* has settled. */
-60:
- ldr r2, [r1]
- ands r2, r2, #1
- beq 60b
-#else
-#error "RTC not defined"
-#endif
-
- /* Interrupt init: Mask all interrupts */
- ldr r0, =ICMR /* enable no sources */
- mov r1, #0
- str r1, [r0]
- /* FIXME */
-
-// #define NODEBUG
-#ifdef NODEBUG
- /*Disable software and data breakpoints */
- mov r0,#0
- mcr p15,0,r0,c14,c8,0 /* ibcr0 */
- mcr p15,0,r0,c14,c9,0 /* ibcr1 */
- mcr p15,0,r0,c14,c4,0 /* dbcon */
-
- /*Enable all debug functionality */
- mov r0,#0x80000000
- mcr p14,0,r0,c10,c0,0 /* dcsr */
-
-#endif
-
- /* ---------------------------------------------------------------- */
- /* End memsetup */
- /* ---------------------------------------------------------------- */
-
-endmemsetup:
-
- mov pc, lr
. = ALIGN(4);
.text :
{
- cpu/at91rm9200/start.o (.text)
+ cpu/arm920t/start.o (.text)
*(.text)
}
. = ALIGN(4);
.text :
{
- cpu/at91rm9200/start.o (.text)
+ cpu/arm920t/start.o (.text)
*(.text)
}
--- /dev/null
+#
+# (C) Copyright 2000-2005
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(SOC).a
+
+OBJS = ether.o i2c.o interrupts.o serial.o
+SOBJS = lowlevel_init.o
+
+all: .depend $(LIB)
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS) $(SOBJS)
+
+#########################################################################
+
+.depend: Makefile $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- /dev/null
+/*
+ * (C) Copyright 2003
+ * Author : Hamid Ikdoumi (Atmel)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <at91rm9200_net.h>
+#include <net.h>
+
+/* ----- Ethernet Buffer definitions ----- */
+
+typedef struct {
+ unsigned long addr, size;
+} rbf_t;
+
+#define RBF_ADDR 0xfffffffc
+#define RBF_OWNER (1<<0)
+#define RBF_WRAP (1<<1)
+#define RBF_BROADCAST (1<<31)
+#define RBF_MULTICAST (1<<30)
+#define RBF_UNICAST (1<<29)
+#define RBF_EXTERNAL (1<<28)
+#define RBF_UNKOWN (1<<27)
+#define RBF_SIZE 0x07ff
+#define RBF_LOCAL4 (1<<26)
+#define RBF_LOCAL3 (1<<25)
+#define RBF_LOCAL2 (1<<24)
+#define RBF_LOCAL1 (1<<23)
+
+/* Emac Buffers in last 512KBytes of SDRAM*/
+/* Be careful, buffer size is limited to 512KBytes !!! */
+#define RBF_FRAMEMAX 100
+/*#define RBF_FRAMEMEM 0x200000 */
+#define RBF_FRAMEMEM 0x21F80000
+#define RBF_FRAMELEN 0x600
+
+#define RBF_FRAMEBTD RBF_FRAMEMEM
+#define RBF_FRAMEBUF (RBF_FRAMEMEM + RBF_FRAMEMAX*sizeof(rbf_t))
+
+
+#ifdef CONFIG_DRIVER_ETHER
+
+#if (CONFIG_COMMANDS & CFG_CMD_NET)
+
+/* structure to interface the PHY */
+AT91S_PhyOps PhyOps;
+
+AT91PS_EMAC p_mac;
+
+/*********** EMAC Phy layer Management functions *************************/
+/*
+ * Name:
+ * at91rm9200_EmacEnableMDIO
+ * Description:
+ * Enables the MDIO bit in MAC control register
+ * Arguments:
+ * p_mac - pointer to struct AT91S_EMAC
+ * Return value:
+ * none
+ */
+void at91rm9200_EmacEnableMDIO (AT91PS_EMAC p_mac)
+{
+ /* Mac CTRL reg set for MDIO enable */
+ p_mac->EMAC_CTL |= AT91C_EMAC_MPE; /* Management port enable */
+}
+
+/*
+ * Name:
+ * at91rm9200_EmacDisableMDIO
+ * Description:
+ * Disables the MDIO bit in MAC control register
+ * Arguments:
+ * p_mac - pointer to struct AT91S_EMAC
+ * Return value:
+ * none
+ */
+void at91rm9200_EmacDisableMDIO (AT91PS_EMAC p_mac)
+{
+ /* Mac CTRL reg set for MDIO disable */
+ p_mac->EMAC_CTL &= ~AT91C_EMAC_MPE; /* Management port disable */
+}
+
+
+/*
+ * Name:
+ * at91rm9200_EmacReadPhy
+ * Description:
+ * Reads data from the PHY register
+ * Arguments:
+ * dev - pointer to struct net_device
+ * RegisterAddress - unsigned char
+ * pInput - pointer to value read from register
+ * Return value:
+ * TRUE - if data read successfully
+ */
+UCHAR at91rm9200_EmacReadPhy (AT91PS_EMAC p_mac,
+ unsigned char RegisterAddress,
+ unsigned short *pInput)
+{
+ p_mac->EMAC_MAN = (AT91C_EMAC_HIGH & ~AT91C_EMAC_LOW) |
+ (AT91C_EMAC_RW_R) |
+ (RegisterAddress << 18) |
+ (AT91C_EMAC_CODE_802_3);
+
+ udelay (10000);
+
+ *pInput = (unsigned short) p_mac->EMAC_MAN;
+
+ return TRUE;
+}
+
+
+/*
+ * Name:
+ * at91rm9200_EmacWritePhy
+ * Description:
+ * Writes data to the PHY register
+ * Arguments:
+ * dev - pointer to struct net_device
+ * RegisterAddress - unsigned char
+ * pOutput - pointer to value to be written in the register
+ * Return value:
+ * TRUE - if data read successfully
+ */
+UCHAR at91rm9200_EmacWritePhy (AT91PS_EMAC p_mac,
+ unsigned char RegisterAddress,
+ unsigned short *pOutput)
+{
+ p_mac->EMAC_MAN = (AT91C_EMAC_HIGH & ~AT91C_EMAC_LOW) |
+ AT91C_EMAC_CODE_802_3 | AT91C_EMAC_RW_W |
+ (RegisterAddress << 18) | *pOutput;
+
+ udelay (10000);
+
+ return TRUE;
+}
+
+
+rbf_t *rbfdt;
+rbf_t *rbfp;
+
+int eth_init (bd_t * bd)
+{
+ int ret;
+ int i;
+
+ p_mac = AT91C_BASE_EMAC;
+
+ /* PIO Disable Register */
+ *AT91C_PIOA_PDR = AT91C_PA16_EMDIO | AT91C_PA15_EMDC | AT91C_PA14_ERXER |
+ AT91C_PA13_ERX1 | AT91C_PA12_ERX0 | AT91C_PA11_ECRS_ECRSDV |
+ AT91C_PA10_ETX1 | AT91C_PA9_ETX0 | AT91C_PA8_ETXEN |
+ AT91C_PA7_ETXCK_EREFCK;
+
+#ifdef CONFIG_AT91C_USE_RMII
+ *AT91C_PIOB_PDR = AT91C_PB19_ERXCK;
+ *AT91C_PIOB_BSR = AT91C_PB19_ERXCK;
+#else
+ *AT91C_PIOB_PDR = AT91C_PB19_ERXCK | AT91C_PB18_ECOL | AT91C_PB17_ERXDV |
+ AT91C_PB16_ERX3 | AT91C_PB15_ERX2 | AT91C_PB14_ETXER |
+ AT91C_PB13_ETX3 | AT91C_PB12_ETX2;
+
+ /* Select B Register */
+ *AT91C_PIOB_BSR = AT91C_PB19_ERXCK | AT91C_PB18_ECOL |
+ AT91C_PB17_ERXDV | AT91C_PB16_ERX3 | AT91C_PB15_ERX2 |
+ AT91C_PB14_ETXER | AT91C_PB13_ETX3 | AT91C_PB12_ETX2;
+#endif
+
+ *AT91C_PMC_PCER = 1 << AT91C_ID_EMAC; /* Peripheral Clock Enable Register */
+
+ p_mac->EMAC_CFG |= AT91C_EMAC_CSR; /* Clear statistics */
+
+ /* Init Ehternet buffers */
+ rbfdt = (rbf_t *) RBF_FRAMEBTD;
+ for (i = 0; i < RBF_FRAMEMAX; i++) {
+ rbfdt[i].addr = RBF_FRAMEBUF + RBF_FRAMELEN * i;
+ rbfdt[i].size = 0;
+ }
+ rbfdt[RBF_FRAMEMAX - 1].addr |= RBF_WRAP;
+ rbfp = &rbfdt[0];
+
+ p_mac->EMAC_SA2L = (bd->bi_enetaddr[3] << 24) | (bd->bi_enetaddr[2] << 16)
+ | (bd->bi_enetaddr[1] << 8) | (bd->bi_enetaddr[0]);
+ p_mac->EMAC_SA2H = (bd->bi_enetaddr[5] << 8) | (bd->bi_enetaddr[4]);
+
+ p_mac->EMAC_RBQP = (long) (&rbfdt[0]);
+ p_mac->EMAC_RSR &= ~(AT91C_EMAC_RSR_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA);
+
+ p_mac->EMAC_CFG = (p_mac->EMAC_CFG | AT91C_EMAC_CAF | AT91C_EMAC_NBC)
+ & ~AT91C_EMAC_CLK;
+
+#ifdef CONFIG_AT91C_USE_RMII
+ p_mac->EMAC_CFG |= AT91C_EMAC_RMII;
+#endif
+
+#if (AT91C_MASTER_CLOCK > 40000000)
+ /* MDIO clock must not exceed 2.5 MHz, so enable MCK divider */
+ p_mac->EMAC_CFG |= AT91C_EMAC_CLK_HCLK_64;
+#endif
+
+ p_mac->EMAC_CTL |= AT91C_EMAC_TE | AT91C_EMAC_RE;
+
+ at91rm92000_GetPhyInterface (& PhyOps);
+
+ if (!PhyOps.IsPhyConnected (p_mac))
+ printf ("PHY not connected!!\n\r");
+
+ /* MII management start from here */
+ if (!(p_mac->EMAC_SR & AT91C_EMAC_LINK)) {
+ if (!(ret = PhyOps.Init (p_mac))) {
+ printf ("MAC: error during MII initialization\n");
+ return 0;
+ }
+ } else {
+ printf ("No link\n\r");
+ return 0;
+ }
+
+ return 0;
+}
+
+int eth_send (volatile void *packet, int length)
+{
+ while (!(p_mac->EMAC_TSR & AT91C_EMAC_BNQ));
+ p_mac->EMAC_TAR = (long) packet;
+ p_mac->EMAC_TCR = length;
+ while (p_mac->EMAC_TCR & 0x7ff);
+ p_mac->EMAC_TSR |= AT91C_EMAC_COMP;
+ return 0;
+}
+
+int eth_rx (void)
+{
+ int size;
+
+ if (!(rbfp->addr & RBF_OWNER))
+ return 0;
+
+ size = rbfp->size & RBF_SIZE;
+ NetReceive ((volatile uchar *) (rbfp->addr & RBF_ADDR), size);
+
+ rbfp->addr &= ~RBF_OWNER;
+ if (rbfp->addr & RBF_WRAP)
+ rbfp = &rbfdt[0];
+ else
+ rbfp++;
+
+ p_mac->EMAC_RSR |= AT91C_EMAC_REC;
+
+ return size;
+}
+
+void eth_halt (void)
+{
+};
+
+#if (CONFIG_COMMANDS & CFG_CMD_MII)
+int miiphy_read(unsigned char addr, unsigned char reg, unsigned short * value)
+{
+ at91rm9200_EmacEnableMDIO (p_mac);
+ at91rm9200_EmacReadPhy (p_mac, reg, value);
+ at91rm9200_EmacDisableMDIO (p_mac);
+ return 0;
+}
+
+int miiphy_write(unsigned char addr, unsigned char reg, unsigned short value)
+{
+ at91rm9200_EmacEnableMDIO (p_mac);
+ at91rm9200_EmacWritePhy (p_mac, reg, &value);
+ at91rm9200_EmacDisableMDIO (p_mac);
+ return 0;
+}
+#endif /* CONFIG_COMMANDS & CFG_CMD_MII */
+
+#endif /* CONFIG_COMMANDS & CFG_CMD_NET */
+
+#endif /* CONFIG_DRIVER_ETHER */
--- /dev/null
+/*
+ * i2c Support for Atmel's AT91RM9200 Two-Wire Interface
+ *
+ * (c) Rick Bronson
+ *
+ * Borrowed heavily from original work by:
+ * Copyright (c) 2000 Philip Edelbrock <phil@stimpy.netroedge.com>
+ *
+ * Modified to work with u-boot by (C) 2004 Gary Jennejohn garyj@denx.de
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+*/
+#include <common.h>
+
+#ifdef CONFIG_HARD_I2C
+
+#include <i2c.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+
+#include <at91rm9200_i2c.h>
+
+/* define DEBUG */
+
+/*
+ * Poll the i2c status register until the specified bit is set.
+ * Returns 0 if timed out (100 msec)
+ */
+static short at91_poll_status(AT91PS_TWI twi, unsigned long bit) {
+ int loop_cntr = 10000;
+ do {
+ udelay(10);
+ } while (!(twi->TWI_SR & bit) && (--loop_cntr > 0));
+
+ return (loop_cntr > 0);
+}
+
+/*
+ * Generic i2c master transfer entrypoint
+ *
+ * rw == 1 means that this is a read
+ */
+static int
+at91_xfer(unsigned char chip, unsigned int addr, int alen,
+ unsigned char *buffer, int len, int rw)
+{
+ AT91PS_TWI twi = (AT91PS_TWI) AT91_TWI_BASE;
+ int length;
+ unsigned char *buf;
+ /* Set the TWI Master Mode Register */
+ twi->TWI_MMR = (chip << 16) | (alen << 8)
+ | ((rw == 1) ? AT91C_TWI_MREAD : 0);
+
+ /* Set TWI Internal Address Register with first messages data field */
+ /* only one address byte is supported */
+ if (alen > 0)
+ twi->TWI_IADR = addr & 0xff;
+
+ length = len;
+ buf = buffer;
+ if (length && buf) { /* sanity check */
+ if (rw) {
+ twi->TWI_CR = AT91C_TWI_START;
+ while (length--) {
+ if (!length)
+ twi->TWI_CR = AT91C_TWI_STOP;
+ /* Wait until transfer is finished */
+ if (!at91_poll_status(twi, AT91C_TWI_RXRDY)) {
+ debug ("at91_i2c: timeout 1\n");
+ return 1;
+ }
+ *buf++ = twi->TWI_RHR;
+ }
+ if (!at91_poll_status(twi, AT91C_TWI_TXCOMP)) {
+ debug ("at91_i2c: timeout 2\n");
+ return 1;
+ }
+ } else {
+ twi->TWI_CR = AT91C_TWI_START;
+ while (length--) {
+ twi->TWI_THR = *buf++;
+ if (!length)
+ twi->TWI_CR = AT91C_TWI_STOP;
+ if (!at91_poll_status(twi, AT91C_TWI_TXRDY)) {
+ debug ("at91_i2c: timeout 3\n");
+ return 1;
+ }
+ }
+ /* Wait until transfer is finished */
+ if (!at91_poll_status(twi, AT91C_TWI_TXCOMP)) {
+ debug ("at91_i2c: timeout 4\n");
+ return 1;
+ }
+ }
+ }
+ return 0;
+}
+
+int
+i2c_probe(unsigned char chip)
+{
+ char buffer[1];
+
+ return at91_xfer(chip, 0, 0, buffer, 1, 1);
+}
+
+int
+i2c_read (unsigned char chip, unsigned int addr, int alen,
+ unsigned char *buffer, int len)
+{
+#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
+ /* we only allow one address byte */
+ if (alen > 1)
+ return 1;
+ /* XXX assume an ATMEL AT24C16 */
+ if (alen == 1) {
+#if 0 /* EEPROM code already sets this correctly */
+ chip |= (addr >> 8) & 0xff;
+#endif
+ addr = addr & 0xff;
+ }
+#endif
+ return at91_xfer(chip, addr, alen, buffer, len, 1);
+}
+
+int
+i2c_write(unsigned char chip, unsigned int addr, int alen,
+ unsigned char *buffer, int len)
+{
+ int i;
+ unsigned char *buf;
+
+#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
+ /* we only allow one address byte */
+ if (alen > 1)
+ return 1;
+ /* XXX assume an ATMEL AT24C16 */
+ if (alen == 1) {
+ buf = buffer;
+ /* do single byte writes */
+ for (i = 0; i < len; i++) {
+#if 0 /* EEPROM code already sets this correctly */
+ chip |= (addr >> 8) & 0xff;
+#endif
+ addr = addr & 0xff;
+ if (at91_xfer(chip, addr, alen, buf++, 1, 0))
+ return 1;
+ addr++;
+ }
+ return 0;
+ }
+#endif
+ return at91_xfer(chip, addr, alen, buffer, len, 0);
+}
+
+/*
+ * Main initialization routine
+ */
+void
+i2c_init(int speed, int slaveaddr)
+{
+ AT91PS_TWI twi = (AT91PS_TWI) AT91_TWI_BASE;
+
+ *AT91C_PIOA_PDR = AT91C_PA25_TWD | AT91C_PA26_TWCK;
+ *AT91C_PIOA_ASR = AT91C_PA25_TWD | AT91C_PA26_TWCK;
+ *AT91C_PIOA_MDER = AT91C_PA25_TWD | AT91C_PA26_TWCK;
+ *AT91C_PMC_PCER = 1 << AT91C_ID_TWI; /* enable peripheral clock */
+
+ twi->TWI_IDR = 0x3ff; /* Disable all interrupts */
+ twi->TWI_CR = AT91C_TWI_SWRST; /* Reset peripheral */
+ twi->TWI_CR = AT91C_TWI_MSEN | AT91C_TWI_SVDIS; /* Set Master mode */
+
+ /* Here, CKDIV = 1 and CHDIV=CLDIV ==> CLDIV = CHDIV = 1/4*((Fmclk/FTWI) -6) */
+ twi->TWI_CWGR = AT91C_TWI_CKDIV1 | AT91C_TWI_CLDIV3 | (AT91C_TWI_CLDIV3 << 8);
+
+ debug ("Found AT91 i2c\n");
+ return;
+}
+#endif /* CONFIG_HARD_I2C */
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Lineo, Inc. <www.lineo.com>
+ * Bernhard Kuhn <bkuhn@lineo.com>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+/*#include <asm/io.h>*/
+#include <asm/arch/hardware.h>
+/*#include <asm/proc/ptrace.h>*/
+
+/* the number of clocks per CFG_HZ */
+#define TIMER_LOAD_VAL (CFG_HZ_CLOCK/CFG_HZ)
+
+/* macro to read the 16 bit timer */
+#define READ_TIMER (tmr->TC_CV & 0x0000ffff)
+AT91PS_TC tmr;
+
+static ulong timestamp;
+static ulong lastinc;
+
+int interrupt_init (void)
+{
+ tmr = AT91C_BASE_TC0;
+
+ /* enables TC1.0 clock */
+ *AT91C_PMC_PCER = 1 << AT91C_ID_TC0; /* enable clock */
+
+ *AT91C_TCB0_BCR = 0;
+ *AT91C_TCB0_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_NONE | AT91C_TCB_TC2XC2S_NONE;
+ tmr->TC_CCR = AT91C_TC_CLKDIS;
+#define AT91C_TC_CMR_CPCTRG (1 << 14)
+ /* set to MCLK/2 and restart the timer when the vlaue in TC_RC is reached */
+ tmr->TC_CMR = AT91C_TC_TIMER_DIV1_CLOCK | AT91C_TC_CMR_CPCTRG;
+
+ tmr->TC_IDR = ~0ul;
+ tmr->TC_RC = TIMER_LOAD_VAL;
+ lastinc = 0;
+ tmr->TC_CCR = AT91C_TC_SWTRG | AT91C_TC_CLKEN;
+ timestamp = 0;
+
+ return (0);
+}
+
+/*
+ * timer without interrupts
+ */
+
+void reset_timer (void)
+{
+ reset_timer_masked ();
+}
+
+ulong get_timer (ulong base)
+{
+ return get_timer_masked () - base;
+}
+
+void set_timer (ulong t)
+{
+ timestamp = t;
+}
+
+void udelay (unsigned long usec)
+{
+ udelay_masked(usec);
+}
+
+void reset_timer_masked (void)
+{
+ /* reset time */
+ lastinc = READ_TIMER;
+ timestamp = 0;
+}
+
+ulong get_timer_raw (void)
+{
+ ulong now = READ_TIMER;
+
+ if (now >= lastinc) {
+ /* normal mode */
+ timestamp += now - lastinc;
+ } else {
+ /* we have an overflow ... */
+ timestamp += now + TIMER_LOAD_VAL - lastinc;
+ }
+ lastinc = now;
+
+ return timestamp;
+}
+
+ulong get_timer_masked (void)
+{
+ return get_timer_raw()/TIMER_LOAD_VAL;
+}
+
+void udelay_masked (unsigned long usec)
+{
+ ulong tmo;
+ ulong endtime;
+ signed long diff;
+
+ tmo = CFG_HZ_CLOCK / 1000;
+ tmo *= usec;
+ tmo /= 1000;
+
+ endtime = get_timer_raw () + tmo;
+
+ do {
+ ulong now = get_timer_raw ();
+ diff = endtime - now;
+ } while (diff >= 0);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+ return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk (void)
+{
+ ulong tbclk;
+
+ tbclk = CFG_HZ;
+ return tbclk;
+}
+
+/*
+ * Reset the cpu by setting up the watchdog timer and let him time out
+ * or toggle a GPIO pin on the AT91RM9200DK board
+ */
+void reset_cpu (ulong ignored)
+{
+
+#ifdef CONFIG_DBGU
+ AT91PS_USART us = (AT91PS_USART) AT91C_BASE_DBGU;
+#endif
+#ifdef CONFIG_USART0
+ AT91PS_USART us = AT91C_BASE_US0;
+#endif
+#ifdef CONFIG_USART1
+ AT91PS_USART us = AT91C_BASE_US1;
+#endif
+#ifdef CONFIG_AT91RM9200DK
+ AT91PS_PIO pio = AT91C_BASE_PIOA;
+#endif
+
+ /*shutdown the console to avoid strange chars during reset */
+ us->US_CR = (AT91C_US_RSTRX | AT91C_US_RSTTX);
+
+#ifdef CONFIG_AT91RM9200DK
+ /* Clear PA19 to trigger the hard reset */
+ pio->PIO_CODR = 0x00080000;
+ pio->PIO_OER = 0x00080000;
+ pio->PIO_PER = 0x00080000;
+#endif
+
+ /* this is the way Linux does it */
+
+ /* FIXME:
+ * These defines should be moved into
+ * include/asm-arm/arch-at91rm9200/AT91RM9200.h
+ * as soon as the whitespace fix gets applied.
+ */
+ #define AT91C_ST_RSTEN (0x1 << 16)
+ #define AT91C_ST_EXTEN (0x1 << 17)
+ #define AT91C_ST_WDRST (0x1 << 0)
+ #define ST_WDMR *((unsigned long *)0xfffffd08) /* watchdog mode register */
+ #define ST_CR *((unsigned long *)0xfffffd00) /* system clock control register */
+
+ ST_WDMR = AT91C_ST_RSTEN | AT91C_ST_EXTEN | 1 ;
+ ST_CR = AT91C_ST_WDRST;
+
+ while (1);
+ /* Never reached */
+}
--- /dev/null
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ *
+ * Modified for the at91rm9200dk board by
+ * (C) Copyright 2004
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+/*
+ * some parameters for the board
+ *
+ * This is based on rm9200dk.cfg for the BDI2000 from ABATRON which in
+ * turn is based on the boot.bin code from ATMEL
+ *
+ */
+
+/* flash */
+#define MC_PUIA 0xFFFFFF10
+#define MC_PUP 0xFFFFFF50
+#define MC_PUER 0xFFFFFF54
+#define MC_ASR 0xFFFFFF04
+#define MC_AASR 0xFFFFFF08
+#define EBI_CFGR 0xFFFFFF64
+#define SMC2_CSR 0xFFFFFF70
+
+/* clocks */
+#define PLLAR 0xFFFFFC28
+#define PLLBR 0xFFFFFC2C
+#define MCKR 0xFFFFFC30
+
+#define AT91C_BASE_CKGR 0xFFFFFC20
+#define CKGR_MOR 0
+
+/* sdram */
+#define PIOC_ASR 0xFFFFF870
+#define PIOC_BSR 0xFFFFF874
+#define PIOC_PDR 0xFFFFF804
+#define EBI_CSA 0xFFFFFF60
+#define SDRC_CR 0xFFFFFF98
+#define SDRC_MR 0xFFFFFF90
+#define SDRC_TR 0xFFFFFF94
+
+
+_MTEXT_BASE:
+#undef START_FROM_MEM
+#ifdef START_FROM_MEM
+ .word TEXT_BASE-PHYS_FLASH_1
+#else
+ .word TEXT_BASE
+#endif
+
+.globl lowlevel_init
+lowlevel_init:
+ /* Get the CKGR Base Address */
+ ldr r1, =AT91C_BASE_CKGR
+ /* Main oscillator Enable register */
+#ifdef CFG_USE_MAIN_OSCILLATOR
+ ldr r0, =0x0000FF01 /* Enable main oscillator, OSCOUNT = 0xFF */
+#else
+ ldr r0, =0x0000FF00 /* Disable main oscillator, OSCOUNT = 0xFF */
+#endif
+ str r0, [r1, #CKGR_MOR]
+ /* Add loop to compensate Main Oscillator startup time */
+ ldr r0, =0x00000010
+LoopOsc:
+ subs r0, r0, #1
+ bhi LoopOsc
+
+ /* memory control configuration */
+ /* this isn't very elegant, but what the heck */
+ ldr r0, =SMRDATA
+ ldr r1, _MTEXT_BASE
+ sub r0, r0, r1
+ add r2, r0, #80
+0:
+ /* the address */
+ ldr r1, [r0], #4
+ /* the value */
+ ldr r3, [r0], #4
+ str r3, [r1]
+ cmp r2, r0
+ bne 0b
+ /* delay - this is all done by guess */
+ ldr r0, =0x00010000
+1:
+ subs r0, r0, #1
+ bhi 1b
+ ldr r0, =SMRDATA1
+ ldr r1, _MTEXT_BASE
+ sub r0, r0, r1
+ add r2, r0, #176
+2:
+ /* the address */
+ ldr r1, [r0], #4
+ /* the value */
+ ldr r3, [r0], #4
+ str r3, [r1]
+ cmp r2, r0
+ bne 2b
+
+ /* everything is fine now */
+ mov pc, lr
+
+ .ltorg
+
+SMRDATA:
+ .word MC_PUIA
+ .word MC_PUIA_VAL
+ .word MC_PUP
+ .word MC_PUP_VAL
+ .word MC_PUER
+ .word MC_PUER_VAL
+ .word MC_ASR
+ .word MC_ASR_VAL
+ .word MC_AASR
+ .word MC_AASR_VAL
+ .word EBI_CFGR
+ .word EBI_CFGR_VAL
+ .word SMC2_CSR
+ .word SMC2_CSR_VAL
+ .word PLLAR
+ .word PLLAR_VAL
+ .word PLLBR
+ .word PLLBR_VAL
+ .word MCKR
+ .word MCKR_VAL
+ /* SMRDATA is 80 bytes long */
+ /* here there's a delay of 100 */
+SMRDATA1:
+ .word PIOC_ASR
+ .word PIOC_ASR_VAL
+ .word PIOC_BSR
+ .word PIOC_BSR_VAL
+ .word PIOC_PDR
+ .word PIOC_PDR_VAL
+ .word EBI_CSA
+ .word EBI_CSA_VAL
+ .word SDRC_CR
+ .word SDRC_CR_VAL
+ .word SDRC_MR
+ .word SDRC_MR_VAL
+ .word SDRAM
+ .word SDRAM_VAL
+ .word SDRC_MR
+ .word SDRC_MR_VAL1
+ .word SDRAM
+ .word SDRAM_VAL
+ .word SDRAM
+ .word SDRAM_VAL
+ .word SDRAM
+ .word SDRAM_VAL
+ .word SDRAM
+ .word SDRAM_VAL
+ .word SDRAM
+ .word SDRAM_VAL
+ .word SDRAM
+ .word SDRAM_VAL
+ .word SDRAM
+ .word SDRAM_VAL
+ .word SDRAM
+ .word SDRAM_VAL
+ .word SDRC_MR
+ .word SDRC_MR_VAL2
+ .word SDRAM1
+ .word SDRAM_VAL
+ .word SDRC_TR
+ .word SDRC_TR_VAL
+ .word SDRAM
+ .word SDRAM_VAL
+ .word SDRC_MR
+ .word SDRC_MR_VAL3
+ .word SDRAM
+ .word SDRAM_VAL
+ /* SMRDATA1 is 176 bytes long */
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Lineo, Inc <www.lineo.com>
+ * Bernhard Kuhn <bkuhn@lineo.com>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+
+#if !defined(CONFIG_DBGU) && !defined(CONFIG_USART0) && !defined(CONFIG_USART1)
+#error must define one of CONFIG_DBGU or CONFIG_USART0 or CONFIG_USART1
+#endif
+
+/* ggi thunder */
+#ifdef CONFIG_DBGU
+AT91PS_USART us = (AT91PS_USART) AT91C_BASE_DBGU;
+#endif
+#ifdef CONFIG_USART0
+AT91PS_USART us = (AT91PS_USART) AT91C_BASE_US0;
+#endif
+#ifdef CONFIG_USART1
+AT91PS_USART us = (AT91PS_USART) AT91C_BASE_US1;
+#endif
+
+void serial_setbrg (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ int baudrate;
+
+ if ((baudrate = gd->baudrate) <= 0)
+ baudrate = CONFIG_BAUDRATE;
+ if (baudrate == 0 || baudrate == CONFIG_BAUDRATE)
+ us->US_BRGR = CFG_AT91C_BRGR_DIVISOR; /* hardcode so no __divsi3 */
+ else
+ /* MASTER_CLOCK/(16 * baudrate) */
+ us->US_BRGR = (AT91C_MASTER_CLOCK >> 4)/baudrate;
+}
+
+int serial_init (void)
+{
+ /* make any port initializations specific to this port */
+#ifdef CONFIG_DBGU
+ *AT91C_PIOA_PDR = AT91C_PA31_DTXD | AT91C_PA30_DRXD; /* PA 31 & 30 */
+ *AT91C_PMC_PCER = 1 << AT91C_ID_SYS; /* enable clock */
+#endif
+#ifdef CONFIG_USART0
+ *AT91C_PIOA_PDR = AT91C_PA17_TXD0 | AT91C_PA18_RXD0;
+ *AT91C_PMC_PCER |= 1 << AT91C_ID_USART0; /* enable clock */
+#endif
+#ifdef CONFIG_USART1
+ *AT91C_PIOB_PDR = AT91C_PB21_TXD1 | AT91C_PB20_RXD1;
+ *AT91C_PMC_PCER |= 1 << AT91C_ID_USART1; /* enable clock */
+#endif
+ serial_setbrg ();
+
+ us->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX;
+ us->US_CR = AT91C_US_RXEN | AT91C_US_TXEN;
+ us->US_MR =
+ (AT91C_US_CLKS_CLOCK | AT91C_US_CHRL_8_BITS |
+ AT91C_US_PAR_NONE | AT91C_US_NBSTOP_1_BIT);
+ us->US_IMR = ~0ul;
+ return (0);
+}
+
+void serial_putc (const char c)
+{
+ if (c == '\n')
+ serial_putc ('\r');
+ while ((us->US_CSR & AT91C_US_TXRDY) == 0);
+ us->US_THR = c;
+}
+
+void serial_puts (const char *s)
+{
+ while (*s) {
+ serial_putc (*s++);
+ }
+}
+
+int serial_getc (void)
+{
+ while ((us->US_CSR & AT91C_US_RXRDY) == 0);
+ return us->US_RHR;
+}
+
+int serial_tstc (void)
+{
+ return ((us->US_CSR & AT91C_US_RXRDY) == AT91C_US_RXRDY);
+}
+++ /dev/null
-#
-# (C) Copyright 2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = lib$(CPU).a
-
-START = start.o
-OBJS = serial.o interrupts.o cpu.o \
- at91rm9200_ether.o i2c.o
-SOBJS = lowlevel.o
-
-all: .depend $(START) $(LIB)
-
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
-
-#########################################################################
-
-.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
-
-sinclude .depend
-
-#########################################################################
+++ /dev/null
-/*
- * (C) Copyright 2003
- * Author : Hamid Ikdoumi (Atmel)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <at91rm9200_net.h>
-#include <net.h>
-
-/* ----- Ethernet Buffer definitions ----- */
-
-typedef struct {
- unsigned long addr, size;
-} rbf_t;
-
-#define RBF_ADDR 0xfffffffc
-#define RBF_OWNER (1<<0)
-#define RBF_WRAP (1<<1)
-#define RBF_BROADCAST (1<<31)
-#define RBF_MULTICAST (1<<30)
-#define RBF_UNICAST (1<<29)
-#define RBF_EXTERNAL (1<<28)
-#define RBF_UNKOWN (1<<27)
-#define RBF_SIZE 0x07ff
-#define RBF_LOCAL4 (1<<26)
-#define RBF_LOCAL3 (1<<25)
-#define RBF_LOCAL2 (1<<24)
-#define RBF_LOCAL1 (1<<23)
-
-/* Emac Buffers in last 512KBytes of SDRAM*/
-/* Be careful, buffer size is limited to 512KBytes !!! */
-#define RBF_FRAMEMAX 100
-/*#define RBF_FRAMEMEM 0x200000 */
-#define RBF_FRAMEMEM 0x21F80000
-#define RBF_FRAMELEN 0x600
-
-#define RBF_FRAMEBTD RBF_FRAMEMEM
-#define RBF_FRAMEBUF (RBF_FRAMEMEM + RBF_FRAMEMAX*sizeof(rbf_t))
-
-
-#ifdef CONFIG_DRIVER_ETHER
-
-#if (CONFIG_COMMANDS & CFG_CMD_NET)
-
-/* structure to interface the PHY */
-AT91S_PhyOps PhyOps;
-
-AT91PS_EMAC p_mac;
-
-/*********** EMAC Phy layer Management functions *************************/
-/*
- * Name:
- * at91rm9200_EmacEnableMDIO
- * Description:
- * Enables the MDIO bit in MAC control register
- * Arguments:
- * p_mac - pointer to struct AT91S_EMAC
- * Return value:
- * none
- */
-void at91rm9200_EmacEnableMDIO (AT91PS_EMAC p_mac)
-{
- /* Mac CTRL reg set for MDIO enable */
- p_mac->EMAC_CTL |= AT91C_EMAC_MPE; /* Management port enable */
-}
-
-/*
- * Name:
- * at91rm9200_EmacDisableMDIO
- * Description:
- * Disables the MDIO bit in MAC control register
- * Arguments:
- * p_mac - pointer to struct AT91S_EMAC
- * Return value:
- * none
- */
-void at91rm9200_EmacDisableMDIO (AT91PS_EMAC p_mac)
-{
- /* Mac CTRL reg set for MDIO disable */
- p_mac->EMAC_CTL &= ~AT91C_EMAC_MPE; /* Management port disable */
-}
-
-
-/*
- * Name:
- * at91rm9200_EmacReadPhy
- * Description:
- * Reads data from the PHY register
- * Arguments:
- * dev - pointer to struct net_device
- * RegisterAddress - unsigned char
- * pInput - pointer to value read from register
- * Return value:
- * TRUE - if data read successfully
- */
-UCHAR at91rm9200_EmacReadPhy (AT91PS_EMAC p_mac,
- unsigned char RegisterAddress,
- unsigned short *pInput)
-{
- p_mac->EMAC_MAN = (AT91C_EMAC_HIGH & ~AT91C_EMAC_LOW) |
- (AT91C_EMAC_RW_R) |
- (RegisterAddress << 18) |
- (AT91C_EMAC_CODE_802_3);
-
- udelay (10000);
-
- *pInput = (unsigned short) p_mac->EMAC_MAN;
-
- return TRUE;
-}
-
-
-/*
- * Name:
- * at91rm9200_EmacWritePhy
- * Description:
- * Writes data to the PHY register
- * Arguments:
- * dev - pointer to struct net_device
- * RegisterAddress - unsigned char
- * pOutput - pointer to value to be written in the register
- * Return value:
- * TRUE - if data read successfully
- */
-UCHAR at91rm9200_EmacWritePhy (AT91PS_EMAC p_mac,
- unsigned char RegisterAddress,
- unsigned short *pOutput)
-{
- p_mac->EMAC_MAN = (AT91C_EMAC_HIGH & ~AT91C_EMAC_LOW) |
- AT91C_EMAC_CODE_802_3 | AT91C_EMAC_RW_W |
- (RegisterAddress << 18) | *pOutput;
-
- udelay (10000);
-
- return TRUE;
-}
-
-
-rbf_t *rbfdt;
-rbf_t *rbfp;
-
-int eth_init (bd_t * bd)
-{
- int ret;
- int i;
-
- p_mac = AT91C_BASE_EMAC;
-
- /* PIO Disable Register */
- *AT91C_PIOA_PDR = AT91C_PA16_EMDIO | AT91C_PA15_EMDC | AT91C_PA14_ERXER |
- AT91C_PA13_ERX1 | AT91C_PA12_ERX0 | AT91C_PA11_ECRS_ECRSDV |
- AT91C_PA10_ETX1 | AT91C_PA9_ETX0 | AT91C_PA8_ETXEN |
- AT91C_PA7_ETXCK_EREFCK;
-
-#ifdef CONFIG_AT91C_USE_RMII
- *AT91C_PIOB_PDR = AT91C_PB19_ERXCK;
- *AT91C_PIOB_BSR = AT91C_PB19_ERXCK;
-#else
- *AT91C_PIOB_PDR = AT91C_PB19_ERXCK | AT91C_PB18_ECOL | AT91C_PB17_ERXDV |
- AT91C_PB16_ERX3 | AT91C_PB15_ERX2 | AT91C_PB14_ETXER |
- AT91C_PB13_ETX3 | AT91C_PB12_ETX2;
-
- /* Select B Register */
- *AT91C_PIOB_BSR = AT91C_PB19_ERXCK | AT91C_PB18_ECOL |
- AT91C_PB17_ERXDV | AT91C_PB16_ERX3 | AT91C_PB15_ERX2 |
- AT91C_PB14_ETXER | AT91C_PB13_ETX3 | AT91C_PB12_ETX2;
-#endif
-
- *AT91C_PMC_PCER = 1 << AT91C_ID_EMAC; /* Peripheral Clock Enable Register */
-
- p_mac->EMAC_CFG |= AT91C_EMAC_CSR; /* Clear statistics */
-
- /* Init Ehternet buffers */
- rbfdt = (rbf_t *) RBF_FRAMEBTD;
- for (i = 0; i < RBF_FRAMEMAX; i++) {
- rbfdt[i].addr = RBF_FRAMEBUF + RBF_FRAMELEN * i;
- rbfdt[i].size = 0;
- }
- rbfdt[RBF_FRAMEMAX - 1].addr |= RBF_WRAP;
- rbfp = &rbfdt[0];
-
- p_mac->EMAC_SA2L = (bd->bi_enetaddr[3] << 24) | (bd->bi_enetaddr[2] << 16)
- | (bd->bi_enetaddr[1] << 8) | (bd->bi_enetaddr[0]);
- p_mac->EMAC_SA2H = (bd->bi_enetaddr[5] << 8) | (bd->bi_enetaddr[4]);
-
- p_mac->EMAC_RBQP = (long) (&rbfdt[0]);
- p_mac->EMAC_RSR &= ~(AT91C_EMAC_RSR_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA);
-
- p_mac->EMAC_CFG = (p_mac->EMAC_CFG | AT91C_EMAC_CAF | AT91C_EMAC_NBC)
- & ~AT91C_EMAC_CLK;
-
-#ifdef CONFIG_AT91C_USE_RMII
- p_mac->EMAC_CFG |= AT91C_EMAC_RMII;
-#endif
-
-#if (AT91C_MASTER_CLOCK > 40000000)
- /* MDIO clock must not exceed 2.5 MHz, so enable MCK divider */
- p_mac->EMAC_CFG |= AT91C_EMAC_CLK_HCLK_64;
-#endif
-
- p_mac->EMAC_CTL |= AT91C_EMAC_TE | AT91C_EMAC_RE;
-
- at91rm92000_GetPhyInterface (& PhyOps);
-
- if (!PhyOps.IsPhyConnected (p_mac))
- printf ("PHY not connected!!\n\r");
-
- /* MII management start from here */
- if (!(p_mac->EMAC_SR & AT91C_EMAC_LINK)) {
- if (!(ret = PhyOps.Init (p_mac))) {
- printf ("MAC: error during MII initialization\n");
- return 0;
- }
- } else {
- printf ("No link\n\r");
- return 0;
- }
-
- return 0;
-}
-
-int eth_send (volatile void *packet, int length)
-{
- while (!(p_mac->EMAC_TSR & AT91C_EMAC_BNQ));
- p_mac->EMAC_TAR = (long) packet;
- p_mac->EMAC_TCR = length;
- while (p_mac->EMAC_TCR & 0x7ff);
- p_mac->EMAC_TSR |= AT91C_EMAC_COMP;
- return 0;
-}
-
-int eth_rx (void)
-{
- int size;
-
- if (!(rbfp->addr & RBF_OWNER))
- return 0;
-
- size = rbfp->size & RBF_SIZE;
- NetReceive ((volatile uchar *) (rbfp->addr & RBF_ADDR), size);
-
- rbfp->addr &= ~RBF_OWNER;
- if (rbfp->addr & RBF_WRAP)
- rbfp = &rbfdt[0];
- else
- rbfp++;
-
- p_mac->EMAC_RSR |= AT91C_EMAC_REC;
-
- return size;
-}
-
-void eth_halt (void)
-{
-};
-
-#if (CONFIG_COMMANDS & CFG_CMD_MII)
-int miiphy_read(unsigned char addr, unsigned char reg, unsigned short * value)
-{
- at91rm9200_EmacEnableMDIO (p_mac);
- at91rm9200_EmacReadPhy (p_mac, reg, value);
- at91rm9200_EmacDisableMDIO (p_mac);
- return 0;
-}
-
-int miiphy_write(unsigned char addr, unsigned char reg, unsigned short value)
-{
- at91rm9200_EmacEnableMDIO (p_mac);
- at91rm9200_EmacWritePhy (p_mac, reg, &value);
- at91rm9200_EmacDisableMDIO (p_mac);
- return 0;
-}
-#endif /* CONFIG_COMMANDS & CFG_CMD_MII */
-
-#endif /* CONFIG_COMMANDS & CFG_CMD_NET */
-
-#endif /* CONFIG_DRIVER_ETHER */
+++ /dev/null
-#
-# (C) Copyright 2002
-# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
-# Marius Groeger <mgroeger@sysgo.de>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \
- -mshort-load-bytes -msoft-float
-
-PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4 -mtune=arm7tdmi
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * CPU specific code
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-
-#if !defined(CONFIG_DBGU) && !defined(CONFIG_USART0) && !defined(CONFIG_USART1)
-#error must define one of CONFIG_DBGU or CONFIG_USART0 or CONFIG_USART1
-#endif
-
-/* read co-processor 15, register #1 (control register) */
-static unsigned long read_p15_c1(void)
-{
- unsigned long value;
-
- __asm__ __volatile__(
- "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n"
- : "=r" (value)
- :
- : "memory");
- /*printf("p15/c1 is = %08lx\n", value); */
- return value;
-}
-
-/* write to co-processor 15, register #1 (control register) */
-static void write_p15_c1(unsigned long value)
-{
- /*printf("write %08lx to p15/c1\n", value); */
- __asm__ __volatile__(
- "mcr p15, 0, %0, c1, c0, 0 @ write it back\n"
- : "=r" (value)
- :
- : "memory");
-
- read_p15_c1();
-}
-
-static void cp_delay(void)
-{
- volatile int i;
-
- /* copro seems to need some delay between reading and writing */
- for (i=0; i<100; i++);
-}
-/* See also ARM Ref. Man. */
-#define C1_MMU (1<<0) /* mmu off/on */
-#define C1_ALIGN (1<<1) /* alignment faults off/on */
-#define C1_IDC (1<<2) /* icache and/or dcache off/on */
-#define C1_WRITE_BUFFER (1<<3) /* write buffer off/on */
-#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */
-#define C1_SYS_PROT (1<<8) /* system protection */
-#define C1_ROM_PROT (1<<9) /* ROM protection */
-#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */
-
-int cpu_init(void)
-{
- /*
- * setup up stacks if necessary
- */
-#ifdef CONFIG_USE_IRQ
- DECLARE_GLOBAL_DATA_PTR;
-
- IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
- FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
-#endif
- return 0;
-}
-
-int cleanup_before_linux(void)
-{
- /*
- * this function is called just before we call linux
- * it prepares the processor for linux
- *
- * we turn off caches etc ...
- * and we set the CPU-speed to 73 MHz - see start.S for details
- */
-
- disable_interrupts();
- return 0;
-}
-
-int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
-
-#ifdef CFG_SOFT_RESET
- disable_interrupts();
- reset_cpu(0);
-#else
-#ifdef CONFIG_DBGU
- AT91PS_USART us = (AT91PS_USART) AT91C_BASE_DBGU;
-#endif
-#ifdef CONFIG_USART0
- AT91PS_USART us = AT91C_BASE_US0;
-#endif
-#ifdef CONFIG_USART1
- AT91PS_USART us = AT91C_BASE_US1;
-#endif
- AT91PS_PIO pio = AT91C_BASE_PIOA;
-
- /*shutdown the console to avoid strange chars during reset */
- us->US_CR = (AT91C_US_RSTRX | AT91C_US_RSTTX);
-
-#ifdef CONFIG_AT91RM9200DK
- /* Clear PA19 to trigger the hard reset */
- pio->PIO_CODR = 0x00080000;
- pio->PIO_OER = 0x00080000;
- pio->PIO_PER = 0x00080000;
-#endif
-#ifdef CONFIG_CMC_PU2
-/* this is the way Linux does it */
-#define AT91C_ST_RSTEN (0x1 << 16)
-#define AT91C_ST_EXTEN (0x1 << 17)
-#define AT91C_ST_WDRST (0x1 << 0)
-/* watchdog mode register */
-#define ST_WDMR *((unsigned long *)0xfffffd08)
-/* system clock control register */
-#define ST_CR *((unsigned long *)0xfffffd00)
- ST_WDMR = AT91C_ST_RSTEN | AT91C_ST_EXTEN | 1 ;
- ST_CR = AT91C_ST_WDRST;
- /* Never reached */
-#endif
-#endif
- return 0;
-}
-
-void icache_enable(void)
-{
- ulong reg;
- reg = read_p15_c1();
- cp_delay();
- write_p15_c1(reg | C1_IDC);
-}
-
-void icache_disable(void)
-{
- ulong reg;
- reg = read_p15_c1();
- cp_delay();
- write_p15_c1(reg & ~C1_IDC);
-}
-
-int icache_status(void)
-{
- return (read_p15_c1() & C1_IDC) != 0;
- return 0;
-}
-
-void dcache_enable(void)
-{
- ulong reg;
- reg = read_p15_c1();
- cp_delay();
- write_p15_c1(reg | C1_IDC);
-}
-
-void dcache_disable(void)
-{
- ulong reg;
- reg = read_p15_c1();
- cp_delay();
- write_p15_c1(reg & ~C1_IDC);
-}
-
-int dcache_status(void)
-{
- return (read_p15_c1() & C1_IDC) != 0;
- return 0;
-}
+++ /dev/null
-/*
- * i2c Support for Atmel's AT91RM9200 Two-Wire Interface
- *
- * (c) Rick Bronson
- *
- * Borrowed heavily from original work by:
- * Copyright (c) 2000 Philip Edelbrock <phil@stimpy.netroedge.com>
- *
- * Modified to work with u-boot by (C) 2004 Gary Jennejohn garyj@denx.de
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
-*/
-#include <common.h>
-
-#ifdef CONFIG_HARD_I2C
-
-#include <i2c.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-
-#include <at91rm9200_i2c.h>
-
-/* define DEBUG */
-
-/*
- * Poll the i2c status register until the specified bit is set.
- * Returns 0 if timed out (100 msec)
- */
-static short at91_poll_status(AT91PS_TWI twi, unsigned long bit) {
- int loop_cntr = 10000;
- do {
- udelay(10);
- } while (!(twi->TWI_SR & bit) && (--loop_cntr > 0));
-
- return (loop_cntr > 0);
-}
-
-/*
- * Generic i2c master transfer entrypoint
- *
- * rw == 1 means that this is a read
- */
-static int
-at91_xfer(unsigned char chip, unsigned int addr, int alen,
- unsigned char *buffer, int len, int rw)
-{
- AT91PS_TWI twi = (AT91PS_TWI) AT91_TWI_BASE;
- int length;
- unsigned char *buf;
- /* Set the TWI Master Mode Register */
- twi->TWI_MMR = (chip << 16) | (alen << 8)
- | ((rw == 1) ? AT91C_TWI_MREAD : 0);
-
- /* Set TWI Internal Address Register with first messages data field */
- /* only one address byte is supported */
- if (alen > 0)
- twi->TWI_IADR = addr & 0xff;
-
- length = len;
- buf = buffer;
- if (length && buf) { /* sanity check */
- if (rw) {
- twi->TWI_CR = AT91C_TWI_START;
- while (length--) {
- if (!length)
- twi->TWI_CR = AT91C_TWI_STOP;
- /* Wait until transfer is finished */
- if (!at91_poll_status(twi, AT91C_TWI_RXRDY)) {
- debug ("at91_i2c: timeout 1\n");
- return 1;
- }
- *buf++ = twi->TWI_RHR;
- }
- if (!at91_poll_status(twi, AT91C_TWI_TXCOMP)) {
- debug ("at91_i2c: timeout 2\n");
- return 1;
- }
- } else {
- twi->TWI_CR = AT91C_TWI_START;
- while (length--) {
- twi->TWI_THR = *buf++;
- if (!length)
- twi->TWI_CR = AT91C_TWI_STOP;
- if (!at91_poll_status(twi, AT91C_TWI_TXRDY)) {
- debug ("at91_i2c: timeout 3\n");
- return 1;
- }
- }
- /* Wait until transfer is finished */
- if (!at91_poll_status(twi, AT91C_TWI_TXCOMP)) {
- debug ("at91_i2c: timeout 4\n");
- return 1;
- }
- }
- }
- return 0;
-}
-
-int
-i2c_probe(unsigned char chip)
-{
- char buffer[1];
-
- return at91_xfer(chip, 0, 0, buffer, 1, 1);
-}
-
-int
-i2c_read (unsigned char chip, unsigned int addr, int alen,
- unsigned char *buffer, int len)
-{
-#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
- /* we only allow one address byte */
- if (alen > 1)
- return 1;
- /* XXX assume an ATMEL AT24C16 */
- if (alen == 1) {
-#if 0 /* EEPROM code already sets this correctly */
- chip |= (addr >> 8) & 0xff;
-#endif
- addr = addr & 0xff;
- }
-#endif
- return at91_xfer(chip, addr, alen, buffer, len, 1);
-}
-
-int
-i2c_write(unsigned char chip, unsigned int addr, int alen,
- unsigned char *buffer, int len)
-{
- int i;
- unsigned char *buf;
-
-#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
- /* we only allow one address byte */
- if (alen > 1)
- return 1;
- /* XXX assume an ATMEL AT24C16 */
- if (alen == 1) {
- buf = buffer;
- /* do single byte writes */
- for (i = 0; i < len; i++) {
-#if 0 /* EEPROM code already sets this correctly */
- chip |= (addr >> 8) & 0xff;
-#endif
- addr = addr & 0xff;
- if (at91_xfer(chip, addr, alen, buf++, 1, 0))
- return 1;
- addr++;
- }
- return 0;
- }
-#endif
- return at91_xfer(chip, addr, alen, buffer, len, 0);
-}
-
-/*
- * Main initialization routine
- */
-void
-i2c_init(int speed, int slaveaddr)
-{
- AT91PS_TWI twi = (AT91PS_TWI) AT91_TWI_BASE;
-
- *AT91C_PIOA_PDR = AT91C_PA25_TWD | AT91C_PA26_TWCK;
- *AT91C_PIOA_ASR = AT91C_PA25_TWD | AT91C_PA26_TWCK;
- *AT91C_PIOA_MDER = AT91C_PA25_TWD | AT91C_PA26_TWCK;
- *AT91C_PMC_PCER = 1 << AT91C_ID_TWI; /* enable peripheral clock */
-
- twi->TWI_IDR = 0x3ff; /* Disable all interrupts */
- twi->TWI_CR = AT91C_TWI_SWRST; /* Reset peripheral */
- twi->TWI_CR = AT91C_TWI_MSEN | AT91C_TWI_SVDIS; /* Set Master mode */
-
- /* Here, CKDIV = 1 and CHDIV=CLDIV ==> CLDIV = CHDIV = 1/4*((Fmclk/FTWI) -6) */
- twi->TWI_CWGR = AT91C_TWI_CKDIV1 | AT91C_TWI_CLDIV3 | (AT91C_TWI_CLDIV3 << 8);
-
- debug ("Found AT91 i2c\n");
- return;
-}
-#endif /* CONFIG_HARD_I2C */
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Lineo, Inc. <www.lineo.com>
- * Bernhard Kuhn <bkuhn@lineo.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/proc/ptrace.h>
-
-/* the number of clocks per CFG_HZ */
-#define TIMER_LOAD_VAL (CFG_HZ_CLOCK/CFG_HZ)
-
-/* macro to read the 16 bit timer */
-#define READ_TIMER (tmr->TC_CV & 0x0000ffff)
-AT91PS_TC tmr;
-
-#ifdef CONFIG_USE_IRQ
-#error There is no IRQ support for AT91RM9200 in U-Boot yet.
-#else
-void enable_interrupts (void)
-{
- return;
-}
-int disable_interrupts (void)
-{
- return 0;
-}
-#endif
-
-
-void bad_mode (void)
-{
- panic ("Resetting CPU ...\n");
- reset_cpu (0);
-}
-
-void show_regs (struct pt_regs *regs)
-{
- unsigned long flags;
- const char *processor_modes[] = {
- "USER_26", "FIQ_26", "IRQ_26", "SVC_26",
- "UK4_26", "UK5_26", "UK6_26", "UK7_26",
- "UK8_26", "UK9_26", "UK10_26", "UK11_26",
- "UK12_26", "UK13_26", "UK14_26", "UK15_26",
- "USER_32", "FIQ_32", "IRQ_32", "SVC_32",
- "UK4_32", "UK5_32", "UK6_32", "ABT_32",
- "UK8_32", "UK9_32", "UK10_32", "UND_32",
- "UK12_32", "UK13_32", "UK14_32", "SYS_32",
- };
-
- flags = condition_codes (regs);
-
- printf ("pc : [<%08lx>] lr : [<%08lx>]\n"
- "sp : %08lx ip : %08lx fp : %08lx\n",
- instruction_pointer (regs),
- regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
- printf ("r10: %08lx r9 : %08lx r8 : %08lx\n",
- regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
- printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n",
- regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4);
- printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n",
- regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0);
- printf ("Flags: %c%c%c%c",
- flags & CC_N_BIT ? 'N' : 'n',
- flags & CC_Z_BIT ? 'Z' : 'z',
- flags & CC_C_BIT ? 'C' : 'c',
- flags & CC_V_BIT ? 'V' : 'v');
- printf (" IRQs %s FIQs %s Mode %s%s\n",
- interrupts_enabled (regs) ? "on" : "off",
- fast_interrupts_enabled (regs) ? "on" : "off",
- processor_modes[processor_mode (regs)],
- thumb_mode (regs) ? " (T)" : "");
-}
-
-void do_undefined_instruction (struct pt_regs *pt_regs)
-{
- printf ("undefined instruction\n");
- show_regs (pt_regs);
- bad_mode ();
-}
-
-void do_software_interrupt (struct pt_regs *pt_regs)
-{
- printf ("software interrupt\n");
- show_regs (pt_regs);
- bad_mode ();
-}
-
-void do_prefetch_abort (struct pt_regs *pt_regs)
-{
- printf ("prefetch abort\n");
- show_regs (pt_regs);
- bad_mode ();
-}
-
-void do_data_abort (struct pt_regs *pt_regs)
-{
- printf ("data abort\n");
- show_regs (pt_regs);
- bad_mode ();
-}
-
-void do_not_used (struct pt_regs *pt_regs)
-{
- printf ("not used\n");
- show_regs (pt_regs);
- bad_mode ();
-}
-
-void do_fiq (struct pt_regs *pt_regs)
-{
- printf ("fast interrupt request\n");
- show_regs (pt_regs);
- bad_mode ();
-}
-
-void do_irq (struct pt_regs *pt_regs)
-{
- printf ("interrupt request\n");
- show_regs (pt_regs);
- bad_mode ();
-}
-
-static ulong timestamp;
-static ulong lastinc;
-
-int interrupt_init (void)
-{
-
- tmr = AT91C_BASE_TC0;
-
- /* enables TC1.0 clock */
- *AT91C_PMC_PCER = 1 << AT91C_ID_TC0; /* enable clock */
-
- *AT91C_TCB0_BCR = 0;
- *AT91C_TCB0_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_NONE | AT91C_TCB_TC2XC2S_NONE;
- tmr->TC_CCR = AT91C_TC_CLKDIS;
-#define AT91C_TC_CMR_CPCTRG (1 << 14)
- /* set to MCLK/2 and restart the timer when the vlaue in TC_RC is reached */
- tmr->TC_CMR = AT91C_TC_TIMER_DIV1_CLOCK | AT91C_TC_CMR_CPCTRG;
-
- tmr->TC_IDR = ~0ul;
- tmr->TC_RC = TIMER_LOAD_VAL;
- lastinc = 0;
- tmr->TC_CCR = AT91C_TC_SWTRG | AT91C_TC_CLKEN;
- timestamp = 0;
-
- return (0);
-}
-
-/*
- * timer without interrupts
- */
-
-void reset_timer (void)
-{
- reset_timer_masked ();
-}
-
-ulong get_timer (ulong base)
-{
- return get_timer_masked () - base;
-}
-
-void set_timer (ulong t)
-{
- timestamp = t;
-}
-
-void udelay (unsigned long usec)
-{
- udelay_masked(usec);
-}
-
-void reset_timer_masked (void)
-{
- /* reset time */
- lastinc = READ_TIMER;
- timestamp = 0;
-}
-
-ulong get_timer_raw (void)
-{
- ulong now = READ_TIMER;
-
- if (now >= lastinc) {
- /* normal mode */
- timestamp += now - lastinc;
- } else {
- /* we have an overflow ... */
- timestamp += now + TIMER_LOAD_VAL - lastinc;
- }
- lastinc = now;
-
- return timestamp;
-}
-
-ulong get_timer_masked (void)
-{
- return get_timer_raw()/TIMER_LOAD_VAL;
-}
-
-void udelay_masked (unsigned long usec)
-{
- ulong tmo;
- ulong endtime;
- signed long diff;
-
- tmo = CFG_HZ_CLOCK / 1000;
- tmo *= usec;
- tmo /= 1000;
-
- endtime = get_timer_raw () + tmo;
-
- do {
- ulong now = get_timer_raw ();
- diff = endtime - now;
- } while (diff >= 0);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk (void)
-{
- ulong tbclk;
-
- tbclk = CFG_HZ;
- return tbclk;
-}
+++ /dev/null
-/*
- * Memory Setup stuff - taken from blob memsetup.S
- *
- * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
- * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
- *
- * Modified for the at91rm9200dk board by
- * (C) Copyright 2004
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-/*
- * some parameters for the board
- *
- * This is based on rm9200dk.cfg for the BDI2000 from ABATRON which in
- * turn is based on the boot.bin code from ATMEL
- *
- */
-
-/* flash */
-#define MC_PUIA 0xFFFFFF10
-#define MC_PUP 0xFFFFFF50
-#define MC_PUER 0xFFFFFF54
-#define MC_ASR 0xFFFFFF04
-#define MC_AASR 0xFFFFFF08
-#define EBI_CFGR 0xFFFFFF64
-#define SMC2_CSR 0xFFFFFF70
-
-/* clocks */
-#define PLLAR 0xFFFFFC28
-#define PLLBR 0xFFFFFC2C
-#define MCKR 0xFFFFFC30
-
-#define AT91C_BASE_CKGR 0xFFFFFC20
-#define CKGR_MOR 0
-
-/* sdram */
-#define PIOC_ASR 0xFFFFF870
-#define PIOC_BSR 0xFFFFF874
-#define PIOC_PDR 0xFFFFF804
-#define EBI_CSA 0xFFFFFF60
-#define SDRC_CR 0xFFFFFF98
-#define SDRC_MR 0xFFFFFF90
-#define SDRC_TR 0xFFFFFF94
-
-
-_MTEXT_BASE:
-#undef START_FROM_MEM
-#ifdef START_FROM_MEM
- .word TEXT_BASE-PHYS_FLASH_1
-#else
- .word TEXT_BASE
-#endif
-
-.globl lowlevel_init
-lowlevel_init:
- /* Get the CKGR Base Address */
- ldr r1, =AT91C_BASE_CKGR
- /* Main oscillator Enable register */
-#ifdef CFG_USE_MAIN_OSCILLATOR
- ldr r0, =0x0000FF01 /* Enable main oscillator, OSCOUNT = 0xFF */
-#else
- ldr r0, =0x0000FF00 /* Disable main oscillator, OSCOUNT = 0xFF */
-#endif
- str r0, [r1, #CKGR_MOR]
- /* Add loop to compensate Main Oscillator startup time */
- ldr r0, =0x00000010
-LoopOsc:
- subs r0, r0, #1
- bhi LoopOsc
-
- /* memory control configuration */
- /* this isn't very elegant, but what the heck */
- ldr r0, =SMRDATA
- ldr r1, _MTEXT_BASE
- sub r0, r0, r1
- add r2, r0, #80
-0:
- /* the address */
- ldr r1, [r0], #4
- /* the value */
- ldr r3, [r0], #4
- str r3, [r1]
- cmp r2, r0
- bne 0b
- /* delay - this is all done by guess */
- ldr r0, =0x00010000
-1:
- subs r0, r0, #1
- bhi 1b
- ldr r0, =SMRDATA1
- ldr r1, _MTEXT_BASE
- sub r0, r0, r1
- add r2, r0, #176
-2:
- /* the address */
- ldr r1, [r0], #4
- /* the value */
- ldr r3, [r0], #4
- str r3, [r1]
- cmp r2, r0
- bne 2b
-
- /* everything is fine now */
- mov pc, lr
-
- .ltorg
-
-SMRDATA:
- .word MC_PUIA
- .word MC_PUIA_VAL
- .word MC_PUP
- .word MC_PUP_VAL
- .word MC_PUER
- .word MC_PUER_VAL
- .word MC_ASR
- .word MC_ASR_VAL
- .word MC_AASR
- .word MC_AASR_VAL
- .word EBI_CFGR
- .word EBI_CFGR_VAL
- .word SMC2_CSR
- .word SMC2_CSR_VAL
- .word PLLAR
- .word PLLAR_VAL
- .word PLLBR
- .word PLLBR_VAL
- .word MCKR
- .word MCKR_VAL
- /* SMRDATA is 80 bytes long */
- /* here there's a delay of 100 */
-SMRDATA1:
- .word PIOC_ASR
- .word PIOC_ASR_VAL
- .word PIOC_BSR
- .word PIOC_BSR_VAL
- .word PIOC_PDR
- .word PIOC_PDR_VAL
- .word EBI_CSA
- .word EBI_CSA_VAL
- .word SDRC_CR
- .word SDRC_CR_VAL
- .word SDRC_MR
- .word SDRC_MR_VAL
- .word SDRAM
- .word SDRAM_VAL
- .word SDRC_MR
- .word SDRC_MR_VAL1
- .word SDRAM
- .word SDRAM_VAL
- .word SDRAM
- .word SDRAM_VAL
- .word SDRAM
- .word SDRAM_VAL
- .word SDRAM
- .word SDRAM_VAL
- .word SDRAM
- .word SDRAM_VAL
- .word SDRAM
- .word SDRAM_VAL
- .word SDRAM
- .word SDRAM_VAL
- .word SDRAM
- .word SDRAM_VAL
- .word SDRC_MR
- .word SDRC_MR_VAL2
- .word SDRAM1
- .word SDRAM_VAL
- .word SDRC_TR
- .word SDRC_TR_VAL
- .word SDRAM
- .word SDRAM_VAL
- .word SDRC_MR
- .word SDRC_MR_VAL3
- .word SDRAM
- .word SDRAM_VAL
- /* SMRDATA1 is 176 bytes long */
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Lineo, Inc <www.lineo.com>
- * Bernhard Kuhn <bkuhn@lineo.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-
-#if !defined(CONFIG_DBGU) && !defined(CONFIG_USART0) && !defined(CONFIG_USART1)
-#error must define one of CONFIG_DBGU or CONFIG_USART0 or CONFIG_USART1
-#endif
-
-/* ggi thunder */
-#ifdef CONFIG_DBGU
-AT91PS_USART us = (AT91PS_USART) AT91C_BASE_DBGU;
-#endif
-#ifdef CONFIG_USART0
-AT91PS_USART us = (AT91PS_USART) AT91C_BASE_US0;
-#endif
-#ifdef CONFIG_USART1
-AT91PS_USART us = (AT91PS_USART) AT91C_BASE_US1;
-#endif
-
-void serial_setbrg (void)
-{
- DECLARE_GLOBAL_DATA_PTR;
- int baudrate;
-
- if ((baudrate = gd->baudrate) <= 0)
- baudrate = CONFIG_BAUDRATE;
- if (baudrate == 0 || baudrate == CONFIG_BAUDRATE)
- us->US_BRGR = CFG_AT91C_BRGR_DIVISOR; /* hardcode so no __divsi3 */
- else
- /* MASTER_CLOCK/(16 * baudrate) */
- us->US_BRGR = (AT91C_MASTER_CLOCK >> 4)/baudrate;
-}
-
-int serial_init (void)
-{
- /* make any port initializations specific to this port */
-#ifdef CONFIG_DBGU
- *AT91C_PIOA_PDR = AT91C_PA31_DTXD | AT91C_PA30_DRXD; /* PA 31 & 30 */
- *AT91C_PMC_PCER = 1 << AT91C_ID_SYS; /* enable clock */
-#endif
-#ifdef CONFIG_USART0
- *AT91C_PIOA_PDR = AT91C_PA17_TXD0 | AT91C_PA18_RXD0;
- *AT91C_PMC_PCER |= 1 << AT91C_ID_USART0; /* enable clock */
-#endif
-#ifdef CONFIG_USART1
- *AT91C_PIOB_PDR = AT91C_PB21_TXD1 | AT91C_PB20_RXD1;
- *AT91C_PMC_PCER |= 1 << AT91C_ID_USART1; /* enable clock */
-#endif
- serial_setbrg ();
-
- us->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX;
- us->US_CR = AT91C_US_RXEN | AT91C_US_TXEN;
- us->US_MR =
- (AT91C_US_CLKS_CLOCK | AT91C_US_CHRL_8_BITS |
- AT91C_US_PAR_NONE | AT91C_US_NBSTOP_1_BIT);
- us->US_IMR = ~0ul;
- return (0);
-}
-
-void serial_putc (const char c)
-{
- if (c == '\n')
- serial_putc ('\r');
- while ((us->US_CSR & AT91C_US_TXRDY) == 0);
- us->US_THR = c;
-}
-
-void serial_puts (const char *s)
-{
- while (*s) {
- serial_putc (*s++);
- }
-}
-
-int serial_getc (void)
-{
- while ((us->US_CSR & AT91C_US_RXRDY) == 0);
- return us->US_RHR;
-}
-
-int serial_tstc (void)
-{
- return ((us->US_CSR & AT91C_US_RXRDY) == AT91C_US_RXRDY);
-}
+++ /dev/null
-/*
- * armboot - Startup Code for ARM720 CPU-core
- *
- * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
- * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#include "config.h"
-#include "version.h"
-
-
-/*
- *************************************************************************
- *
- * Jump vector table as in table 3.1 in [1]
- *
- *************************************************************************
- */
-
-
-.globl _start
-_start: b reset
- ldr pc, _undefined_instruction
- ldr pc, _software_interrupt
- ldr pc, _prefetch_abort
- ldr pc, _data_abort
- ldr pc, _not_used
- ldr pc, _irq
- ldr pc, _fiq
-
-_undefined_instruction: .word undefined_instruction
-_software_interrupt: .word software_interrupt
-_prefetch_abort: .word prefetch_abort
-_data_abort: .word data_abort
-_not_used: .word not_used
-_irq: .word irq
-_fiq: .word fiq
-
- .balignl 16,0xdeadbeef
-
-
-/*
- *************************************************************************
- *
- * Startup Code (reset vector)
- *
- * do important init only if we don't start from memory!
- * relocate armboot to ram
- * setup stack
- * jump to second stage
- *
- *************************************************************************
- */
-
-_TEXT_BASE:
- .word TEXT_BASE
-
-.globl _armboot_start
-_armboot_start:
- .word _start
-
-/*
- * These are defined in the board-specific linker script.
- */
-.globl _bss_start
-_bss_start:
- .word __bss_start
-
-.globl _bss_end
-_bss_end:
- .word _end
-
-#ifdef CONFIG_USE_IRQ
-/* IRQ stack memory (calculated at run-time) */
-.globl IRQ_STACK_START
-IRQ_STACK_START:
- .word 0x0badc0de
-
-/* IRQ stack memory (calculated at run-time) */
-.globl FIQ_STACK_START
-FIQ_STACK_START:
- .word 0x0badc0de
-#endif
-
-
-/*
- * the actual reset code
- */
-
-reset:
- /*
- * set the cpu to SVC32 mode
- */
- mrs r0,cpsr
- bic r0,r0,#0x1f
- orr r0,r0,#0xd3 /* was 13 */
- msr cpsr,r0
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
- /* scratch stack */
-/**** ldr r1, =0x00204000 ****/
- /* Insure word alignment */
-/**** bic r1, r1, #3 ****/
- /* Init stack SYS */
-/**** mov sp, r1 ****/
- /*
- * This does a lot more than just set up the memory, which
- * is why it's called lowlevel_init
- */
- bl lowlevel_init /* in lowlevel.S */
-
- /*
- * Read/modify/write CP15 control register
- * disable MMU, enable I-Cache, select Asychronous Clocking Mode
- */
-
- mrc p15, 0, r0, c1, c0, 0 @ read cp15 control register (cp15 r1) in r0
- bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
- bic r0, r0, #0x0000008f @ clear bits 7, 3:0 (B--- WCAM)
- orr r0, r0, #0x00000002 @ set bit 2 (A) Align
- orr r0, r0, #0x00000004 @ set bit 3 (C) D-Cache
- orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
- orr r0, r0, #0xC0000000 @ set bits 31:30 (iA, nF)
- mcr p15, 0, r0, c1, c0, 0 @ write r0 in cp15 control register (cp15 r1)
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
- /*
- * relocate exeception table
- */
- ldr r0, =_start
- ldr r1, =0x0
- mov r2, #16
-copyex:
- subs r2, r2, #1
- ldr r3, [r0], #4
- str r3, [r1], #4
- bne copyex
-
- /*
- * we do sys-critical inits only at reboot,
- * not when booting from ram!
- */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
- bl cpu_init_crit
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
-
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
-relocate: /* relocate U-Boot to RAM */
- adr r0, _start /* r0 <- current position of code */
- ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
- cmp r0, r1 /* don't reloc during debug */
- beq stack_setup
-
- ldr r2, _armboot_start
- ldr r3, _bss_start
- sub r2, r3, r2 /* r2 <- size of armboot */
- add r2, r0, r2 /* r2 <- source end address */
-
-copy_loop:
- ldmia r0!, {r3-r10} /* copy from source address [r0] */
- stmia r1!, {r3-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
- ble copy_loop
-#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
-
- /* Set up the stack */
-stack_setup:
- ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
- sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
- sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
-#ifdef CONFIG_USE_IRQ
- sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
-#endif
- sub sp, r0, #12 /* leave 3 words for abort-stack */
-
-clear_bss:
- ldr r0, _bss_start /* find start of bss segment */
- ldr r1, _bss_end /* stop here */
- mov r2, #0x00000000 /* clear */
-
-clbss_l:str r2, [r0] /* clear loop... */
- add r0, r0, #4
- cmp r0, r1
- ble clbss_l
-
- ldr pc,_start_armboot
-
-_start_armboot: .word start_armboot
-
-/*
- *************************************************************************
- *
- * CPU_init_critical registers
- *
- *************************************************************************
- */
-
-cpu_init_crit:
- /* do nothing for now */
- mov pc, lr
-
-
-/*
- *************************************************************************
- *
- * Interrupt handling
- *
- *************************************************************************
- */
-
-@
-@ IRQ stack frame.
-@
-#define S_FRAME_SIZE 72
-
-#define S_OLD_R0 68
-#define S_PSR 64
-#define S_PC 60
-#define S_LR 56
-#define S_SP 52
-
-#define S_IP 48
-#define S_FP 44
-#define S_R10 40
-#define S_R9 36
-#define S_R8 32
-#define S_R7 28
-#define S_R6 24
-#define S_R5 20
-#define S_R4 16
-#define S_R3 12
-#define S_R2 8
-#define S_R1 4
-#define S_R0 0
-
-#define MODE_SVC 0x13
-#define I_BIT 0x80
-
-/*
- * use bad_save_user_regs for abort/prefetch/undef/swi ...
- * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
- */
-
- .macro bad_save_user_regs
- sub sp, sp, #S_FRAME_SIZE
- stmia sp, {r0 - r12} @ Calling r0-r12
- add r8, sp, #S_PC
-
- ldr r2, _armboot_start
- sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
- sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
- ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0
- add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
-
- add r5, sp, #S_SP
- mov r1, lr
- stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r
- mov r0, sp
- .endm
-
- .macro irq_save_user_regs
- sub sp, sp, #S_FRAME_SIZE
- stmia sp, {r0 - r12} @ Calling r0-r12
- add r8, sp, #S_PC
- stmdb r8, {sp, lr}^ @ Calling SP, LR
- str lr, [r8, #0] @ Save calling PC
- mrs r6, spsr
- str r6, [r8, #4] @ Save CPSR
- str r0, [r8, #8] @ Save OLD_R0
- mov r0, sp
- .endm
-
- .macro irq_restore_user_regs
- ldmia sp, {r0 - lr}^ @ Calling r0 - lr
- mov r0, r0
- ldr lr, [sp, #S_PC] @ Get PC
- add sp, sp, #S_FRAME_SIZE
- subs pc, lr, #4 @ return & move spsr_svc into cpsr
- .endm
-
- .macro get_bad_stack
- ldr r13, _armboot_start @ setup our mode stack
- sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
- sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
-
- str lr, [r13] @ save caller lr / spsr
- mrs lr, spsr
- str lr, [r13, #4]
-
- mov r13, #MODE_SVC @ prepare SVC-Mode
- msr spsr_c, r13
- mov lr, pc
- movs pc, lr
- .endm
-
- .macro get_irq_stack @ setup IRQ stack
- ldr sp, IRQ_STACK_START
- .endm
-
- .macro get_fiq_stack @ setup FIQ stack
- ldr sp, FIQ_STACK_START
- .endm
-
-/*
- * exception handlers
- */
- .align 5
-undefined_instruction:
- get_bad_stack
- bad_save_user_regs
- bl do_undefined_instruction
-
- .align 5
-software_interrupt:
- get_bad_stack
- bad_save_user_regs
- bl do_software_interrupt
-
- .align 5
-prefetch_abort:
- get_bad_stack
- bad_save_user_regs
- bl do_prefetch_abort
-
- .align 5
-data_abort:
- get_bad_stack
- bad_save_user_regs
- bl do_data_abort
-
- .align 5
-not_used:
- get_bad_stack
- bad_save_user_regs
- bl do_not_used
-
-#ifdef CONFIG_USE_IRQ
-
- .align 5
-irq:
- get_irq_stack
- irq_save_user_regs
- bl do_irq
- irq_restore_user_regs
-
- .align 5
-fiq:
- get_fiq_stack
- /* someone ought to write a more effiction fiq_save_user_regs */
- irq_save_user_regs
- bl do_fiq
- irq_restore_user_regs
-
-#else
-
- .align 5
-irq:
- get_bad_stack
- bad_save_user_regs
- bl do_irq
-
- .align 5
-fiq:
- get_bad_stack
- bad_save_user_regs
- bl do_fiq
-
-#endif
-
- .align 5
-.globl reset_cpu
-reset_cpu:
- mov pc, r0
#ifndef __CONFIG_H
#define __CONFIG_H
-/*
- * If we are developing, we might want to start armboot from ram
- * so we MUST NOT initialize critical regs like mem-timing ...
- */
-#define CONFIG_INIT_CRITICAL /* undef for developing */
-#define RTC
-
/*
* High Level Configuration Options
* (easy to change)
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+#define RTC
+
/*
* Size of malloc() pool
*/
#define AT91_SLOW_CLOCK 32768 /* slow clock */
-#define CONFIG_AT91RM9200DK 1 /* on an AT91RM9200DK Board */
-#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
+#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */
+#define CONFIG_AT91RM9200DK 1 /* on an AT91RM9200DK Board */
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+#define USE_920T_MMU 1
+
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
#define AT91_SLOW_CLOCK 32768 /* slow clock */
-#define CONFIG_AT91RM9200DK 1 /* on an AT91RM9200DK Board */
-#define CONFIG_CMC_PU2 1 /* on an CMC_PU2 Board */
-#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
+#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */
+#define CONFIG_AT91RM9200DK 1 /* on an AT91RM9200DK Board */
+#define CONFIG_CMC_PU2 1 /* on an CMC_PU2 Board */
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+#define USE_920T_MMU 1
+
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
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