arm: socfpga: Add socfpga_spim_enable() to reset_manager.c

This function will be needed by the upcoming Designware master SPI
driver. As the SPI master controller is held in reset by the current
Preloader implementation. So we need to release the reset for the
driver to communicate with the controller.

This function is called from arch_early_init_r() if the SPI
driver is enabled.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Pavel Machek <pavel@denx.de>

diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c
index 8c3e5f7cd423c608ade2409fc233c0c706251b9d..73cffd3a8d6f13a3f1fe8c10de1675912de5ca62 100644 (file)
--- a/arch/arm/cpu/armv7/socfpga/misc.c
+++ b/arch/arm/cpu/armv7/socfpga/misc.c
@@ -202,6 +202,12 @@ int arch_early_init_r(void)
 
        /* Add device descriptor to FPGA device table */
        socfpga_fpga_add();
+
+#ifdef CONFIG_DESIGNWARE_SPI
+       /* Get Designware SPI controller out of reset */
+       socfpga_spim_enable();
+#endif
+
        return 0;
 }
 

diff --git a/arch/arm/cpu/armv7/socfpga/reset_manager.c b/arch/arm/cpu/armv7/socfpga/reset_manager.c
index 1d3a95d0c8e73cef22666f5f8adf42ba77e4f471..af9db850fef0a5635bfccf534050d29253ff4d8a 100644 (file)
--- a/arch/arm/cpu/armv7/socfpga/reset_manager.c
+++ b/arch/arm/cpu/armv7/socfpga/reset_manager.c
@@ -104,3 +104,12 @@ void socfpga_emac_reset(int enable)
 #endif
        }
 }
+
+/* SPI Master enable (its held in reset by the preloader) */
+void socfpga_spim_enable(void)
+{
+       const void *reset = &reset_manager_base->per_mod_reset;
+
+       clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SPIM0_LSB);
+       clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SPIM1_LSB);
+}

diff --git a/arch/arm/include/asm/arch-socfpga/reset_manager.h b/arch/arm/include/asm/arch-socfpga/reset_manager.h
index 1857b80b3e44005bfb13b3fb50054d01734fb7ab..034135bff46905ef97c532d0a03be554d12681ce 100644 (file)
--- a/arch/arm/include/asm/arch-socfpga/reset_manager.h
+++ b/arch/arm/include/asm/arch-socfpga/reset_manager.h
@@ -14,6 +14,7 @@ void socfpga_bridges_reset(int enable);
 
 void socfpga_emac_reset(int enable);
 void socfpga_watchdog_reset(void);
+void socfpga_spim_enable(void);
 
 struct socfpga_reset_manager {
        u32     status;
@@ -35,5 +36,7 @@ struct socfpga_reset_manager {
 #define RSTMGR_PERMODRST_EMAC0_LSB     0
 #define RSTMGR_PERMODRST_EMAC1_LSB     1
 #define RSTMGR_PERMODRST_L4WD0_LSB     6
+#define RSTMGR_PERMODRST_SPIM0_LSB     18
+#define RSTMGR_PERMODRST_SPIM1_LSB     19
 
 #endif /* _RESET_MANAGER_H_ */