Cut down the VDDIO/VDDA regulator stabilization delays to 500 uS. That should be
enough according to the datasheet and bootlets.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Robert Deliƫn <robert@delien.nl>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Matthias Fuchs <matthias.fuchs@esd.eu>
                        if (powered_by_linreg ||
                                (readl(&power_regs->hw_power_sts) &
                                        POWER_STS_VDD5V_GT_VDDIO))
-                               early_delay(1500);
+                               early_delay(500);
                        else {
                                while (!(readl(&power_regs->hw_power_sts) &
                                        POWER_STS_DC_OK))
                        if (powered_by_linreg ||
                                (readl(&power_regs->hw_power_sts) &
                                        POWER_STS_VDD5V_GT_VDDIO))
-                               early_delay(1500);
+                               early_delay(500);
                        else {
                                while (!(readl(&power_regs->hw_power_sts) &
                                        POWER_STS_DC_OK))
                        if (powered_by_linreg ||
                                (readl(&power_regs->hw_power_sts) &
                                        POWER_STS_VDD5V_GT_VDDIO))
-                               early_delay(1500);
+                               early_delay(500);
                        else {
                                while (!(readl(&power_regs->hw_power_sts) &
                                        POWER_STS_DC_OK))
                        if (powered_by_linreg ||
                                (readl(&power_regs->hw_power_sts) &
                                        POWER_STS_VDD5V_GT_VDDIO))
-                               early_delay(1500);
+                               early_delay(500);
                        else {
                                while (!(readl(&power_regs->hw_power_sts) &
                                        POWER_STS_DC_OK))