]> git.sur5r.net Git - u-boot/commitdiff
cfi_flash driver - Add delay after reset command
authorAaron Williams <aaron.williams@caviumnetworks.com>
Tue, 12 Apr 2011 07:59:04 +0000 (00:59 -0700)
committerStefan Roese <sr@denx.de>
Thu, 21 Apr 2011 13:51:49 +0000 (15:51 +0200)
I ran into a problem where the reset was failing except when I enabled
debugging support.  After talking with Garret Swalling at Spansion I
was told that the GL-N series of devices require a 500ns wait for the
reset to complete.  The below patch adds a 1us delay after all reset
commands.

-Aaron Williams

Signed-off-by: Aaron Williams <aaron.williams@caviumnetworks.com>
Signed-off-by: Stefan Roese <sr@denx.de>
drivers/mtd/cfi_flash.c

index aa76f6ce4812092350e924e2a7d1bbbac0f53e72..6039e1fadc0aa0003a9e34ab80284c46c0d180e3 100644 (file)
@@ -581,6 +581,7 @@ static int flash_status_check (flash_info_t * info, flash_sect_t sector,
                                prompt, info->start[sector],
                                flash_read_long (info, sector, 0));
                        flash_write_cmd (info, sector, 0, info->cmd_reset);
+                       udelay(1);
                        return ERR_TIMOUT;
                }
                udelay (1);             /* also triggers watchdog */
@@ -628,6 +629,7 @@ static int flash_full_status_check (flash_info_t * info, flash_sect_t sector,
                                puts ("Vpp Low Error.\n");
                }
                flash_write_cmd (info, sector, 0, info->cmd_reset);
+               udelay(1);
                break;
        default:
                break;
@@ -1491,6 +1493,7 @@ void flash_read_user_serial (flash_info_t * info, void *buffer, int offset,
        flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID);
        memcpy (dst, src + offset, len);
        flash_write_cmd (info, 0, 0, info->cmd_reset);
+       udelay(1);
        flash_unmap(info, 0, FLASH_OFFSET_USER_PROTECTION, src);
 }
 
@@ -1506,6 +1509,7 @@ void flash_read_factory_serial (flash_info_t * info, void *buffer, int offset,
        flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID);
        memcpy (buffer, src + offset, len);
        flash_write_cmd (info, 0, 0, info->cmd_reset);
+       udelay(1);
        flash_unmap(info, 0, FLASH_OFFSET_INTEL_PROTECTION, src);
 }
 
@@ -1537,6 +1541,7 @@ static void cfi_reverse_geometry(struct cfi_qry *qry)
 static void cmdset_intel_read_jedec_ids(flash_info_t *info)
 {
        flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+       udelay(1);
        flash_write_cmd(info, 0, 0, FLASH_CMD_READ_ID);
        udelay(1000); /* some flash are slow to respond */
        info->manufacturer_id = flash_read_uchar (info,
@@ -1613,6 +1618,7 @@ static void cmdset_amd_read_jedec_ids(flash_info_t *info)
                break;
        }
        flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
+       udelay(1);
 }
 
 static int cmdset_amd_init(flash_info_t *info, struct cfi_qry *qry)
@@ -1739,6 +1745,7 @@ void __flash_cmd_reset(flash_info_t *info)
         * that AMD flash roms ignore the Intel command.
         */
        flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
+       udelay(1);
        flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
 }
 void flash_cmd_reset(flash_info_t *info)