--- /dev/null
+/*
+ * Creative ZEN X-Fi3 setup
+ *
+ * Copyright (C) 2013 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+#include <asm/arch/iomux-mx23.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+
+#define MUX_CONFIG_EMI (MXS_PAD_1V8 | MXS_PAD_12MA | MXS_PAD_PULLUP)
+#define MUX_CONFIG_SSP (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
+#define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
+
+const iomux_cfg_t iomux_setup[] = {
+ /* EMI */
+ MX23_PAD_EMI_D00__EMI_D00 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D01__EMI_D01 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D02__EMI_D02 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D03__EMI_D03 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D04__EMI_D04 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D05__EMI_D05 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D06__EMI_D06 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D07__EMI_D07 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D08__EMI_D08 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D09__EMI_D09 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D10__EMI_D10 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D11__EMI_D11 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D12__EMI_D12 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D13__EMI_D13 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D14__EMI_D14 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D15__EMI_D15 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_CLKN__EMI_CLKN | MUX_CONFIG_EMI,
+
+ MX23_PAD_EMI_A00__EMI_A00 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_A01__EMI_A01 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_A02__EMI_A02 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_A03__EMI_A03 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_A04__EMI_A04 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_A05__EMI_A05 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_A06__EMI_A06 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_A07__EMI_A07 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_A08__EMI_A08 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_A09__EMI_A09 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_A10__EMI_A10 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_A11__EMI_A11 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_A12__EMI_A12 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
+
+ MX23_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
+
+ MX23_PAD_LCD_D00__LCD_D00 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D01__LCD_D01 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D02__LCD_D02 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D03__LCD_D03 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D04__LCD_D04 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D05__LCD_D05 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D06__LCD_D06 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D07__LCD_D07 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D08__LCD_D08 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D09__LCD_D09 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_RESET__LCD_RESET | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_RS__LCD_RS | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_WR__LCD_WR | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_CS__LCD_CS | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_VSYNC__LCD_VSYNC | MUX_CONFIG_LCD,
+
+ MX23_PAD_SSP1_CMD__SSP1_CMD | MUX_CONFIG_SSP,
+ MX23_PAD_SSP1_DETECT__GPIO_2_1 | MUX_CONFIG_SSP,
+ MX23_PAD_SSP1_DATA0__SSP1_DATA0 | MUX_CONFIG_SSP,
+ MX23_PAD_SSP1_DATA1__SSP1_DATA1 | MUX_CONFIG_SSP,
+ MX23_PAD_SSP1_DATA2__SSP1_DATA2 | MUX_CONFIG_SSP,
+ MX23_PAD_SSP1_DATA3__SSP1_DATA3 | MUX_CONFIG_SSP,
+ MX23_PAD_SSP1_SCK__SSP1_SCK | MUX_CONFIG_SSP,
+ MX23_PAD_GPMI_D07__GPIO_0_7 | MUX_CONFIG_SSP,
+
+ MX23_PAD_GPMI_D00__SSP2_DATA0 | MUX_CONFIG_SSP,
+ MX23_PAD_GPMI_D01__SSP2_DATA1 | MUX_CONFIG_SSP,
+ MX23_PAD_GPMI_D02__SSP2_DATA2 | MUX_CONFIG_SSP,
+ MX23_PAD_GPMI_D03__SSP2_DATA3 | MUX_CONFIG_SSP,
+ MX23_PAD_GPMI_RDY1__SSP2_CMD | MUX_CONFIG_SSP,
+ MX23_PAD_GPMI_WRN__SSP2_SCK | MUX_CONFIG_SSP,
+
+ /* PWM -- FIXME */
+ MX23_PAD_PWM2__GPIO_1_28 | MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP,
+};
+
+void mxs_adjust_memory_params(uint32_t *dram_vals)
+{
+ /* mDDR configuration values */
+ const uint32_t regs[] = {
+ 0x01010001, 0x00010000, 0x01000000, 0x00000001,
+ 0x00010101, 0x00000001, 0x00010000, 0x01000001,
+ 0x01010000, 0x00000001, 0x07000200, 0x04070203,
+ 0x02020002, 0x06070a02, 0x0d000201, 0x0305000d,
+ 0x02080800, 0x19330f0a, 0x1f1f1c00, 0x020a1313,
+ 0x03061323, 0x0000000a, 0x00080008, 0x00200020,
+ 0x00200020, 0x00200020, 0x000003f7, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000020, 0x00000000,
+ 0x001023cd, 0x20410010, 0x00006665, 0x00000000,
+ 0x00000101, 0x00000001, 0x00000000, 0x00000000,
+ };
+ memcpy(dram_vals, regs, sizeof(regs));
+}
+
+void board_init_ll(const uint32_t arg, const uint32_t *resptr)
+{
+ mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
+}
--- /dev/null
+/*
+ * Creative ZEN X-Fi3 board
+ *
+ * Copyright (C) 2013 Marek Vasut <marex@denx.de>
+ *
+ * Hardware investigation done by:
+ *
+ * Amaury Pouly <amaury.pouly@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/iomux-mx23.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Functions
+ */
+int board_early_init_f(void)
+{
+ /* IO0 clock at 480MHz */
+ mxs_set_ioclk(MXC_IOCLK0, 480000);
+
+ /* SSP0 clock at 96MHz */
+ mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ return mxs_dram_init();
+}
+
+#ifdef CONFIG_CMD_MMC
+static int xfi3_mmc_cd(int id)
+{
+ switch (id) {
+ case 0:
+ /* The SSP_DETECT is inverted on this board. */
+ return gpio_get_value(MX23_PAD_SSP1_DETECT__GPIO_2_1);
+ case 1:
+ /* Phison bridge always present */
+ return 1;
+ default:
+ return 0;
+ }
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ int ret;
+
+ /* MicroSD slot */
+ gpio_direction_input(MX23_PAD_SSP1_DETECT__GPIO_2_1);
+ gpio_direction_output(MX23_PAD_GPMI_D07__GPIO_0_7, 0);
+ ret = mxsmmc_initialize(bis, 0, NULL, xfi3_mmc_cd);
+ if (ret)
+ return ret;
+
+ /* Phison SD-NAND bridge */
+ ret = mxsmmc_initialize(bis, 1, NULL, xfi3_mmc_cd);
+
+ return ret;
+}
+#endif
+
+#ifdef CONFIG_VIDEO_MXS
+static int mxsfb_write_byte(uint32_t payload, const unsigned int data)
+{
+ struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
+ const unsigned int timeout = 0x10000;
+
+ if (mxs_wait_mask_clr(®s->hw_lcdif_ctrl_reg, LCDIF_CTRL_RUN,
+ timeout))
+ return -ETIMEDOUT;
+
+ writel((1 << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) |
+ (1 << LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET),
+ ®s->hw_lcdif_transfer_count);
+
+ writel(LCDIF_CTRL_DATA_SELECT | LCDIF_CTRL_RUN,
+ ®s->hw_lcdif_ctrl_clr);
+
+ if (data)
+ writel(LCDIF_CTRL_DATA_SELECT, ®s->hw_lcdif_ctrl_set);
+
+ writel(LCDIF_CTRL_RUN, ®s->hw_lcdif_ctrl_set);
+
+ if (mxs_wait_mask_clr(®s->hw_lcdif_lcdif_stat_reg, 1 << 29,
+ timeout))
+ return -ETIMEDOUT;
+
+ writel(payload, ®s->hw_lcdif_data);
+ return mxs_wait_mask_clr(®s->hw_lcdif_ctrl_reg, LCDIF_CTRL_RUN,
+ timeout);
+}
+
+static void mxsfb_write_register(uint32_t reg, uint32_t data)
+{
+ mxsfb_write_byte(reg, 0);
+ mxsfb_write_byte(data, 1);
+}
+
+static const struct {
+ uint8_t reg;
+ uint8_t delay;
+ uint16_t val;
+} lcd_regs[] = {
+ { 0x01, 0, 0x001c },
+ { 0x02, 0, 0x0100 },
+ /* Writing 0x30 to reg. 0x03 flips the LCD */
+ { 0x03, 0, 0x1038 },
+ { 0x08, 0, 0x0808 },
+ /* This can contain 0x111 to rotate the LCD. */
+ { 0x0c, 0, 0x0000 },
+ { 0x0f, 0, 0x0c01 },
+ { 0x20, 0, 0x0000 },
+ { 0x21, 30, 0x0000 },
+ /* Wait 30 mS here */
+ { 0x10, 0, 0x0a00 },
+ { 0x11, 30, 0x1038 },
+ /* Wait 30 mS here */
+ { 0x12, 0, 0x1010 },
+ { 0x13, 0, 0x0050 },
+ { 0x14, 0, 0x4f58 },
+ { 0x30, 0, 0x0000 },
+ { 0x31, 0, 0x00db },
+ { 0x32, 0, 0x0000 },
+ { 0x33, 0, 0x0000 },
+ { 0x34, 0, 0x00db },
+ { 0x35, 0, 0x0000 },
+ { 0x36, 0, 0x00af },
+ { 0x37, 0, 0x0000 },
+ { 0x38, 0, 0x00db },
+ { 0x39, 0, 0x0000 },
+ { 0x50, 0, 0x0000 },
+ { 0x51, 0, 0x0705 },
+ { 0x52, 0, 0x0e0a },
+ { 0x53, 0, 0x0300 },
+ { 0x54, 0, 0x0a0e },
+ { 0x55, 0, 0x0507 },
+ { 0x56, 0, 0x0000 },
+ { 0x57, 0, 0x0003 },
+ { 0x58, 0, 0x090a },
+ { 0x59, 30, 0x0a09 },
+ /* Wait 30 mS here */
+ { 0x07, 30, 0x1017 },
+ /* Wait 40 mS here */
+ { 0x36, 0, 0x00af },
+ { 0x37, 0, 0x0000 },
+ { 0x38, 0, 0x00db },
+ { 0x39, 0, 0x0000 },
+ { 0x20, 0, 0x0000 },
+ { 0x21, 0, 0x0000 },
+};
+
+void board_mxsfb_system_setup(void)
+{
+ struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
+ int i;
+
+ /* Switch the LCDIF into System-Mode */
+ writel(LCDIF_CTRL_LCDIF_MASTER | LCDIF_CTRL_DOTCLK_MODE |
+ LCDIF_CTRL_BYPASS_COUNT, ®s->hw_lcdif_ctrl_clr);
+
+ /* Restart the SmartLCD controller */
+ mdelay(50);
+ writel(1, ®s->hw_lcdif_ctrl1_set);
+ mdelay(50);
+ writel(1, ®s->hw_lcdif_ctrl1_clr);
+ mdelay(50);
+ writel(1, ®s->hw_lcdif_ctrl1_set);
+ mdelay(50);
+
+ /* Program the SmartLCD controller */
+ writel(LCDIF_CTRL1_RECOVER_ON_UNDERFLOW, ®s->hw_lcdif_ctrl1_set);
+
+ writel((0x03 << LCDIF_TIMING_CMD_HOLD_OFFSET) |
+ (0x03 << LCDIF_TIMING_CMD_SETUP_OFFSET) |
+ (0x03 << LCDIF_TIMING_DATA_HOLD_OFFSET) |
+ (0x02 << LCDIF_TIMING_DATA_SETUP_OFFSET),
+ ®s->hw_lcdif_timing);
+
+ /*
+ * OTM2201A init and configuration sequence.
+ */
+ for (i = 0; i < ARRAY_SIZE(lcd_regs); i++) {
+ mxsfb_write_register(lcd_regs[i].reg, lcd_regs[i].val);
+ if (lcd_regs[i].delay)
+ mdelay(lcd_regs[i].delay);
+ }
+ /* Turn on Framebuffer Upload Mode */
+ mxsfb_write_byte(0x22, 0);
+
+ writel(LCDIF_CTRL_LCDIF_MASTER | LCDIF_CTRL_DATA_SELECT,
+ ®s->hw_lcdif_ctrl_set);
+}
+#endif
+
+int board_init(void)
+{
+ /* Adress of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ /* Turn on PWM backlight */
+ gpio_direction_output(MX23_PAD_PWM2__GPIO_1_28, 1);
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ usb_eth_initialize(bis);
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2013 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __CONFIGS_XFI3_H__
+#define __CONFIGS_XFI3_H__
+
+/* System configurations */
+#define CONFIG_MX23 /* i.MX23 SoC */
+
+/* U-Boot Commands */
+#define CONFIG_SYS_NO_FLASH
+#include <config_cmd_default.h>
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_GPIO
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_USB
+#define CONFIG_VIDEO
+
+/* Memory configuration */
+#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
+#define PHYS_SDRAM_1 0x40000000 /* Base address */
+#define PHYS_SDRAM_1_SIZE 0x08000000 /* Max 128 MB RAM */
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+
+/* Environment */
+#define CONFIG_ENV_SIZE (16 * 1024)
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_OVERWRITE
+
+/* Booting Linux */
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_BOOTARGS "console=ttyAMA0,115200n8 "
+#define CONFIG_LOADADDR 0x42000000
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+/* LCD */
+#ifdef CONFIG_VIDEO
+#define CONFIG_VIDEO_FONT_4X6
+#define CONFIG_VIDEO_MXS_MODE_SYSTEM
+#define CONFIG_SYS_BLACK_IN_WRITE
+#define LCD_BPP LCD_COLOR16
+#endif
+
+/* USB */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_EHCI_MXS_PORT0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+
+#define CONFIG_MV_UDC /* ChipIdea CI13xxx UDC */
+#define CONFIG_USB_GADGET_DUALSPEED
+
+#define CONFIG_USB_ETHER
+#define CONFIG_USB_ETH_CDC
+#define CONFIG_NETCONSOLE
+#endif
+
+/* The rest of the configuration is shared */
+#include <configs/mxs.h>
+
+#endif /* __CONFIGS_XFI3_H__ */
projects / u-boot / commitdiff