at91: Update board NAND drivers to current API.

Signed-off-by: Scott Wood <scottwood@freescale.com>

diff --git a/board/atmel/at91cap9adk/nand.c b/board/atmel/at91cap9adk/nand.c
index 0432ef13d8525253d382c277b103ccc0862a2937..1dec5582f7a7c02b85771a08033a5e17ca5877b7 100644 (file)
--- a/board/atmel/at91cap9adk/nand.c
+++ b/board/atmel/at91cap9adk/nand.c
@@ -37,36 +37,35 @@
 #define        MASK_ALE        (1 << 21)       /* our ALE is AD21 */
 #define        MASK_CLE        (1 << 22)       /* our CLE is AD22 */
 
-static void at91cap9adk_nand_hwcontrol(struct mtd_info *mtd, int cmd)
+static void at91cap9adk_nand_hwcontrol(struct mtd_info *mtd,
+                                      int cmd, unsigned int ctrl)
 {
        struct nand_chip *this = mtd->priv;
-       ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
 
-       IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
-       switch (cmd) {
-       case NAND_CTL_SETCLE:
-               IO_ADDR_W |= MASK_CLE;
-               break;
-       case NAND_CTL_SETALE:
-               IO_ADDR_W |= MASK_ALE;
-               break;
-       case NAND_CTL_CLRNCE:
-               at91_set_gpio_value(AT91_PIN_PD15, 1);
-               break;
-       case NAND_CTL_SETNCE:
-               at91_set_gpio_value(AT91_PIN_PD15, 0);
-               break;
+       if (ctrl & NAND_CTRL_CHANGE) {
+               ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
+               IO_ADDR_W &= ~(MASK_ALE | MASK_CLE);
+
+               if (ctrl & NAND_CLE)
+                       IO_ADDR_W |= MASK_CLE;
+               if (ctrl & NAND_ALE)
+                       IO_ADDR_W |= MASK_ALE;
+
+               at91_set_gpio_value(AT91_PIN_PD15, !(ctrl & NAND_NCE));
+               this->IO_ADDR_W = (void *) IO_ADDR_W;
        }
-       this->IO_ADDR_W = (void *) IO_ADDR_W;
+
+       if (cmd != NAND_CMD_NONE)
+               writeb(cmd, this->IO_ADDR_W);
 }
 
 int board_nand_init(struct nand_chip *nand)
 {
-       nand->eccmode = NAND_ECC_SOFT;
+       nand->ecc.mode = NAND_ECC_SOFT;
 #ifdef CFG_NAND_DBW_16
        nand->options = NAND_BUSWIDTH_16;
 #endif
-       nand->hwcontrol = at91cap9adk_nand_hwcontrol;
+       nand->cmd_ctrl = at91cap9adk_nand_hwcontrol;
        nand->chip_delay = 20;
 
        return 0;

diff --git a/board/atmel/at91sam9260ek/nand.c b/board/atmel/at91sam9260ek/nand.c
index 9738f0fd48a8576b5e0b06db212fc59ab29c5a2e..665e35c54b96b4894bb721bc69efa620f552026b 100644 (file)
--- a/board/atmel/at91sam9260ek/nand.c
+++ b/board/atmel/at91sam9260ek/nand.c
@@ -37,27 +37,26 @@
 #define        MASK_ALE        (1 << 21)       /* our ALE is AD21 */
 #define        MASK_CLE        (1 << 22)       /* our CLE is AD22 */
 
-static void at91sam9260ek_nand_hwcontrol(struct mtd_info *mtd, int cmd)
+static void at91sam9260ek_nand_hwcontrol(struct mtd_info *mtd,
+                                        int cmd, unsigned int ctrl)
 {
        struct nand_chip *this = mtd->priv;
-       ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
 
-       IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
-       switch (cmd) {
-       case NAND_CTL_SETCLE:
-               IO_ADDR_W |= MASK_CLE;
-               break;
-       case NAND_CTL_SETALE:
-               IO_ADDR_W |= MASK_ALE;
-               break;
-       case NAND_CTL_CLRNCE:
-               at91_set_gpio_value(AT91_PIN_PC14, 1);
-               break;
-       case NAND_CTL_SETNCE:
-               at91_set_gpio_value(AT91_PIN_PC14, 0);
-               break;
+       if (ctrl & NAND_CTRL_CHANGE) {
+               ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
+               IO_ADDR_W &= ~(MASK_ALE | MASK_CLE);
+
+               if (ctrl & NAND_CLE)
+                       IO_ADDR_W |= MASK_CLE;
+               if (ctrl & NAND_ALE)
+                       IO_ADDR_W |= MASK_ALE;
+
+               at91_set_gpio_value(AT91_PIN_PC14, !(ctrl & NAND_NCE));
+               this->IO_ADDR_W = (void *) IO_ADDR_W;
        }
-       this->IO_ADDR_W = (void *) IO_ADDR_W;
+
+       if (cmd != NAND_CMD_NONE)
+               writeb(cmd, this->IO_ADDR_W);
 }
 
 static int at91sam9260ek_nand_ready(struct mtd_info *mtd)
@@ -67,11 +66,11 @@ static int at91sam9260ek_nand_ready(struct mtd_info *mtd)
 
 int board_nand_init(struct nand_chip *nand)
 {
-       nand->eccmode = NAND_ECC_SOFT;
+       nand->ecc.mode = NAND_ECC_SOFT;
 #ifdef CFG_NAND_DBW_16
        nand->options = NAND_BUSWIDTH_16;
 #endif
-       nand->hwcontrol = at91sam9260ek_nand_hwcontrol;
+       nand->cmd_ctrl = at91sam9260ek_nand_hwcontrol;
        nand->dev_ready = at91sam9260ek_nand_ready;
        nand->chip_delay = 20;
 

diff --git a/board/atmel/at91sam9261ek/nand.c b/board/atmel/at91sam9261ek/nand.c
index 35b26dbefef24fb3b720dbd90d57c6bd6862b48d..fccb9d78def34449be0c8cdc74873672822af388 100644 (file)
--- a/board/atmel/at91sam9261ek/nand.c
+++ b/board/atmel/at91sam9261ek/nand.c
@@ -37,27 +37,26 @@
 #define        MASK_ALE        (1 << 22)       /* our ALE is AD22 */
 #define        MASK_CLE        (1 << 21)       /* our CLE is AD21 */
 
-static void at91sam9261ek_nand_hwcontrol(struct mtd_info *mtd, int cmd)
+static void at91sam9261ek_nand_hwcontrol(struct mtd_info *mtd,
+                                        int cmd, unsigned int ctrl)
 {
        struct nand_chip *this = mtd->priv;
-       ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
 
-       IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
-       switch (cmd) {
-       case NAND_CTL_SETCLE:
-               IO_ADDR_W |= MASK_CLE;
-               break;
-       case NAND_CTL_SETALE:
-               IO_ADDR_W |= MASK_ALE;
-               break;
-       case NAND_CTL_CLRNCE:
-               at91_set_gpio_value(AT91_PIN_PC14, 1);
-               break;
-       case NAND_CTL_SETNCE:
-               at91_set_gpio_value(AT91_PIN_PC14, 0);
-               break;
+       if (ctrl & NAND_CTRL_CHANGE) {
+               ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
+               IO_ADDR_W &= ~(MASK_ALE | MASK_CLE);
+
+               if (ctrl & NAND_CLE)
+                       IO_ADDR_W |= MASK_CLE;
+               if (ctrl & NAND_ALE)
+                       IO_ADDR_W |= MASK_ALE;
+
+               at91_set_gpio_value(AT91_PIN_PC14, !(ctrl & NAND_NCE));
+               this->IO_ADDR_W = (void *) IO_ADDR_W;
        }
-       this->IO_ADDR_W = (void *) IO_ADDR_W;
+
+       if (cmd != NAND_CMD_NONE)
+               writeb(cmd, this->IO_ADDR_W);
 }
 
 static int at91sam9261ek_nand_ready(struct mtd_info *mtd)
@@ -67,11 +66,11 @@ static int at91sam9261ek_nand_ready(struct mtd_info *mtd)
 
 int board_nand_init(struct nand_chip *nand)
 {
-       nand->eccmode = NAND_ECC_SOFT;
+       nand->ecc.mode = NAND_ECC_SOFT;
 #ifdef CFG_NAND_DBW_16
        nand->options = NAND_BUSWIDTH_16;
 #endif
-       nand->hwcontrol = at91sam9261ek_nand_hwcontrol;
+       nand->cmd_ctrl = at91sam9261ek_nand_hwcontrol;
        nand->dev_ready = at91sam9261ek_nand_ready;
        nand->chip_delay = 20;
 

diff --git a/board/atmel/at91sam9263ek/nand.c b/board/atmel/at91sam9263ek/nand.c
index 5079972652f232e0460614919d7f9db206f1ca94..250ec7f3943c059211864cf12982df41772662ff 100644 (file)
--- a/board/atmel/at91sam9263ek/nand.c
+++ b/board/atmel/at91sam9263ek/nand.c
@@ -37,27 +37,26 @@
 #define        MASK_ALE        (1 << 21)       /* our ALE is AD21 */
 #define        MASK_CLE        (1 << 22)       /* our CLE is AD22 */
 
-static void at91sam9263ek_nand_hwcontrol(struct mtd_info *mtd, int cmd)
+static void at91sam9263ek_nand_hwcontrol(struct mtd_info *mtd,
+                                        int cmd, unsigned int ctrl)
 {
        struct nand_chip *this = mtd->priv;
-       ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
 
-       IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
-       switch (cmd) {
-       case NAND_CTL_SETCLE:
-               IO_ADDR_W |= MASK_CLE;
-               break;
-       case NAND_CTL_SETALE:
-               IO_ADDR_W |= MASK_ALE;
-               break;
-       case NAND_CTL_CLRNCE:
-               at91_set_gpio_value(AT91_PIN_PD15, 1);
-               break;
-       case NAND_CTL_SETNCE:
-               at91_set_gpio_value(AT91_PIN_PD15, 0);
-               break;
+       if (ctrl & NAND_CTRL_CHANGE) {
+               ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
+               IO_ADDR_W &= ~(MASK_ALE | MASK_CLE);
+
+               if (ctrl & NAND_CLE)
+                       IO_ADDR_W |= MASK_CLE;
+               if (ctrl & NAND_ALE)
+                       IO_ADDR_W |= MASK_ALE;
+
+               at91_set_gpio_value(AT91_PIN_PD15, !(ctrl & NAND_NCE));
+               this->IO_ADDR_W = (void *) IO_ADDR_W;
        }
-       this->IO_ADDR_W = (void *) IO_ADDR_W;
+
+       if (cmd != NAND_CMD_NONE)
+               writeb(cmd, this->IO_ADDR_W);
 }
 
 static int at91sam9263ek_nand_ready(struct mtd_info *mtd)
@@ -67,11 +66,11 @@ static int at91sam9263ek_nand_ready(struct mtd_info *mtd)
 
 int board_nand_init(struct nand_chip *nand)
 {
-       nand->eccmode = NAND_ECC_SOFT;
+       nand->ecc.mode = NAND_ECC_SOFT;
 #ifdef CFG_NAND_DBW_16
        nand->options = NAND_BUSWIDTH_16;
 #endif
-       nand->hwcontrol = at91sam9263ek_nand_hwcontrol;
+       nand->cmd_ctrl = at91sam9263ek_nand_hwcontrol;
        nand->dev_ready = at91sam9263ek_nand_ready;
        nand->chip_delay = 20;
 

diff --git a/board/atmel/at91sam9rlek/nand.c b/board/atmel/at91sam9rlek/nand.c
index 5af1a311750b56c64a3d4e9f31e04d7bd0527994..eb342b842f211e41e9ae60b7ce11ca21f995617a 100644 (file)
--- a/board/atmel/at91sam9rlek/nand.c
+++ b/board/atmel/at91sam9rlek/nand.c
@@ -37,27 +37,26 @@
 #define        MASK_ALE        (1 << 21)       /* our ALE is AD21 */
 #define        MASK_CLE        (1 << 22)       /* our CLE is AD22 */
 
-static void at91sam9rlek_nand_hwcontrol(struct mtd_info *mtd, int cmd)
+static void at91sam9rlek_nand_hwcontrol(struct mtd_info *mtd,
+                                       int cmd, unsigned int ctrl)
 {
        struct nand_chip *this = mtd->priv;
-       ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
 
-       IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
-       switch (cmd) {
-       case NAND_CTL_SETCLE:
-               IO_ADDR_W |= MASK_CLE;
-               break;
-       case NAND_CTL_SETALE:
-               IO_ADDR_W |= MASK_ALE;
-               break;
-       case NAND_CTL_CLRNCE:
-               at91_set_gpio_value(AT91_PIN_PB6, 1);
-               break;
-       case NAND_CTL_SETNCE:
-               at91_set_gpio_value(AT91_PIN_PB6, 0);
-               break;
+       if (ctrl & NAND_CTRL_CHANGE) {
+               ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
+               IO_ADDR_W &= ~(MASK_ALE | MASK_CLE);
+
+               if (ctrl & NAND_CLE)
+                       IO_ADDR_W |= MASK_CLE;
+               if (ctrl & NAND_ALE)
+                       IO_ADDR_W |= MASK_ALE;
+
+               at91_set_gpio_value(AT91_PIN_PB6, !(ctrl & NAND_NCE));
+               this->IO_ADDR_W = (void *) IO_ADDR_W;
        }
-       this->IO_ADDR_W = (void *) IO_ADDR_W;
+
+       if (cmd != NAND_CMD_NONE)
+               writeb(cmd, this->IO_ADDR_W);
 }
 
 static int at91sam9rlek_nand_ready(struct mtd_info *mtd)
@@ -67,11 +66,11 @@ static int at91sam9rlek_nand_ready(struct mtd_info *mtd)
 
 int board_nand_init(struct nand_chip *nand)
 {
-       nand->eccmode = NAND_ECC_SOFT;
+       nand->ecc.mode = NAND_ECC_SOFT;
 #ifdef CFG_NAND_DBW_16
        nand->options = NAND_BUSWIDTH_16;
 #endif
-       nand->hwcontrol = at91sam9rlek_nand_hwcontrol;
+       nand->cmd_ctrl = at91sam9rlek_nand_hwcontrol;
        nand->dev_ready = at91sam9rlek_nand_ready;
        nand->chip_delay = 20;