logicpd-torpedo-37xx-devkit.dtb \
logicpd-som-lv-37xx-devkit.dtb
+dtb-$(CONFIG_TARGET_SAMA5D2_PTC_EK) += \
+ at91-sama5d2_ptc_ek.dtb
+
dtb-$(CONFIG_TARGET_SAMA5D2_XPLAINED) += \
at91-sama5d2_xplained.dtb
--- /dev/null
+/*
+ * at91-sama5d2_ptc_ek.dts - Device Tree file for SAMA5D2 PTC EK board
+ *
+ * Copyright (C) 2017 Microchip Technology Inc,
+ * Ludovic Desroches <ludovic.desroches@microchip.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include "sama5d2.dtsi"
+#include "sama5d2-pinfunc.h"
+
+/ {
+ model = "Atmel SAMA5D2 PTC EK";
+ compatible = "atmel,sama5d2-ptc_ek", "atmel,sama5d2", "atmel,sama5";
+
+ chosen {
+ u-boot,dm-pre-reloc;
+ stdout-path = &uart0;
+ };
+
+ ahb {
+ usb0: gadget@00300000 {
+ atmel,vbus-gpio = <&pioA PIN_PA27 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usba_vbus>;
+ status = "okay";
+ };
+
+ usb1: ohci@00400000 {
+ num-ports = <3>;
+ atmel,vbus-gpio = <0
+ &pioA PIN_PB12 GPIO_ACTIVE_HIGH
+ 0
+ >;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_default>;
+ status = "okay";
+ };
+
+ usb2: ehci@00500000 {
+ status = "okay";
+ };
+
+ sdmmc0: sdio-host@a0000000 {
+ bus-width = <8>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdmmc0_cmd_dat_default &pinctrl_sdmmc0_ck_cd_default>;
+ status = "okay";
+ u-boot,dm-pre-reloc;
+ };
+
+ sdmmc1: sdio-host@b0000000 {
+ bus-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdmmc1_cmd_dat_default &pinctrl_sdmmc1_ck_cd_default>;
+ status = "disabled"; /* conflicts with nand and qspi0*/
+ u-boot,dm-pre-reloc;
+ };
+
+ apb {
+ macb0: ethernet@f8008000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_macb0_rmii &pinctrl_macb0_phy_irq>;
+ phy-mode = "rmii";
+ status = "okay";
+
+ ethernet-phy@1 {
+ reg = <0x1>;
+ };
+ };
+
+ uart0: serial@f801c000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0_default>;
+ status = "okay";
+ u-boot,dm-pre-reloc;
+ };
+
+ i2c1: i2c@fc028000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ status = "okay";
+
+ i2c_eeprom: i2c_eeprom@50 {
+ compatible = "atmel,24mac402";
+ reg = <0x50>;
+ };
+ };
+
+ pioA: gpio@fc038000 {
+ pinctrl {
+ pinctrl_i2c1_default: i2c1_default {
+ pinmux = <PIN_PC6__TWD1>,
+ <PIN_PC7__TWCK1>;
+ bias-disable;
+ };
+
+ pinctrl_macb0_phy_irq: macb0_phy_irq {
+ pinmux = <PIN_PB24__GPIO>;
+ bias-disable;
+ };
+
+ pinctrl_macb0_rmii: macb0_rmii {
+ pinmux = <PIN_PB14__GTXCK>,
+ <PIN_PB15__GTXEN>,
+ <PIN_PB16__GRXDV>,
+ <PIN_PB17__GRXER>,
+ <PIN_PB18__GRX0>,
+ <PIN_PB19__GRX1>,
+ <PIN_PB20__GTX0>,
+ <PIN_PB21__GTX1>,
+ <PIN_PB22__GMDC>,
+ <PIN_PB23__GMDIO>;
+ bias-disable;
+ };
+
+ pinctrl_sdmmc0_cmd_dat_default: sdmmc0_cmd_dat_default {
+ pinmux = <PIN_PA1__SDMMC0_CMD>,
+ <PIN_PA2__SDMMC0_DAT0>,
+ <PIN_PA3__SDMMC0_DAT1>,
+ <PIN_PA4__SDMMC0_DAT2>,
+ <PIN_PA5__SDMMC0_DAT3>,
+ <PIN_PA6__SDMMC0_DAT4>,
+ <PIN_PA7__SDMMC0_DAT5>,
+ <PIN_PA8__SDMMC0_DAT6>,
+ <PIN_PA9__SDMMC0_DAT7>;
+ bias-pull-up;
+ u-boot,dm-pre-reloc;
+ };
+
+ pinctrl_sdmmc0_ck_cd_default: sdmmc0_ck_cd_default {
+ pinmux = <PIN_PA0__SDMMC0_CK>,
+ <PIN_PA10__SDMMC0_RSTN>,
+ <PIN_PA11__SDMMC0_VDDSEL>,
+ <PIN_PA13__SDMMC0_CD>;
+ bias-disable;
+ u-boot,dm-pre-reloc;
+ };
+
+ pinctrl_sdmmc1_cmd_dat_default: sdmmc1_cmd_dat_default {
+ pinmux = <PIN_PA28__SDMMC1_CMD>,
+ <PIN_PA18__SDMMC1_DAT0>,
+ <PIN_PA19__SDMMC1_DAT1>,
+ <PIN_PA20__SDMMC1_DAT2>,
+ <PIN_PA21__SDMMC1_DAT3>;
+ bias-pull-up;
+ u-boot,dm-pre-reloc;
+ };
+
+ pinctrl_sdmmc1_ck_cd_default: sdmmc1_ck_cd_default {
+ pinmux = <PIN_PA22__SDMMC1_CK>,
+ <PIN_PA30__SDMMC1_CD>;
+ bias-disable;
+ u-boot,dm-pre-reloc;
+ };
+
+ pinctrl_uart0_default: uart0_default {
+ pinmux = <PIN_PB26__URXD0>,
+ <PIN_PB27__UTXD0>;
+ bias-disable;
+ u-boot,dm-pre-reloc;
+ };
+
+ pinctrl_usb_default: usb_default {
+ pinmux = <PIN_PB12__GPIO>;
+ bias-disable;
+ };
+
+ pinctrl_usba_vbus: usba_vbus {
+ pinmux = <PIN_PB11__GPIO>;
+ bias-disable;
+ };
+ };
+ };
+ };
+ };
+};
#clock-cells = <0>;
reg = <24>;
atmel,clk-output-range = <0 83000000>;
+ u-boot,dm-pre-reloc;
};
uart1_clk: uart1_clk@25 {
#clock-cells = <0>;
reg = <26>;
atmel,clk-output-range = <0 83000000>;
+ u-boot,dm-pre-reloc;
};
uart3_clk: uart3_clk@27 {
status = "disabled";
};
+ uart0: serial@f801c000 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0xf801c000 0x100>;
+ clocks = <&uart0_clk>;
+ clock-names = "usart";
+ status = "disabled";
+ };
+
uart1: serial@f8020000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xf8020000 0x100>;
status = "disabled";
};
+ uart2: serial@f8024000 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0xf8024000 0x100>;
+ clocks = <&uart2_clk>;
+ clock-names = "usart";
+ status = "disabled";
+ };
+
i2c0: i2c@f8028000 {
compatible = "atmel,sama5d2-i2c";
reg = <0xf8028000 0x100>;
select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
-config TARGET_SAMA5D2_PTC
- bool "SAMA5D2 PTC board"
+config TARGET_SAMA5D2_PTC_EK
+ bool "SAMA5D2 PTC EK board"
select SAMA5D2
- select SUPPORT_SPL
select BOARD_EARLY_INIT_F
config TARGET_SAMA5D2_XPLAINED
source "board/atmel/at91sam9n12ek/Kconfig"
source "board/atmel/at91sam9rlek/Kconfig"
source "board/atmel/at91sam9x5ek/Kconfig"
-source "board/atmel/sama5d2_ptc/Kconfig"
+source "board/atmel/sama5d2_ptc_ek/Kconfig"
source "board/atmel/sama5d2_xplained/Kconfig"
source "board/atmel/sama5d27_som1_ek/Kconfig"
source "board/atmel/sama5d3_xplained/Kconfig"
+++ /dev/null
-if TARGET_SAMA5D2_PTC
-
-config SYS_BOARD
- default "sama5d2_ptc"
-
-config SYS_VENDOR
- default "atmel"
-
-config SYS_SOC
- default "at91"
-
-config SYS_CONFIG_NAME
- default "sama5d2_ptc"
-
-endif
+++ /dev/null
-SAMA5D2 PTC Engineering BOARD
-M: Wenyou Yang <wenyou.yang@atmel.com>
-S: Maintained
-F: board/atmel/sama5d2_ptc/
-F: include/configs/sama5d2_ptc.h
-F: configs/sama5d2_ptc_spiflash_defconfig
-F: configs/sama5d2_ptc_nandflash_defconfig
+++ /dev/null
-#
-# Copyright (C) 2016 Atmel
-# Wenyou Yang <wenyou.yang@atmel.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += sama5d2_ptc.o
+++ /dev/null
-/*
- * Copyright (C) 2016 Atmel
- * Wenyou.Yang <wenyou.yang@atmel.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <atmel_hlcdc.h>
-#include <lcd.h>
-#include <mmc.h>
-#include <net.h>
-#include <netdev.h>
-#include <spi.h>
-#include <version.h>
-#include <asm/io.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/atmel_pio4.h>
-#include <asm/arch/atmel_mpddrc.h>
-#include <asm/arch/atmel_usba_udc.h>
-#include <asm/arch/atmel_sdhci.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/sama5_sfr.h>
-#include <asm/arch/sama5d2.h>
-#include <asm/arch/sama5d3_smc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
- return bus == 0 && cs == 0;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
- atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 0);
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
- atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 1);
-}
-
-static void board_spi0_hw_init(void)
-{
- atmel_pio4_set_a_periph(AT91_PIO_PORTA, 14, 0);
- atmel_pio4_set_a_periph(AT91_PIO_PORTA, 15, 0);
- atmel_pio4_set_a_periph(AT91_PIO_PORTA, 16, 0);
-
- atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 1);
-
- at91_periph_clk_enable(ATMEL_ID_SPI0);
-}
-
-static void board_nand_hw_init(void)
-{
- struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
- struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR;
-
- at91_periph_clk_enable(ATMEL_ID_HSMC);
-
- writel(AT91_SFR_EBICFG_DRIVE0_HIGH |
- AT91_SFR_EBICFG_PULL0_NONE |
- AT91_SFR_EBICFG_DRIVE1_HIGH |
- AT91_SFR_EBICFG_PULL1_NONE, &sfr->ebicfg);
-
- /* Configure SMC CS3 for NAND */
- writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
- AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
- &smc->cs[3].setup);
- writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) |
- AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3),
- &smc->cs[3].pulse);
- writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
- &smc->cs[3].cycle);
- writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) |
- AT91_SMC_TIMINGS_TAR(2) | AT91_SMC_TIMINGS_TRR(3) |
- AT91_SMC_TIMINGS_TWB(7) | AT91_SMC_TIMINGS_RBNSEL(3) |
- AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
- writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
- AT91_SMC_MODE_EXNW_DISABLE |
- AT91_SMC_MODE_DBW_8 |
- AT91_SMC_MODE_TDF_CYCLE(3),
- &smc->cs[3].mode);
-
- atmel_pio4_set_f_periph(AT91_PIO_PORTA, 0, 0); /* D0 */
- atmel_pio4_set_f_periph(AT91_PIO_PORTA, 1, 0); /* D1 */
- atmel_pio4_set_f_periph(AT91_PIO_PORTA, 2, 0); /* D2 */
- atmel_pio4_set_f_periph(AT91_PIO_PORTA, 3, 0); /* D3 */
- atmel_pio4_set_f_periph(AT91_PIO_PORTA, 4, 0); /* D4 */
- atmel_pio4_set_f_periph(AT91_PIO_PORTA, 5, 0); /* D5 */
- atmel_pio4_set_f_periph(AT91_PIO_PORTA, 6, 0); /* D6 */
- atmel_pio4_set_f_periph(AT91_PIO_PORTA, 7, 0); /* D7 */
- atmel_pio4_set_f_periph(AT91_PIO_PORTA, 12, 0); /* RE */
- atmel_pio4_set_f_periph(AT91_PIO_PORTA, 8, 0); /* WE */
- atmel_pio4_set_f_periph(AT91_PIO_PORTA, 9, 1); /* NCS */
- atmel_pio4_set_f_periph(AT91_PIO_PORTA, 21, 1); /* RDY */
- atmel_pio4_set_f_periph(AT91_PIO_PORTA, 10, 1); /* ALE */
- atmel_pio4_set_f_periph(AT91_PIO_PORTA, 11, 1); /* CLE */
-}
-
-static void board_usb_hw_init(void)
-{
- atmel_pio4_set_pio_output(AT91_PIO_PORTA, 28, 1);
-}
-
-static void board_gmac_hw_init(void)
-{
- atmel_pio4_set_f_periph(AT91_PIO_PORTB, 14, 0); /* GTXCK */
- atmel_pio4_set_f_periph(AT91_PIO_PORTB, 15, 0); /* GTXEN */
- atmel_pio4_set_f_periph(AT91_PIO_PORTB, 16, 0); /* GRXDV */
- atmel_pio4_set_f_periph(AT91_PIO_PORTB, 17, 0); /* GRXER */
- atmel_pio4_set_f_periph(AT91_PIO_PORTB, 18, 0); /* GRX0 */
- atmel_pio4_set_f_periph(AT91_PIO_PORTB, 19, 0); /* GRX1 */
- atmel_pio4_set_f_periph(AT91_PIO_PORTB, 20, 0); /* GTX0 */
- atmel_pio4_set_f_periph(AT91_PIO_PORTB, 21, 0); /* GTX1 */
- atmel_pio4_set_f_periph(AT91_PIO_PORTB, 22, 0); /* GMDC */
- atmel_pio4_set_f_periph(AT91_PIO_PORTB, 23, 0); /* GMDIO */
-
- at91_periph_clk_enable(ATMEL_ID_GMAC);
-}
-
-static void board_uart0_hw_init(void)
-{
- atmel_pio4_set_c_periph(AT91_PIO_PORTB, 26, 1); /* URXD0 */
- atmel_pio4_set_c_periph(AT91_PIO_PORTB, 27, 0); /* UTXD0 */
-
- at91_periph_clk_enable(CONFIG_USART_ID);
-}
-
-int board_early_init_f(void)
-{
- at91_periph_clk_enable(ATMEL_ID_PIOA);
- at91_periph_clk_enable(ATMEL_ID_PIOB);
- at91_periph_clk_enable(ATMEL_ID_PIOC);
- at91_periph_clk_enable(ATMEL_ID_PIOD);
-
- board_uart0_hw_init();
-
- return 0;
-}
-
-int board_init(void)
-{
- /* address of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
-#ifdef CONFIG_ATMEL_SPI
- board_spi0_hw_init();
-#endif
-#ifdef CONFIG_NAND_ATMEL
- board_nand_hw_init();
-#endif
-#ifdef CONFIG_MACB
- board_gmac_hw_init();
-#endif
-#ifdef CONFIG_CMD_USB
- board_usb_hw_init();
-#endif
-#ifdef CONFIG_USB_GADGET_ATMEL_USBA
- at91_udp_hw_init();
-#endif
-
- return 0;
-}
-
-int dram_init(void)
-{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
- return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-
-#ifdef CONFIG_MACB
- rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00);
- if (rc)
- printf("GMAC register failed\n");
-#endif
-
-#ifdef CONFIG_USB_GADGET_ATMEL_USBA
- usba_udc_probe(&pdata);
-#ifdef CONFIG_USB_ETH_RNDIS
- usb_eth_initialize(bis);
-#endif
-#endif
-
- return rc;
-}
-
-/* SPL */
-#ifdef CONFIG_SPL_BUILD
-void spl_board_init(void)
-{
-#ifdef CONFIG_SPI_BOOT
- board_spi0_hw_init();
-#endif
-
-#ifdef CONFIG_NAND_BOOT
- board_nand_hw_init();
-#endif
-}
-
-static void ddrc_conf(struct atmel_mpddrc_config *ddrc)
-{
- ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR3_SDRAM);
-
- ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
- ATMEL_MPDDRC_CR_NR_ROW_14 |
- ATMEL_MPDDRC_CR_CAS_DDR_CAS5 |
- ATMEL_MPDDRC_CR_DIC_DS |
- ATMEL_MPDDRC_CR_DIS_DLL |
- ATMEL_MPDDRC_CR_NB_8BANKS |
- ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
- ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
-
- ddrc->rtr = 0x511;
-
- ddrc->tpr0 = ((6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) |
- (3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET) |
- (4 << ATMEL_MPDDRC_TPR0_TWR_OFFSET) |
- (9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET) |
- (3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET) |
- (4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET) |
- (4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET) |
- (4 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET));
-
- ddrc->tpr1 = ((27 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) |
- (29 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET) |
- (0 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET) |
- (3 << ATMEL_MPDDRC_TPR1_TXP_OFFSET));
-
- ddrc->tpr2 = ((0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) |
- (0 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET) |
- (0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET) |
- (4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET) |
- (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET));
-}
-
-void mem_init(void)
-{
- struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
- struct atmel_mpddrc_config ddrc_config;
- u32 reg;
-
- ddrc_conf(&ddrc_config);
-
- at91_periph_clk_enable(ATMEL_ID_MPDDRC);
- at91_system_clk_enable(AT91_PMC_DDR);
-
- reg = readl(&mpddrc->io_calibr);
- reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV;
- reg |= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55;
- reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO;
- reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(100);
- writel(reg, &mpddrc->io_calibr);
-
- writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_TWO_CYCLE,
- &mpddrc->rd_data_path);
-
- ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config);
-
- writel(0x3, &mpddrc->cal_mr4);
- writel(64, &mpddrc->tim_cal);
-}
-
-void at91_pmc_init(void)
-{
- at91_plla_init(AT91_PMC_PLLAR_29 |
- AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
- AT91_PMC_PLLXR_MUL(82) |
- AT91_PMC_PLLXR_DIV(1));
-
- at91_pllicpr_init(0);
-
- at91_mck_init(AT91_PMC_MCKR_H32MXDIV |
- AT91_PMC_MCKR_PLLADIV_2 |
- AT91_PMC_MCKR_MDIV_3 |
- AT91_PMC_MCKR_CSS_PLLA);
-}
-#endif
--- /dev/null
+if TARGET_SAMA5D2_PTC_EK
+
+config SYS_BOARD
+ default "sama5d2_ptc_ek"
+
+config SYS_VENDOR
+ default "atmel"
+
+config SYS_SOC
+ default "at91"
+
+config SYS_CONFIG_NAME
+ default "sama5d2_ptc_ek"
+
+endif
--- /dev/null
+SAMA5D2 PTC EK BOARD
+M: Wenyou Yang <wenyou.yang@microchip.com>
+M: Ludovic Desroches <ludovic.desroches@microchip.com>
+S: Maintained
+F: board/atmel/sama5d2_ptc_ek/
+F: include/configs/sama5d2_ptc_ek.h
+F: configs/sama5d2_ptc_ek_mmc_defconfig
+F: configs/sama5d2_ptc_ek_nandflash_defconfig
--- /dev/null
+#
+# Copyright (C) 2017 Microchip Corporation
+# Wenyou Yang <wenyou.yang@microchip.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += sama5d2_ptc_ek.o
--- /dev/null
+/*
+ * Copyright (C) 2017 Microchip Corporation
+ * Wenyou Yang <wenyou.yang@microchip.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+#include <dm.h>
+#include <i2c.h>
+#include <nand.h>
+#include <version.h>
+#include <asm/io.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/atmel_pio4.h>
+#include <asm/arch/atmel_mpddrc.h>
+#include <asm/arch/atmel_sdhci.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/sama5d2.h>
+#include <asm/arch/sama5d2_smc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_NAND_ATMEL
+static void board_nand_hw_init(void)
+{
+ struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+
+ at91_periph_clk_enable(ATMEL_ID_HSMC);
+
+ /* Configure SMC CS3 for NAND */
+ writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
+ AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
+ &smc->cs[3].setup);
+ writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) |
+ AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3),
+ &smc->cs[3].pulse);
+ writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+ &smc->cs[3].cycle);
+ writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) |
+ AT91_SMC_TIMINGS_TAR(2) | AT91_SMC_TIMINGS_TRR(3) |
+ AT91_SMC_TIMINGS_TWB(7) | AT91_SMC_TIMINGS_RBNSEL(3) |
+ AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_EXNW_DISABLE |
+ AT91_SMC_MODE_DBW_8 |
+ AT91_SMC_MODE_TDF_CYCLE(3),
+ &smc->cs[3].mode);
+
+ atmel_pio4_set_b_periph(AT91_PIO_PORTA, 22, 0); /* D0 */
+ atmel_pio4_set_b_periph(AT91_PIO_PORTA, 23, 0); /* D1 */
+ atmel_pio4_set_b_periph(AT91_PIO_PORTA, 24, 0); /* D2 */
+ atmel_pio4_set_b_periph(AT91_PIO_PORTA, 25, 0); /* D3 */
+ atmel_pio4_set_b_periph(AT91_PIO_PORTA, 26, 0); /* D4 */
+ atmel_pio4_set_b_periph(AT91_PIO_PORTA, 27, 0); /* D5 */
+ atmel_pio4_set_b_periph(AT91_PIO_PORTA, 28, 0); /* D6 */
+ atmel_pio4_set_b_periph(AT91_PIO_PORTA, 29, 0); /* D7 */
+ atmel_pio4_set_b_periph(AT91_PIO_PORTB, 2, 0); /* RE */
+ atmel_pio4_set_b_periph(AT91_PIO_PORTA, 30, 0); /* WE */
+ atmel_pio4_set_b_periph(AT91_PIO_PORTA, 31, 1); /* NCS */
+ atmel_pio4_set_b_periph(AT91_PIO_PORTC, 8, 1); /* RDY */
+ atmel_pio4_set_b_periph(AT91_PIO_PORTB, 0, 1); /* ALE */
+ atmel_pio4_set_b_periph(AT91_PIO_PORTB, 1, 1); /* CLE */
+}
+#endif
+
+static void board_usb_hw_init(void)
+{
+ atmel_pio4_set_pio_output(AT91_PIO_PORTB, 12, 1);
+}
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+static void board_uart0_hw_init(void)
+{
+ atmel_pio4_set_c_periph(AT91_PIO_PORTB, 26, 1); /* URXD0 */
+ atmel_pio4_set_c_periph(AT91_PIO_PORTB, 27, 0); /* UTXD0 */
+
+ at91_periph_clk_enable(ATMEL_ID_UART0);
+}
+
+void board_debug_uart_init(void)
+{
+ board_uart0_hw_init();
+}
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+#ifdef CONFIG_DEBUG_UART
+ debug_uart_init();
+#endif
+ return 0;
+}
+#endif
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_NAND_ATMEL
+ board_nand_hw_init();
+#endif
+#ifdef CONFIG_CMD_USB
+ board_usb_hw_init();
+#endif
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+ return 0;
+}
+
+#define AT24MAC_MAC_OFFSET 0xfa
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+#ifdef CONFIG_I2C_EEPROM
+ at91_set_ethaddr(AT24MAC_MAC_OFFSET);
+#endif
+ return 0;
+}
+#endif
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_SAMA5D2_PTC_EK=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_ptc_ek"
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_MMC"
+CONFIG_SD_BOOT=y
+CONFIG_BOOTDELAY=3
+CONFIG_CONSOLE_MUX=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_AT91_H32MX=y
+CONFIG_AT91_GENERIC_CLK=y
+CONFIG_DM_GPIO=y
+CONFIG_ATMEL_PIO4=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_AT91=y
+CONFIG_I2C_EEPROM=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ATMEL=y
+CONFIG_DM_ETH=y
+CONFIG_MACB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AT91PIO4=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART_ATMEL=y
+CONFIG_DEBUG_UART_BASE=0xf801c000
+CONFIG_DEBUG_UART_CLOCK=82000000
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ATMEL_USART=y
+CONFIG_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_SAMA5D2_PTC_EK=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_ptc_ek"
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_NANDFLASH"
+CONFIG_NAND_BOOT=y
+CONFIG_BOOTDELAY=3
+CONFIG_CONSOLE_MUX=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_AT91_H32MX=y
+CONFIG_AT91_GENERIC_CLK=y
+CONFIG_DM_GPIO=y
+CONFIG_ATMEL_PIO4=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_AT91=y
+CONFIG_I2C_EEPROM=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ATMEL=y
+CONFIG_DM_ETH=y
+CONFIG_MACB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AT91PIO4=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART_ATMEL=y
+CONFIG_DEBUG_UART_BASE=0xf801c000
+CONFIG_DEBUG_UART_CLOCK=82000000
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ATMEL_USART=y
+CONFIG_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_SAMA5D2_PTC=y
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_NAND_BOOT=y
-CONFIG_BOOTDELAY=3
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,57600 earlyprintk mtdparts=atmel_nand:6M(bootstrap)ro, 6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=2 root=ubi0:rootfs"
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_NAND=y
-CONFIG_CMD_NAND_TRIMFFS=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_NAND=y
-# CONFIG_MMC is not set
-CONFIG_SPI_FLASH=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Atmel SAMA5D2_PTC"
-CONFIG_USB_GADGET_ATMEL_USBA=y
-CONFIG_USB_ETHER=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_AT91=y
-CONFIG_TARGET_SAMA5D2_PTC=y
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_SPI_BOOT=y
-CONFIG_BOOTDELAY=3
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,57600 earlyprintk mtdparts=atmel_nand:6M(bootstrap)ro, 6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=2 root=ubi0:rootfs"
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_NAND=y
-CONFIG_CMD_NAND_TRIMFFS=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-# CONFIG_MMC is not set
-CONFIG_SPI_FLASH=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Atmel SAMA5D2_PTC"
-CONFIG_USB_GADGET_ATMEL_USBA=y
-CONFIG_USB_ETHER=y
+++ /dev/null
-/*
- * Configuration settings for the SAMA5D2 PTC Engineering board.
- *
- * Copyright (C) 2016 Atmel
- * Wenyou Yang <wenyou.yang@atmel.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include "at91-sama5_common.h"
-
-/* serial console */
-#define CONFIG_ATMEL_USART
-#define CONFIG_USART_BASE 0xf801c000
-#define CONFIG_USART_ID 24
-
-#define CONFIG_SYS_SDRAM_BASE 0x20000000
-#define CONFIG_SYS_SDRAM_SIZE 0x20000000
-
-#define CONFIG_SYS_TIMER_COUNTER 0xf804803c
-
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_INIT_SP_ADDR 0x210000
-#else
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
-#endif
-
-#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
-
-#undef CONFIG_AT91_GPIO
-#define CONFIG_ATMEL_PIO4
-
-/* SDRAM */
-#define CONFIG_NR_DRAM_BANKS 1
-
-/* SerialFlash */
-#ifdef CONFIG_CMD_SF
-#define CONFIG_ATMEL_SPI
-#define CONFIG_SPI_FLASH_ATMEL
-#define CONFIG_SF_DEFAULT_BUS 0
-#define CONFIG_SF_DEFAULT_CS 0
-#define CONFIG_SF_DEFAULT_SPEED 30000000
-#endif
-
-/* NAND flash */
-#ifdef CONFIG_CMD_NAND
-#define CONFIG_NAND_ATMEL
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE 0x80000000
-/* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
-/* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-/* PMECC & PMERRLOC */
-#define CONFIG_ATMEL_NAND_HWECC
-#define CONFIG_ATMEL_NAND_HW_PMECC
-#endif
-
-/* USB device */
-
-/* Ethernet Hardware */
-#define CONFIG_MACB
-#define CONFIG_RMII
-#define CONFIG_NET_RETRY_COUNT 20
-#define CONFIG_MACB_SEARCH_PHY
-
-#ifdef CONFIG_NAND_BOOT
-#undef CONFIG_ENV_OFFSET
-#undef CONFIG_ENV_OFFSET_REDUND
-#undef CONFIG_BOOTCOMMAND
-/* u-boot env in nand flash */
-#define CONFIG_ENV_OFFSET 0x200000
-#define CONFIG_ENV_OFFSET_REDUND 0x400000
-#define CONFIG_BOOTCOMMAND "nand read 0x21000000 0xb80000 0x80000;" \
- "nand read 0x22000000 0x600000 0x600000;" \
- "bootz 0x22000000 - 0x21000000"
-#endif
-
-/* SPL */
-#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_TEXT_BASE 0x200000
-#define CONFIG_SPL_MAX_SIZE 0x10000
-#define CONFIG_SPL_BSS_START_ADDR 0x20000000
-#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
-#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
-#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
-
-#define CONFIG_SYS_MONITOR_LEN (512 << 10)
-
-#ifdef CONFIG_SPI_BOOT
-#define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
-
-#elif CONFIG_NAND_BOOT
-#define CONFIG_SPL_NAND_DRIVERS
-#define CONFIG_SPL_NAND_BASE
-#endif
-#define CONFIG_PMECC_CAP 8
-#define CONFIG_PMECC_SECTOR_SIZE 512
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_SIZE 0x1000
-#define CONFIG_SYS_NAND_PAGE_COUNT 64
-#define CONFIG_SYS_NAND_OOBSIZE 224
-#define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
-#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
-
-#endif
--- /dev/null
+/*
+ * Configuration file for the SAMA5D2 PTC EK Board.
+ *
+ * Copyright (C) 2017 Microchip Technology Inc.
+ * Wenyou Yang <wenyou.yang@microchip.com>
+ * Ludovic Desroches <ludovic.desroches@microchip.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "at91-sama5_common.h"
+
+#undef CONFIG_SYS_AT91_MAIN_CLOCK
+#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */
+
+#define CONFIG_MISC_INIT_R
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SYS_SDRAM_BASE 0x20000000
+#define CONFIG_SYS_SDRAM_SIZE 0x20000000
+
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
+
+/* NAND Flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE BIT(21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE BIT(22)
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+/* PMECC & PMERRLOC */
+#define CONFIG_ATMEL_NAND_HWECC
+#define CONFIG_ATMEL_NAND_HW_PMECC
+#endif
+
+#endif /* __CONFIG_H */
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