mmc: i.MX6: fsl_esdhc: Define maximum bus width supported by a board

Maximum bus width supported by some i.MX6 boards is not 8bit like
others. In case where both host controller and card support 8bit transfers,
they agree to communicate on 8bit interface while some boards support only 4bit interface.
Due to this reason the mmc 8bit default mode fails on these boards. To rectify this,
define maximum bus width supported by these boards (4bit). If max_bus_width is not
defined, it is 0 by default and 8bit width support will be enabled in host
capabilities otherwise host capabilities are modified accordingly.

It is tested with a MMCplus card.

Signed-off-by: Abbas Raza <Abbas_Raza@mentor.com>
cc: stefano Babic <sbabic@denx.de>
cc: Andy Fleming <afleming@gmail.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Acked-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>

diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c
index 229c2378396d43a365d6682af35c0e519ccd69d4..e5b7795c5b1025d62edb23ca4c9ba1bf31f1bfbe 100644 (file)
--- a/board/boundary/nitrogen6x/nitrogen6x.c
+++ b/board/boundary/nitrogen6x/nitrogen6x.c
@@ -304,6 +304,9 @@ int board_mmc_init(bd_t *bis)
        usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
        usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 
+       usdhc_cfg[0].max_bus_width = 4;
+       usdhc_cfg[1].max_bus_width = 4;
+
        for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
                switch (index) {
                case 0:

diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
index 5b69a6d2decee87b2cab508db3c812a2681a2668..0e25613f19f27b168bd4264c0d1342ce590a3eb3 100644 (file)
--- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
+++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
@@ -274,6 +274,9 @@ int board_mmc_init(bd_t *bis)
        usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
        usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 
+       usdhc_cfg[0].max_bus_width = 4;
+       usdhc_cfg[1].max_bus_width = 4;
+
        for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
                switch (index) {
                case 0:

diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c
index d95189f77de4c3573ec30c53e04fe1b083c1d2b5..8d071e1fe12152ce0e708ab9d3fa0433b3be1867 100644 (file)
--- a/board/wandboard/wandboard.c
+++ b/board/wandboard/wandboard.c
@@ -105,6 +105,8 @@ int board_mmc_init(bd_t *bis)
        imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 
        usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+       usdhc_cfg[0].max_bus_width = 4;
+
        return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 }
 

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 54b5363169b5d10f9ac747ab75eef724422a28a0..35f879ea6e5f83d7715b02a6e0a934b11e1e21c9 100644 (file)
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -580,6 +580,13 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
 
        mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC;
 
+       if (cfg->max_bus_width > 0) {
+               if (cfg->max_bus_width < 8)
+                       mmc->host_caps &= ~MMC_MODE_8BIT;
+               if (cfg->max_bus_width < 4)
+                       mmc->host_caps &= ~MMC_MODE_4BIT;
+       }
+
        if (caps & ESDHC_HOSTCAPBLT_HSS)
                mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
 

diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
index 47d2fe4f188fa4a623c517ce5c01a84de6e7084b..0a1a0715e957d0d35286f9843dfcbfe957f6531f 100644 (file)
--- a/include/fsl_esdhc.h
+++ b/include/fsl_esdhc.h
@@ -168,6 +168,7 @@
 struct fsl_esdhc_cfg {
        u32     esdhc_base;
        u32     sdhc_clk;
+       u8      max_bus_width;
 };
 
 /* Select the correct accessors depending on endianess */