]> git.sur5r.net Git - u-boot/commitdiff
Move machine specific code to board at s3c64xx (v2)
authorKyungmin Park <kmpark@infradead.org>
Wed, 26 Nov 2008 01:18:13 +0000 (10:18 +0900)
committerJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Sat, 4 Apr 2009 22:30:38 +0000 (00:30 +0200)
Move machine specific code to smdk6400.
Some board use OneNAND instead of NAND.

Some register MP0_CS_CFG[5:0] are controled by both h/w and s/w.
So it's better to use macro instead of hard-coded value.

Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
board/samsung/smdk6400/lowlevel_init.S
cpu/arm1176/s3c64xx/cpu_init.S
include/s3c6400.h

index e0119a771c55c703b909789c2092d724b59cc585..47f72f6132efc0d835329beb8bc0524bd4bd098a 100644 (file)
@@ -104,6 +104,13 @@ lowlevel_init:
        bl nand_asm_init
 #endif
 
+       /* Memory subsystem address 0x7e00f120 */
+       ldr     r0, =ELFIN_MEM_SYS_CFG
+
+       /* Xm0CSn2 = NFCON CS0, Xm0CSn3 = NFCON CS1 */
+       mov     r1, #S3C64XX_MEM_SYS_CFG_NAND
+       str     r1, [r0]
+
        bl      mem_ctrl_asm_init
 
 /* Wakeup support. Don't know if it's going to be used, untested. */
index 08bda99fdc52e870fb54d3b0d83db3477a7ef2fd..32bb467f2f64c6b7e216b5bcc65b92b60acbd397 100644 (file)
 
        .globl mem_ctrl_asm_init
 mem_ctrl_asm_init:
-       /* Memory subsystem address 0x7e00f120 */
-       ldr     r0, =ELFIN_MEM_SYS_CFG
-
-       /* Xm0CSn2 = NFCON CS0, Xm0CSn3 = NFCON CS1 */
-       mov     r1, #0xd
-       str     r1, [r0]
-
        /* DMC1 base address 0x7e001000 */
        ldr     r0, =ELFIN_DMC1_BASE
 
index fd3e99bcfa21633306be0e15fb8af26a3af2f5b6..d3f136d91f0dc1ed0f8359345b03c02ca9ad799f 100644 (file)
  */
 #define ELFIN_MEM_SYS_CFG      0x7e00f120
 
+#define S3C64XX_MEM_SYS_CFG_16BIT      (1 << 12)
+
+#define S3C64XX_MEM_SYS_CFG_NAND       0x0008
+#define S3C64XX_MEM_SYS_CFG_ONENAND    S3C64XX_MEM_SYS_CFG_16BIT
+
 #define GPACON         (ELFIN_GPIO_BASE + GPACON_OFFSET)
 #define GPADAT         (ELFIN_GPIO_BASE + GPADAT_OFFSET)
 #define GPAPUD         (ELFIN_GPIO_BASE + GPAPUD_OFFSET)