imx: dma: correct MXS_DMA_ALIGNMENT

We should not hardcode MXS_DMA_ALIGNMENT to 32, since we can not guarantee
that socs' cache line size is 32 bytes.
If on chips whose cache line size is 64 bytes, error occurs:
"
NAND:  ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0
ERROR: v7_dcache_inval_range - stop address is not aligned - 0xbdf1f4a0
ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0
"
Align MXS_DMA_ALIGNMENT with ARCH_DMA_MINALIGN whose value is same to
CONFIG_SYS_CACHELINE_SIZE if CONFIG_SYS_CACHELINE_SIZE defined.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>

diff --git a/arch/arm/include/asm/imx-common/dma.h b/arch/arm/include/asm/imx-common/dma.h
index d5c1f7f255a3c5f6eee70634d6dd747ac5639530..7d421b3967cfb8295abfa4cb84d8f0d048879a5f 100644 (file)
--- a/arch/arm/include/asm/imx-common/dma.h
+++ b/arch/arm/include/asm/imx-common/dma.h
@@ -22,7 +22,7 @@
 #define        DMA_PIO_WORDS           CONFIG_ARCH_DMA_PIO_WORDS
 #endif
 
-#define MXS_DMA_ALIGNMENT      32
+#define MXS_DMA_ALIGNMENT      ARCH_DMA_MINALIGN
 
 /*
  * MXS DMA channels