]> git.sur5r.net Git - u-boot/commitdiff
powerpc/t1024qds: Add T1024 QDS board support
authorShengzhou Liu <Shengzhou.Liu@freescale.com>
Mon, 24 Nov 2014 09:11:55 +0000 (17:11 +0800)
committerYork Sun <yorksun@freescale.com>
Fri, 5 Dec 2014 16:06:15 +0000 (08:06 -0800)
T1024QDS is a high-performance computing evaluation, development and
test platform for T1024 QorIQ Power Architecture processor.

T1024QDS board Overview
-----------------------
- T1024 SoC integrating two 64-bit e5500 cores up to 1.4GHz
- CoreNet fabric supporting coherent and noncoherent transactions with
  prioritization and bandwidth allocation
- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support
- Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC
- Ethernet interfaces:
  - Two 10M/100M/1G RGMII ports on-board
  - Three 1G/2.5Gbps SGMII ports
  - Four 1Gbps QSGMII ports
  - one 10Gbps XFI or 10Base-KR interface
- SerDes: 4 lanes up to 10.3125GHz Supporting SGMII/QSGMII, XFI, PCIe, SATA and Aurora
- PCIe: Three PCI Express controllers with five PCIe slots.
- IFC: 128MB NOR Flash, 2GB NAND Flash, PromJet debug port and Qixis FPGA
- Video: DIU supports video up to 1280x1024x32 bpp.
  - Chrontel CH7201 for HDMI connection.
  - TI DS90C387R for direct LCD connection.
  - Raw (not encoded) video connector for testing or other encoders.
- QUICC Engine block
  - 32-bit RISC controller for flexible support of the communications peripherals
  - Serial DMA channel for receive and transmit on all serial channels
  - Two universal communication controllers, supporting TDM, HDLC, and UART
- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
- eSPI: Three SPI flash devices.
- SATA: one SATA 2.O.
- USB: Two USB2.0 ports with internal PHY (one Type-A + one micro Type mini-AB)
- eSDHC: Support SD, SDHC, SDXC and MMC/eMMC.
- I2C: Four I2C controllers.
- UART: Two UART on board.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
[York Sun: Fix ft_board_setup() type, fix MAINTAINERS for SECURE_BOOT
   Fix Kconfig by adding SUPPORT_SPL]
Reviewed-by: York Sun <yorksun@freescale.com>
22 files changed:
arch/powerpc/cpu/mpc85xx/Kconfig
board/freescale/t102xqds/Kconfig [new file with mode: 0644]
board/freescale/t102xqds/MAINTAINERS [new file with mode: 0644]
board/freescale/t102xqds/Makefile [new file with mode: 0644]
board/freescale/t102xqds/README [new file with mode: 0644]
board/freescale/t102xqds/ddr.c [new file with mode: 0644]
board/freescale/t102xqds/eth_t102xqds.c [new file with mode: 0644]
board/freescale/t102xqds/law.c [new file with mode: 0644]
board/freescale/t102xqds/pci.c [new file with mode: 0644]
board/freescale/t102xqds/spl.c [new file with mode: 0644]
board/freescale/t102xqds/t1024_pbi.cfg [new file with mode: 0644]
board/freescale/t102xqds/t1024_rcw.cfg [new file with mode: 0644]
board/freescale/t102xqds/t102xqds.c [new file with mode: 0644]
board/freescale/t102xqds/t102xqds.h [new file with mode: 0644]
board/freescale/t102xqds/t102xqds_qixis.h [new file with mode: 0644]
board/freescale/t102xqds/tlb.c [new file with mode: 0644]
configs/T1024QDS_D4_SECURE_BOOT_defconfig [new file with mode: 0644]
configs/T1024QDS_NAND_defconfig [new file with mode: 0644]
configs/T1024QDS_SDCARD_defconfig [new file with mode: 0644]
configs/T1024QDS_SECURE_BOOT_defconfig [new file with mode: 0644]
configs/T1024QDS_SPIFLASH_defconfig [new file with mode: 0644]
include/configs/T102xQDS.h [new file with mode: 0644]

index 7b42d06952c4116c09177aea508384e247171308..693e513998f407276c20eff9790accbd07ab1c18 100644 (file)
@@ -110,6 +110,10 @@ config TARGET_P2041RDB
 config TARGET_QEMU_PPCE500
        bool "Support qemu-ppce500"
 
+config TARGET_T102XQDS
+       bool "Support T102xQDS"
+       select SUPPORT_SPL
+
 config TARGET_T1040QDS
        bool "Support T1040QDS"
 
@@ -183,6 +187,7 @@ source "board/freescale/p2020come/Kconfig"
 source "board/freescale/p2020ds/Kconfig"
 source "board/freescale/p2041rdb/Kconfig"
 source "board/freescale/qemu-ppce500/Kconfig"
+source "board/freescale/t102xqds/Kconfig"
 source "board/freescale/t1040qds/Kconfig"
 source "board/freescale/t104xrdb/Kconfig"
 source "board/freescale/t208xqds/Kconfig"
diff --git a/board/freescale/t102xqds/Kconfig b/board/freescale/t102xqds/Kconfig
new file mode 100644 (file)
index 0000000..4d17798
--- /dev/null
@@ -0,0 +1,12 @@
+if TARGET_T102XQDS
+
+config SYS_BOARD
+       default "t102xqds"
+
+config SYS_VENDOR
+       default "freescale"
+
+config SYS_CONFIG_NAME
+       default "T102xQDS"
+
+endif
diff --git a/board/freescale/t102xqds/MAINTAINERS b/board/freescale/t102xqds/MAINTAINERS
new file mode 100644 (file)
index 0000000..1ffccc4
--- /dev/null
@@ -0,0 +1,12 @@
+T102XQDS BOARD
+M:     Shengzhou Liu  <Shengzhou.Liu@freescale.com>
+S:     Maintained
+F:     board/freescale/t102xqds/
+F:     include/configs/T102xQDS.h
+F:     configs/T1024QDS_defconfig
+F:     configs/T1024QDS_NAND_defconfig
+F:     configs/T1024QDS_SDCARD_defconfig
+F:     configs/T1024QDS_SPIFLASH_defconfig
+F:     configs/T1024QDS_D4_defconfig
+F:     configs/T1024QDS_SECURE_BOOT_defconfig
+F:     configs/T1024QDS_D4_SECURE_BOOT_defconfig
diff --git a/board/freescale/t102xqds/Makefile b/board/freescale/t102xqds/Makefile
new file mode 100644 (file)
index 0000000..d94f230
--- /dev/null
@@ -0,0 +1,17 @@
+#
+# Copyright 2014 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+else
+obj-y  += t102xqds.o
+obj-y  += eth_t102xqds.o
+obj-$(CONFIG_PCI) += pci.o
+obj-$(CONFIG_FSL_DIU_FB) += ../t1040qds/diu.o
+endif
+obj-y   += ddr.o
+obj-y   += law.o
+obj-y   += tlb.o
diff --git a/board/freescale/t102xqds/README b/board/freescale/t102xqds/README
new file mode 100644 (file)
index 0000000..bb0f280
--- /dev/null
@@ -0,0 +1,328 @@
+T1024 SoC Overview
+------------------
+The T1024/T1023 dual core and T1014/T1013 single core QorIQ communication processor
+combines two or one 64-bit Power Architecture e5500 core respectively with high
+performance datapath acceleration logic, and network peripheral bus interfaces
+required for networking and telecommunications. This processor can be used in
+applications such as enterprise WLAN access points, routers, switches, firewall
+and other packet processing intensive small enterprise and branch office appliances,
+and general-purpose embedded computing. Its high level of integration offers
+significant performance benefits and greatly helps to simplify board design.
+
+
+The T1024 SoC includes the following function and features:
+- two e5500 cores, each with a private 256 KB L2 cache
+  - Up to 1.4 GHz with 64-bit ISA support (Power Architecture v2.06-compliant)
+  - Three levels of instructions: User, supervisor, and hypervisor
+  - Independent boot and reset
+  - Secure boot capability
+- 256 KB shared L3 CoreNet platform cache (CPC)
+- Interconnect CoreNet platform
+  - CoreNet coherency manager supporting coherent and noncoherent transactions
+    with prioritization and bandwidth allocation amongst CoreNet endpoints
+  - 150 Gbps coherent read bandwidth
+- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support
+- Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions:
+  - Packet parsing, classification, and distribution
+  - Queue management for scheduling, packet sequencing, and congestion management
+  - Cryptography Acceleration (SEC 5.x)
+  - IEEE 1588 support
+  - Hardware buffer management for buffer allocation and deallocation
+  - MACSEC on DPAA-based Ethernet ports
+- Ethernet interfaces
+  - Four 1 Gbps Ethernet controllers
+- Parallel Ethernet interfaces
+  - Two RGMII interfaces
+- High speed peripheral interfaces
+  - Three PCI Express 2.0 controllers/ports running at up to 5 GHz
+  - One SATA controller supporting 1.5 and 3.0 Gb/s operation
+  - One QSGMII interface
+  - Four SGMII interface supporting 1000 Mbps
+  - Three SGMII interfaces supporting up to 2500 Mbps
+  - 10GbE XFI or 10Base-KR interface
+- Additional peripheral interfaces
+  - Two USB 2.0 controllers with integrated PHY
+  - SD/eSDHC/eMMC
+  - eSPI controller
+  - Four I2C controllers
+  - Four UARTs
+  - Four GPIO controllers
+  - Integrated flash controller (IFC)
+  - LCD interface (DIU) with 12 bit dual data rate
+- Multicore programmable interrupt controller (PIC)
+- Two 8-channel DMA engines
+- Single source clocking implementation
+- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
+- QUICC Engine block
+  - 32-bit RISC controller for flexible support of the communications peripherals
+  - Serial DMA channel for receive and transmit on all serial channels
+  - Two universal communication controllers, supporting TDM, HDLC, and UART
+
+T1023 Personality
+------------------
+T1023 is a reduced personality of T1024 without QUICC Engine, DIU, and
+unavailable deep sleep. Rest of the blocks are almost same as T1024.
+Differences between T1024 and T1023
+Feature                T1024  T1023
+QUICC Engine:  yes    no
+DIU:           yes    no
+Deep Sleep:    yes    no
+I2C controller: 4      3
+DDR:           64-bit 32-bit
+IFC:           32-bit 28-bit
+
+
+T1024QDS board Overview
+-----------------------
+- SERDES Connections
+  4 lanes supporting the following:
+  - PCI Express: supports Gen 1 and Gen 2
+  - SGMII 1G and SGMII 2.5G
+  - QSGMII
+  - XFI
+  - SATA 2.0
+  - High-speed multiplexers route the SerDes traffic to appropriate slots or connectors.
+  - Aurora debug with dedicated connectors.
+- DDR Controller
+  - Supports up to 1600 MTPS data-rate.
+  - Supports one DDR4 or DDR3L module using DDR4 to DDR3L adapter card.
+    - Supports Single-, dual- or quad-rank DIMMs
+  - DDR power supplies 1.35V (DDR3L)/1.20V (DDR4) to all devices with automatic tracking of VTT.
+- IFC/Local Bus
+  - NAND Flash: 8-bit, async, up to 2GB
+  - NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB
+    - NOR devices support 8 virtual banks
+    - Socketed to allow alternate devices
+  - GASIC: Simple (minimal) target within QIXIS FPGA
+  - PromJET rapid memory download support
+  - IFC Debug/Development card
+- Ethernet
+  - Two on-board RGMII 10M/100M/1G ethernet ports.
+  - One QSGMII interface
+  - Four SGMII interface supporting 1Gbps
+  - Three SGMII interfaces supporting 2.5Gbps
+  - one 10Gbps XFI or 10Base-KR interface
+- QIXIS System Logic FPGA
+  - Manages system power and reset sequencing.
+  - Manages the configurations of DUT, board, and clock for dynamic shmoo.
+  - Collects V-I-T data in background for code/power profiling.
+  - Supports legacy TMT test features (POSt, IRS, SYSCLK-synchronous assertion).
+  - General fault monitoring and logging.
+  - Powered from ATX 'standby' power supply that allows continuous operation while rest of the system is off.
+- Clocks
+  - System and DDR clock (SYSCLK, DDRCLK).
+    - Switch selectable to one of 16 common settings in the interval of 64 MHz-166 MHz.
+    - Software programmable in 1 MHz increments from 1-200 MHz.
+  - SERDES clocks
+    - Provides clocks to SerDes blocks and slots.
+    - 100 MHz, 125 MHz and 156.25 MHz options.
+    - Spread-spectrum option for 100 MHz.
+- Power Supplies
+  - Dedicated PMBus regulator for VDD and VDDC.
+  - Adjustable from 0.7V to 1.3V at 35A
+    - VDD can be disabled independanty from VDDC for “deep sleep”.
+    - DDR3L/DDR4 power supply for GVDD: 1.35 or 1.20V at up to 22A.
+    - VTT/MVREF automatically track operating voltage.
+    - Dedicated 2.5V VPP supply.
+  - Dedicated regulators/filters for AVDD supplies.
+  - Dedicated regulators for other supplies, for example OVDD, CVDD, DVDD, LVDD, POVDD, and EVDD.
+- Video
+  - DIU supports video up to 1280x1024x32 bpp.
+    - Chrontel CH7201 for HDMI connection.
+    - TI DS90C387R for direct LCD connection.
+    - Raw (not encoded) video connector for testing or other encoders.
+- USB
+  - Supports two USB 2.0 ports with integrated PHYs.
+    - Two type A ports with 5V@1.5A per port.
+    - Second port can be converted to OTG mini-AB.
+- SDHC
+  For T1024QDS, the SDHC port connects directly to an adapter card slot that has the following features:
+    - upport for optional clock feedback paths.
+    - Support for optional high-speed voltage translation direction controls.
+    - Support for SD slots for: SD, SDHC (1x, 4x, 8x) and MMC.
+    - Support for eMMC memory devices.
+- SPI
+  -On-board support of 3 different devices and sizes.
+- Other IO
+  - Two Serial ports
+  - ProfiBus port
+  - Four I2C ports
+
+
+Memory map on T1024QDS
+----------------------
+Start Address  End Address      Description                    Size
+0xF_FFDF_0000  0xF_FFDF_0FFF    IFC - FPGA                     4KB
+0xF_FF80_0000  0xF_FF80_FFFF    IFC - NAND Flash               64KB
+0xF_FE00_0000  0xF_FEFF_FFFF    CCSRBAR                                16MB
+0xF_F802_0000  0xF_F802_FFFF    PCI Express 3 I/O Space                64KB
+0xF_F801_0000  0xF_F801_FFFF    PCI Express 2 I/O Space                64KB
+0xF_F800_0000  0xF_F800_FFFF    PCI Express 1 I/O Space                64KB
+0xF_F600_0000  0xF_F7FF_FFFF    Queue manager software portal   32MB
+0xF_F400_0000  0xF_F5FF_FFFF    Buffer manager software portal  32MB
+0xF_E800_0000  0xF_EFFF_FFFF    IFC - NOR Flash                        128MB
+0xF_E000_0000  0xF_E7FF_FFFF    Promjet                                128MB
+0xF_0000_0000  0xF_003F_FFFF    DCSR                           4MB
+0xC_2000_0000  0xC_2FFF_FFFF    PCI Express 3 Mem Space                256MB
+0xC_1000_0000  0xC_1FFF_FFFF    PCI Express 2 Mem Space                256MB
+0xC_0000_0000  0xC_0FFF_FFFF    PCI Express 1 Mem Space                256MB
+0x0_0000_0000  0x0_ffff_ffff    DDR                            4GB
+
+
+128MB NOR Flash memory Map
+--------------------------
+Start Address   End Address     Definition                     Max size
+0xEFF40000      0xEFFFFFFF      u-boot (current bank)          768KB
+0xEFF20000      0xEFF3FFFF      u-boot env (current bank)      128KB
+0xEFF00000      0xEFF1FFFF      FMAN Ucode (current bank)      128KB
+0xEFE00000      0xEFE3FFFF      QE firmware (current bank)     256KB
+0xED300000      0xEFEFFFFF      rootfs (alt bank)              44MB
+0xEC800000      0xEC8FFFFF      Hardware device tree (alt bank) 1MB
+0xEC020000      0xEC7FFFFF      Linux.uImage (alt bank)                7MB + 875KB
+0xEC000000      0xEC01FFFF      RCW (alt bank)                 128KB
+0xEBF40000      0xEBFFFFFF      u-boot (alt bank)              768KB
+0xEBF20000      0xEBF3FFFF      u-boot env (alt bank)          128KB
+0xEBF00000      0xEBF1FFFF      FMAN ucode (alt bank)          128KB
+0xEBE00000      0xEBE3FFFF      QE firmware (alt bank)         256KB
+0xE9300000      0xEBEFFFFF      rootfs (current bank)          44MB
+0xE8800000      0xE88FFFFF      Hardware device tree (cur bank) 1MB
+0xE8020000      0xE86FFFFF      Linux.uImage (current bank)    7MB + 875KB
+0xE8000000      0xE801FFFF      RCW (current bank)             128KB
+
+
+SerDes clock vs DIP-switch settings
+-----------------------------------
+SRDS_PRTCL_S1  SD1_REF_CLK1    SD1_REF_CLK2    SW4[1:4]
+0x6F           100MHz          125MHz          1101
+0xD6           100MHz          100MHz          1111
+0x99           156.25MHz       100MHz          1011
+
+
+T1024 Clock frequency
+----------------------
+BIN   Core     DDR       Platform  FMan
+Bin1: 1400MHz  1600MT/s  400MHz    700MHz
+Bin2: 1200MHz  1600MT/s  400MHz    600MHz
+Bin3: 1000MHz  1600MT/s  400MHz    500MHz
+
+
+
+Software configurations and board settings
+------------------------------------------
+1. NOR boot:
+   a. build NOR boot image
+       $  make T1024QDS_defconfig    (For DDR3L, by default)
+       or make T1024QDS_D4_defconfig (For DDR4)
+       $  make
+   b. program u-boot.bin image to NOR flash
+       => tftp 1000000 u-boot.bin
+       => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
+       set SW1[1:8] = '00010011', SW2[1] = '1', SW6[1:4] = '0000' for NOR boot
+
+   Switching between default bank0 and alternate bank4 on NOR flash
+   To change boot source to vbank4:
+       via software:   run command 'qixis_reset altbank' in u-boot.
+       via DIP-switch: set SW6[1:4] = '0100'
+
+   To change boot source to vbank0:
+       via software:   run command 'qixis_reset' in u-boot.
+       via DIP-Switch: set SW6[1:4] = '0000'
+
+2. NAND Boot:
+   a. build PBL image for NAND boot
+       $ make T1024QDS_NAND_defconfig
+       $ make
+   b. program u-boot-with-spl-pbl.bin to NAND flash
+       => tftp 1000000 u-boot-with-spl-pbl.bin
+       => nand erase 0 $filesize
+       => nand write 1000000 0 $filesize
+       set SW1[1:8] = '10000010', SW2[1] = '0' and SW6[1:4] = '1001' for NAND boot
+
+3. SPI Boot:
+   a. build PBL image for SPI boot
+       $ make T1024QDS_SPIFLASH_defconfig
+       $ make
+   b. program u-boot-with-spl-pbl.bin to SPI flash
+       => tftp 1000000 u-boot-with-spl-pbl.bin
+       => sf probe 0
+       => sf erase 0 f0000
+       => sf write 1000000 0 $filesize
+       set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot
+
+4. SD Boot:
+   a. build PBL image for SD boot
+       $ make T1024QDS_SDCARD_defconfig
+       $ make
+   b. program u-boot-with-spl-pbl.bin to SD/MMC card
+       => tftp 1000000 u-boot-with-spl-pbl.bin
+       => mmc write 1000000 8 0x800
+       => tftp 1000000 fsl_fman_ucode_t1024_xx.bin
+       => mmc write 1000000 0x820 80
+       set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
+
+
+DIU/QE-TDM/SDXC settings
+-------------------
+a) For TDM Riser:     set pin_mux=tdm in hwconfig
+b) For UCC(ProfiBus): set pin_mux=ucc in hwconfig
+c) For HDMI(DVI):     set pin_mux=hdmi in hwconfig
+d) For LCD(DFP):      set pin_mux=lcd in hwconfig
+e) For SDXC:         set adaptor=sdxc in hwconfig
+
+2-stage NAND/SPI/SD boot loader
+-------------------------------
+PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM.
+SPL further initializes DDR using SPD and environment variables
+and copy u-boot(768 KB) from NAND/SPI/SD device to DDR.
+Finally SPL transers control to u-boot for futher booting.
+
+SPL has following features:
+ - Executes within 256K
+ - No relocation required
+
+Run time view of SPL framework
+-------------------------------------------------
+|Area             | Address                    |
+-------------------------------------------------
+|SecureBoot header | 0xFFFC0000 (32KB)         |
+-------------------------------------------------
+|GD, BD                   | 0xFFFC8000 (4KB)           |
+-------------------------------------------------
+|ENV              | 0xFFFC9000 (8KB)           |
+-------------------------------------------------
+|HEAP             | 0xFFFCB000 (30KB)          |
+-------------------------------------------------
+|STACK            | 0xFFFD8000 (22KB)          |
+-------------------------------------------------
+|U-boot SPL       | 0xFFFD8000 (160KB)         |
+-------------------------------------------------
+
+NAND Flash memory Map on T1024QDS
+-------------------------------------------------------------
+Start          End             Definition      Size
+0x000000       0x0FFFFF        u-boot          1MB
+0x100000       0x15FFFF        u-boot env      8KB
+0x160000       0x17FFFF        FMAN Ucode      128KB
+0x180000       0x19FFFF        QE Firmware     128KB
+
+
+SD Card memory Map on T1024QDS
+----------------------------------------------------
+Block          #blocks         Definition      Size
+0x008          2048            u-boot img      1MB
+0x800          0016            u-boot env      8KB
+0x820          0256            FMAN Ucode      128KB
+0x920          0256            QE Firmware     128KB
+
+
+SPI Flash memory Map on T1024QDS
+----------------------------------------------------
+Start          End             Definition      Size
+0x000000       0x0FFFFF        u-boot img      1MB
+0x100000       0x101FFF        u-boot env      8KB
+0x110000       0x12FFFF        FMAN Ucode      128KB
+0x130000       0x14FFFF        QE Firmware     128KB
+
+
+For more details, please refer to T1024QDS Reference Manual and access
+website www.freescale.com and Freescale QorIQ SDK Infocenter document.
diff --git a/board/freescale/t102xqds/ddr.c b/board/freescale/t102xqds/ddr.c
new file mode 100644 (file)
index 0000000..46fc64e
--- /dev/null
@@ -0,0 +1,170 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <hwconfig.h>
+#include <asm/mmu.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/fsl_law.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct board_specific_parameters {
+       u32 n_ranks;
+       u32 datarate_mhz_high;
+       u32 rank_gb;
+       u32 clk_adjust;
+       u32 wrlvl_start;
+       u32 wrlvl_ctl_2;
+       u32 wrlvl_ctl_3;
+};
+
+/*
+ * datarate_mhz_high values need to be in ascending order
+ */
+static const struct board_specific_parameters udimm0[] = {
+       /*
+        * memory controller 0
+        *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl |
+        * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |
+        */
+#if defined(CONFIG_SYS_FSL_DDR4)
+       {2,  1666,  0,  4,  7,  0x0808090B,  0x0C0D0E0A,},
+       {2,  1900,  0,  4,  6,  0x08080A0C,  0x0D0E0F0A,},
+       {1,  1666,  0,  4,  6,  0x0708090B,  0x0C0D0E09,},
+       {1,  1900,  0,  4,  6,  0x08080A0C,  0x0D0E0F0A,},
+       {1,  2200,  0,  4,  7,  0x08090A0D,  0x0F0F100C,},
+#elif defined(CONFIG_SYS_FSL_DDR3)
+       {2,  833,   0,  4,  6,  0x06060607,  0x08080807,},
+       {2,  1350,  0,  4,  7,  0x0708080A,  0x0A0B0C09,},
+       {2,  1666,  0,  4,  7,  0x0808090B,  0x0C0D0E0A,},
+       {1,  833,   0,  4,  6,  0x06060607,  0x08080807,},
+       {1,  1350,  0,  4,  7,  0x0708080A,  0x0A0B0C09,},
+       {1,  1666,  0,  4,  7,  0x0808090B,  0x0C0D0E0A,},
+#else
+#error DDR type not defined
+#endif
+       {}
+};
+
+static const struct board_specific_parameters *udimms[] = {
+       udimm0,
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+                          dimm_params_t *pdimm,
+                          unsigned int ctrl_num)
+{
+       const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+       ulong ddr_freq;
+       struct cpu_type *cpu = gd->arch.cpu;
+
+       if (ctrl_num > 2) {
+               printf("Not supported controller number %d\n", ctrl_num);
+               return;
+       }
+       if (!pdimm->n_ranks)
+               return;
+
+       pbsp = udimms[0];
+
+       /* Get clk_adjust according to the board ddr freqency and n_banks
+        * specified in board_specific_parameters table.
+        */
+       ddr_freq = get_ddr_freq(0) / 1000000;
+       while (pbsp->datarate_mhz_high) {
+               if (pbsp->n_ranks == pdimm->n_ranks &&
+                   (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
+                       if (ddr_freq <= pbsp->datarate_mhz_high) {
+                               popts->clk_adjust = pbsp->clk_adjust;
+                               popts->wrlvl_start = pbsp->wrlvl_start;
+                               popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+                               popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+                               goto found;
+                       }
+                       pbsp_highest = pbsp;
+               }
+               pbsp++;
+       }
+
+       if (pbsp_highest) {
+               printf("Error: board specific timing not found\n");
+               printf("for data rate %lu MT/s\n", ddr_freq);
+               printf("Trying to use the highest speed (%u) parameters\n",
+                      pbsp_highest->datarate_mhz_high);
+               popts->clk_adjust = pbsp_highest->clk_adjust;
+               popts->wrlvl_start = pbsp_highest->wrlvl_start;
+               popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+               popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+       } else {
+               panic("DIMM is not supported by this board");
+       }
+found:
+       debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
+             pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
+       debug("\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, ",
+             pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2);
+       debug("wrlvl_ctrl_3 0x%x\n", pbsp->wrlvl_ctl_3);
+
+       /*
+        * Factors to consider for half-strength driver enable:
+        *      - number of DIMMs installed
+        */
+       popts->half_strength_driver_enable = 1;
+       /*
+        * Write leveling override
+        */
+       popts->wrlvl_override = 1;
+       popts->wrlvl_sample = 0xf;
+
+       /*
+        * rtt and rtt_wr override
+        */
+       popts->rtt_override = 0;
+
+       /* Enable ZQ calibration */
+       popts->zq_en = 1;
+
+       /* DHC_EN =1, ODT = 75 Ohm */
+#ifdef CONFIG_SYS_FSL_DDR4
+       popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
+       popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
+                         DDR_CDR2_VREF_OVRD(70);       /* Vref = 70% */
+#else
+       popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
+       popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+#endif
+
+       /* T1023 supports max DDR bus 32bit width, T1024 supports DDR 64bit,
+        * set DDR bus width to 32bit for T1023
+        */
+       if (cpu->soc_ver == SVR_T1023)
+               popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;
+
+#ifdef CONFIG_FORCE_DDR_DATA_BUS_WIDTH_32
+       /* for DDR bus 32bit test on T1024 */
+       popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;
+#endif
+}
+
+phys_size_t initdram(int board_type)
+{
+       phys_size_t dram_size;
+
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
+       puts("Initializing....using SPD\n");
+
+       dram_size = fsl_ddr_sdram();
+       dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+       dram_size *= 0x100000;
+#else
+       /* DDR has been initialised by first stage boot loader */
+       dram_size =  fsl_ddr_sdram_size();
+#endif
+       return dram_size;
+}
diff --git a/board/freescale/t102xqds/eth_t102xqds.c b/board/freescale/t102xqds/eth_t102xqds.c
new file mode 100644 (file)
index 0000000..7723f58
--- /dev/null
@@ -0,0 +1,442 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * Shengzhou Liu <Shengzhou.Liu@freescale.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <malloc.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <miiphy.h>
+#include <phy.h>
+#include <asm/fsl_dtsec.h>
+#include <asm/fsl_serdes.h>
+#include "../common/qixis.h"
+#include "../common/fman.h"
+#include "t102xqds_qixis.h"
+
+#define EMI_NONE       0xFFFFFFFF
+#define EMI1_RGMII1    0
+#define EMI1_RGMII2    1
+#define EMI1_SLOT1     2
+#define EMI1_SLOT2     3
+#define EMI1_SLOT3     4
+#define EMI1_SLOT4     5
+#define EMI1_SLOT5     6
+#define EMI2           7
+
+static int mdio_mux[NUM_FM_PORTS];
+
+static const char * const mdio_names[] = {
+       "T1024QDS_MDIO_RGMII1",
+       "T1024QDS_MDIO_RGMII2",
+       "T1024QDS_MDIO_SLOT1",
+       "T1024QDS_MDIO_SLOT2",
+       "T1024QDS_MDIO_SLOT3",
+       "T1024QDS_MDIO_SLOT4",
+       "T1024QDS_MDIO_SLOT5",
+       "T1024QDS_MDIO_10GC",
+       "NULL",
+};
+
+/* Map SerDes1 4 lanes to default slot, will be initialized dynamically */
+static u8 lane_to_slot[] = {2, 3, 4, 5};
+
+static const char *t1024qds_mdio_name_for_muxval(u8 muxval)
+{
+       return mdio_names[muxval];
+}
+
+struct mii_dev *mii_dev_for_muxval(u8 muxval)
+{
+       struct mii_dev *bus;
+       const char *name;
+
+       if (muxval > EMI2)
+               return NULL;
+
+       name = t1024qds_mdio_name_for_muxval(muxval);
+
+       if (!name) {
+               printf("No bus for muxval %x\n", muxval);
+               return NULL;
+       }
+
+       bus = miiphy_get_dev_by_name(name);
+
+       if (!bus) {
+               printf("No bus by name %s\n", name);
+               return NULL;
+       }
+
+       return bus;
+}
+
+struct t1024qds_mdio {
+       u8 muxval;
+       struct mii_dev *realbus;
+};
+
+static void t1024qds_mux_mdio(u8 muxval)
+{
+       u8 brdcfg4;
+
+       if (muxval < 7) {
+               brdcfg4 = QIXIS_READ(brdcfg[4]);
+               brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
+               brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
+               QIXIS_WRITE(brdcfg[4], brdcfg4);
+       }
+}
+
+static int t1024qds_mdio_read(struct mii_dev *bus, int addr, int devad,
+                             int regnum)
+{
+       struct t1024qds_mdio *priv = bus->priv;
+
+       t1024qds_mux_mdio(priv->muxval);
+
+       return priv->realbus->read(priv->realbus, addr, devad, regnum);
+}
+
+static int t1024qds_mdio_write(struct mii_dev *bus, int addr, int devad,
+                              int regnum, u16 value)
+{
+       struct t1024qds_mdio *priv = bus->priv;
+
+       t1024qds_mux_mdio(priv->muxval);
+
+       return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
+}
+
+static int t1024qds_mdio_reset(struct mii_dev *bus)
+{
+       struct t1024qds_mdio *priv = bus->priv;
+
+       return priv->realbus->reset(priv->realbus);
+}
+
+static int t1024qds_mdio_init(char *realbusname, u8 muxval)
+{
+       struct t1024qds_mdio *pmdio;
+       struct mii_dev *bus = mdio_alloc();
+
+       if (!bus) {
+               printf("Failed to allocate t1024qds MDIO bus\n");
+               return -1;
+       }
+
+       pmdio = malloc(sizeof(*pmdio));
+       if (!pmdio) {
+               printf("Failed to allocate t1024qds private data\n");
+               free(bus);
+               return -1;
+       }
+
+       bus->read = t1024qds_mdio_read;
+       bus->write = t1024qds_mdio_write;
+       bus->reset = t1024qds_mdio_reset;
+       sprintf(bus->name, t1024qds_mdio_name_for_muxval(muxval));
+
+       pmdio->realbus = miiphy_get_dev_by_name(realbusname);
+
+       if (!pmdio->realbus) {
+               printf("No bus with name %s\n", realbusname);
+               free(bus);
+               free(pmdio);
+               return -1;
+       }
+
+       pmdio->muxval = muxval;
+       bus->priv = pmdio;
+       return mdio_register(bus);
+}
+
+void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
+                             enum fm_port port, int offset)
+{
+       struct fixed_link f_link;
+
+       if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_RGMII) {
+               if (port == FM1_DTSEC3) {
+                       fdt_set_phy_handle(fdt, compat, addr, "rgmii_phy2");
+                       fdt_setprop(fdt, offset, "phy-connection-type",
+                                   "rgmii", 5);
+                       fdt_status_okay_by_alias(fdt, "emi1_rgmii1");
+               }
+       } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
+               if (port == FM1_DTSEC1) {
+                       fdt_set_phy_handle(fdt, compat, addr,
+                                          "sgmii_vsc8234_phy_s5");
+               } else if (port == FM1_DTSEC2) {
+                       fdt_set_phy_handle(fdt, compat, addr,
+                                          "sgmii_vsc8234_phy_s4");
+               }
+       } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) {
+               if (port == FM1_DTSEC3) {
+                       fdt_set_phy_handle(fdt, compat, addr,
+                                          "sgmii_aqr105_phy_s3");
+               }
+       } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) {
+               switch (port) {
+               case FM1_DTSEC1:
+                       fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p1");
+                       break;
+               case FM1_DTSEC2:
+                       fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p2");
+                       break;
+               case FM1_DTSEC3:
+                       fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p3");
+                       break;
+               case FM1_DTSEC4:
+                       fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p4");
+                       break;
+               default:
+                       break;
+               }
+               fdt_delprop(fdt, offset, "phy-connection-type");
+               fdt_setprop(fdt, offset, "phy-connection-type", "qsgmii", 6);
+               fdt_status_okay_by_alias(fdt, "emi1_slot2");
+       } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
+               /* XFI interface */
+               f_link.phy_id = port;
+               f_link.duplex = 1;
+               f_link.link_speed = 10000;
+               f_link.pause = 0;
+               f_link.asym_pause = 0;
+               /* no PHY for XFI */
+               fdt_delprop(fdt, offset, "phy-handle");
+               fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
+               fdt_setprop(fdt, offset, "phy-connection-type", "xgmii", 5);
+       }
+}
+
+void fdt_fixup_board_enet(void *fdt)
+{
+}
+
+/*
+ * This function reads RCW to check if Serdes1{A:D} is configured
+ * to slot 1/2/3/4/5 and update the lane_to_slot[] array accordingly
+ */
+static void initialize_lane_to_slot(void)
+{
+       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
+                               FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+
+       srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+       switch (srds_s1) {
+       case 0x46:
+       case 0x47:
+               lane_to_slot[1] = 2;
+               break;
+       default:
+               break;
+       }
+}
+
+int board_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_FMAN_ENET)
+       int i, idx, lane, slot, interface;
+       struct memac_mdio_info dtsec_mdio_info;
+       struct memac_mdio_info tgec_mdio_info;
+       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       u32 srds_s1;
+
+       srds_s1 = in_be32(&gur->rcwsr[4]) &
+                                       FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+       srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+       initialize_lane_to_slot();
+
+       /* Initialize the mdio_mux array so we can recognize empty elements */
+       for (i = 0; i < NUM_FM_PORTS; i++)
+               mdio_mux[i] = EMI_NONE;
+
+       dtsec_mdio_info.regs =
+               (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+
+       dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+       /* Register the 1G MDIO bus */
+       fm_memac_mdio_init(bis, &dtsec_mdio_info);
+
+       tgec_mdio_info.regs =
+               (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
+       tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
+
+       /* Register the 10G MDIO bus */
+       fm_memac_mdio_init(bis, &tgec_mdio_info);
+
+       /* Register the muxing front-ends to the MDIO buses */
+       t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
+       t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
+       t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
+       t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
+       t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
+       t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
+       t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
+       t1024qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
+
+       /* Set the two on-board RGMII PHY address */
+       fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
+       fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR);
+
+       switch (srds_s1) {
+       case 0xd5:
+       case 0xd6:
+               /* QSGMII in Slot2 */
+               fm_info_set_phy_address(FM1_DTSEC1, 0x8);
+               fm_info_set_phy_address(FM1_DTSEC2, 0x9);
+               fm_info_set_phy_address(FM1_DTSEC3, 0xa);
+               fm_info_set_phy_address(FM1_DTSEC4, 0xb);
+               break;
+       case 0x95:
+       case 0x99:
+               /*
+                * XFI does not need a PHY to work, but to avoid U-boot use
+                * default PHY address which is zero to a MAC when it found
+                * a MAC has no PHY address, we give a PHY address to XFI
+                * MAC, and should not use a real XAUI PHY address, since
+                * MDIO can access it successfully, and then MDIO thinks the
+                * XAUI card is used for the XFI MAC, which will cause error.
+                */
+               fm_info_set_phy_address(FM1_10GEC1, 4);
+               fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
+               break;
+       case 0x6f:
+               /* SGMII in Slot3, Slot4, Slot5 */
+               fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_AQ_PHY_ADDR_S5);
+               fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_AQ_PHY_ADDR_S4);
+               fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR);
+               break;
+       case 0x7f:
+               fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_AQ_PHY_ADDR_S5);
+               fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_AQ_PHY_ADDR_S4);
+               fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_AQ_PHY_ADDR_S3);
+               break;
+       case 0x47:
+               fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
+               break;
+       case 0x77:
+               fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
+               fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_AQ_PHY_ADDR_S3);
+               break;
+       case 0x5a:
+               fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
+               break;
+       case 0x6a:
+               fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
+               fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR);
+               break;
+       case 0x5b:
+               fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
+               fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
+               break;
+       case 0x6b:
+               fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
+               fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
+               fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR);
+               break;
+       default:
+               break;
+       }
+
+       for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+               idx = i - FM1_DTSEC1;
+               interface = fm_info_get_enet_if(i);
+               switch (interface) {
+               case PHY_INTERFACE_MODE_SGMII:
+               case PHY_INTERFACE_MODE_SGMII_2500:
+               case PHY_INTERFACE_MODE_QSGMII:
+                       if (interface == PHY_INTERFACE_MODE_SGMII) {
+                               lane = serdes_get_first_lane(FSL_SRDS_1,
+                                               SGMII_FM1_DTSEC1 + idx);
+                       } else if (interface == PHY_INTERFACE_MODE_SGMII_2500) {
+                               lane = serdes_get_first_lane(FSL_SRDS_1,
+                                               SGMII_2500_FM1_DTSEC1 + idx);
+                       } else {
+                               lane = serdes_get_first_lane(FSL_SRDS_1,
+                                               QSGMII_FM1_A);
+                       }
+
+                       if (lane < 0)
+                               break;
+
+                       slot = lane_to_slot[lane];
+                       debug("FM1@DTSEC%u expects SGMII in slot %u\n",
+                             idx + 1, slot);
+                       if (QIXIS_READ(present2) & (1 << (slot - 1)))
+                               fm_disable_port(i);
+
+                       switch (slot) {
+                       case 2:
+                               mdio_mux[i] = EMI1_SLOT2;
+                               fm_info_set_mdio(i, mii_dev_for_muxval(
+                                                mdio_mux[i]));
+                               break;
+                       case 3:
+                               mdio_mux[i] = EMI1_SLOT3;
+                               fm_info_set_mdio(i, mii_dev_for_muxval(
+                                                mdio_mux[i]));
+                               break;
+                       case 4:
+                               mdio_mux[i] = EMI1_SLOT4;
+                               fm_info_set_mdio(i, mii_dev_for_muxval(
+                                                mdio_mux[i]));
+                               break;
+                       case 5:
+                               mdio_mux[i] = EMI1_SLOT5;
+                               fm_info_set_mdio(i, mii_dev_for_muxval(
+                                                mdio_mux[i]));
+                               break;
+                       }
+                       break;
+               case PHY_INTERFACE_MODE_RGMII:
+                       if (i == FM1_DTSEC3)
+                               mdio_mux[i] = EMI1_RGMII2;
+                       else if (i == FM1_DTSEC4)
+                               mdio_mux[i] = EMI1_RGMII1;
+                       fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+                       break;
+               default:
+                       break;
+               }
+       }
+
+       for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
+               idx = i - FM1_10GEC1;
+               switch (fm_info_get_enet_if(i)) {
+               case PHY_INTERFACE_MODE_XGMII:
+                       lane = serdes_get_first_lane(FSL_SRDS_1,
+                                                    XFI_FM1_MAC1 + idx);
+                       if (lane < 0)
+                               break;
+                       mdio_mux[i] = EMI2;
+                       fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+                       break;
+               default:
+                       break;
+               }
+       }
+
+       cpu_eth_init(bis);
+#endif /* CONFIG_FMAN_ENET */
+
+       return pci_eth_init(bis);
+}
diff --git a/board/freescale/t102xqds/law.c b/board/freescale/t102xqds/law.c
new file mode 100644 (file)
index 0000000..b1c9d01
--- /dev/null
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+#ifndef CONFIG_SYS_NO_FLASH
+       SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
+#endif
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+       SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+       SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+#endif
+#ifdef QIXIS_BASE_PHYS
+       SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+       SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+       SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/t102xqds/pci.c b/board/freescale/t102xqds/pci.c
new file mode 100644 (file)
index 0000000..7369289
--- /dev/null
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/fsl_serdes.h>
+
+void pci_init_board(void)
+{
+       fsl_pcie_init_board(0);
+}
+
+void pci_of_setup(void *blob, bd_t *bd)
+{
+       FT_FSL_PCI_SETUP;
+}
diff --git a/board/freescale/t102xqds/spl.c b/board/freescale/t102xqds/spl.c
new file mode 100644 (file)
index 0000000..08aef6e
--- /dev/null
@@ -0,0 +1,151 @@
+/* Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <ns16550.h>
+#include <nand.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <spi_flash.h>
+#include "../common/qixis.h"
+#include "t102xqds_qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+phys_size_t get_effective_memsize(void)
+{
+       return CONFIG_SYS_L3_SIZE;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+       u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+
+       switch (sysclk_conf & 0x0F) {
+       case QIXIS_SYSCLK_83:
+               return 83333333;
+       case QIXIS_SYSCLK_100:
+               return 100000000;
+       case QIXIS_SYSCLK_125:
+               return 125000000;
+       case QIXIS_SYSCLK_133:
+               return 133333333;
+       case QIXIS_SYSCLK_150:
+               return 150000000;
+       case QIXIS_SYSCLK_160:
+               return 160000000;
+       case QIXIS_SYSCLK_166:
+               return 166666666;
+       }
+       return 66666666;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+       u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
+
+       switch ((ddrclk_conf & 0x30) >> 4) {
+       case QIXIS_DDRCLK_100:
+               return 100000000;
+       case QIXIS_DDRCLK_125:
+               return 125000000;
+       case QIXIS_DDRCLK_133:
+               return 133333333;
+       }
+       return 66666666;
+}
+
+void board_init_f(ulong bootflag)
+{
+       u32 plat_ratio, sys_clk, ccb_clk;
+       ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+#if defined(CONFIG_PPC_T1040) && defined(CONFIG_SPL_NAND_BOOT)
+       /*
+        * There is T1040 SoC issue where NOR, FPGA are inaccessible during
+        * NAND boot because IFC signals > IFC_AD7 are not enabled.
+        * This workaround changes RCW source to make all signals enabled.
+        */
+       u32 porsr1, pinctl;
+#define FSL_CORENET_CCSR_PORSR1_RCW_MASK        0xFF800000
+
+       porsr1 = in_be32(&gur->porsr1);
+       pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000);
+       out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl);
+#endif
+
+       /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
+       memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
+
+       /* Update GD pointer */
+       gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
+
+       console_init_f();
+
+       /* initialize selected port with appropriate baud rate */
+       sys_clk = get_board_sys_clk();
+       plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
+       ccb_clk = sys_clk * plat_ratio / 2;
+
+       NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+                    ccb_clk / 16 / CONFIG_BAUDRATE);
+
+#if defined(CONFIG_SPL_MMC_BOOT)
+       puts("\nSD boot...\n");
+#elif defined(CONFIG_SPL_SPI_BOOT)
+       puts("\nSPI boot...\n");
+#elif defined(CONFIG_SPL_NAND_BOOT)
+       puts("\nNAND boot...\n");
+#endif
+
+       relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+       bd_t *bd;
+
+       bd = (bd_t *)(gd + sizeof(gd_t));
+       memset(bd, 0, sizeof(bd_t));
+       gd->bd = bd;
+       bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
+       bd->bi_memsize = CONFIG_SYS_L3_SIZE;
+
+       probecpu();
+       get_clocks();
+       mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+                       CONFIG_SPL_RELOC_MALLOC_SIZE);
+
+#ifdef CONFIG_SPL_NAND_BOOT
+       nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+                           (uchar *)CONFIG_ENV_ADDR);
+#endif
+#ifdef CONFIG_SPL_MMC_BOOT
+       mmc_initialize(bd);
+       mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+                          (uchar *)CONFIG_ENV_ADDR);
+#endif
+#ifdef CONFIG_SPL_SPI_BOOT
+       spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+                          (uchar *)CONFIG_ENV_ADDR);
+#endif
+
+       gd->env_addr  = (ulong)(CONFIG_ENV_ADDR);
+       gd->env_valid = 1;
+
+       i2c_init_all();
+
+       gd->ram_size = initdram(0);
+
+#ifdef CONFIG_SPL_MMC_BOOT
+       mmc_boot();
+#elif defined(CONFIG_SPL_SPI_BOOT)
+       spi_boot();
+#elif defined(CONFIG_SPL_NAND_BOOT)
+       nand_boot();
+#endif
+}
diff --git a/board/freescale/t102xqds/t1024_pbi.cfg b/board/freescale/t102xqds/t1024_pbi.cfg
new file mode 100644 (file)
index 0000000..7b9e9b0
--- /dev/null
@@ -0,0 +1,26 @@
+#PBI commands
+#Initialize CPC1
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+#Configure CPC1 as 256KB SRAM
+09010100 00000000
+09010104 fffc0007
+09010f00 08000000
+09010000 80000000
+#Configure LAW for CPC1
+09000cd0 00000000
+09000cd4 fffc0000
+09000cd8 81000011
+#Configure alternate space
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Configure SPI controller
+09110000 80000403
+09110020 2d170008
+09110024 00100008
+09110028 00100008
+0911002c 00100008
+#Flush PBL data
+091380c0 000FFFFF
diff --git a/board/freescale/t102xqds/t1024_rcw.cfg b/board/freescale/t102xqds/t1024_rcw.cfg
new file mode 100644 (file)
index 0000000..4b8f719
--- /dev/null
@@ -0,0 +1,10 @@
+# single-source clock:Sys_Clock = DDR_Refclock = Diff_Sysclk = 100 MHz
+# Core/DDR/Platform/FMan = 1400MHz/1600MT/s/400MHz/700MHz
+
+# PBL preamble and RCW header for T1024QDS
+aa55aa55 010e0100
+# Serdes protocol 0x6F
+0810000e 00000000 00000000 00000000
+37800001 00000012 e8104000 21000000
+00000000 00000000 00000000 00030810
+00000000 036c5a00 00000000 00000006
diff --git a/board/freescale/t102xqds/t102xqds.c b/board/freescale/t102xqds/t102xqds.c
new file mode 100644 (file)
index 0000000..97ef95a
--- /dev/null
@@ -0,0 +1,321 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <netdev.h>
+#include <linux/compiler.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <fm_eth.h>
+#include <hwconfig.h>
+#include <asm/mpc85xx_gpio.h>
+#include "../common/qixis.h"
+#include "t102xqds.h"
+#include "t102xqds_qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+       char buf[64];
+       struct cpu_type *cpu = gd->arch.cpu;
+       static const char *const freq[] = {"100", "125", "156.25", "100.0"};
+       int clock;
+       u8 sw = QIXIS_READ(arch);
+
+       printf("Board: %sQDS, ", cpu->name);
+       printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4);
+       printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1);
+
+#ifdef CONFIG_SDCARD
+       puts("SD/MMC\n");
+#elif CONFIG_SPIFLASH
+       puts("SPI\n");
+#else
+       sw = QIXIS_READ(brdcfg[0]);
+       sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
+
+       if (sw < 0x8)
+               printf("vBank: %d\n", sw);
+       else if (sw == 0x8)
+               puts("PromJet\n");
+       else if (sw == 0x9)
+               puts("NAND\n");
+       else if (sw == 0x15)
+               printf("IFC Card\n");
+       else
+               printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
+#endif
+
+       printf("FPGA: v%d (%s), build %d",
+              (int)QIXIS_READ(scver), qixis_read_tag(buf),
+              (int)qixis_read_minor());
+       /* the timestamp string contains "\n" at the end */
+       printf(" on %s", qixis_read_time(buf));
+
+       puts("SERDES Reference: ");
+       sw = QIXIS_READ(brdcfg[2]);
+       clock = (sw >> 6) & 3;
+       printf("Clock1=%sMHz ", freq[clock]);
+       clock = (sw >> 4) & 3;
+       printf("Clock2=%sMHz\n", freq[clock]);
+
+       return 0;
+}
+
+int select_i2c_ch_pca9547(u8 ch)
+{
+       int ret;
+
+       ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+       if (ret) {
+               puts("PCA: failed to select proper channel\n");
+               return ret;
+       }
+
+       return 0;
+}
+
+static int board_mux_lane_to_slot(void)
+{
+       ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       u32 srds_prtcl_s1;
+       u8 brdcfg9;
+
+       srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
+                               FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+       srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+
+       brdcfg9 = QIXIS_READ(brdcfg[9]);
+       QIXIS_WRITE(brdcfg[9], brdcfg9 | BRDCFG9_XFI_TX_DISABLE);
+
+       switch (srds_prtcl_s1) {
+       case 0:
+               /* SerDes1 is not enabled */
+               break;
+       case 0xd5:
+       case 0x5b:
+       case 0x6b:
+       case 0x77:
+       case 0x6f:
+       case 0x7f:
+               QIXIS_WRITE(brdcfg[12], 0x8c);
+               break;
+       case 0x40:
+               QIXIS_WRITE(brdcfg[12], 0xfc);
+               break;
+       case 0xd6:
+       case 0x5a:
+       case 0x6a:
+       case 0x56:
+               QIXIS_WRITE(brdcfg[12], 0x88);
+               break;
+       case 0x47:
+               QIXIS_WRITE(brdcfg[12], 0xcc);
+               break;
+       case 0x46:
+               QIXIS_WRITE(brdcfg[12], 0xc8);
+               break;
+       case 0x95:
+       case 0x99:
+               brdcfg9 &= ~BRDCFG9_XFI_TX_DISABLE;
+               QIXIS_WRITE(brdcfg[9], brdcfg9);
+               QIXIS_WRITE(brdcfg[12], 0x8c);
+               break;
+       case 0x116:
+               QIXIS_WRITE(brdcfg[12], 0x00);
+               break;
+       case 0x115:
+       case 0x119:
+       case 0x129:
+       case 0x12b:
+               /* Aurora, PCIe, SGMII, SATA */
+               QIXIS_WRITE(brdcfg[12], 0x04);
+               break;
+       default:
+               printf("WARNING: unsupported for SerDes Protocol %d\n",
+                      srds_prtcl_s1);
+               return -1;
+       }
+
+       return 0;
+}
+
+#ifdef CONFIG_PPC_T1024
+static void board_mux_setup(void)
+{
+       u8 brdcfg15;
+
+       brdcfg15 = QIXIS_READ(brdcfg[15]);
+       brdcfg15 &= ~BRDCFG15_DIUSEL_MASK;
+
+       if (hwconfig_arg_cmp("pin_mux", "tdm")) {
+               /* Route QE_TDM multiplexed signals to TDM Riser slot */
+               QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_TDM);
+               QIXIS_WRITE(brdcfg[13], BRDCFG13_TDM_INTERFACE << 2);
+       } else if (hwconfig_arg_cmp("pin_mux", "ucc")) {
+               /* to UCC (ProfiBus) interface */
+               QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_UCC);
+       } else if (hwconfig_arg_cmp("pin_mux", "hdmi")) {
+               /* to DVI (HDMI) encoder */
+               QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_HDMI);
+       } else if (hwconfig_arg_cmp("pin_mux", "lcd")) {
+               /* to DFP (LCD) encoder */
+               QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_LCDFM |
+                           BRDCFG15_LCDPD | BRDCFG15_DIUSEL_LCD);
+       }
+}
+#endif
+
+int board_early_init_r(void)
+{
+#ifdef CONFIG_SYS_FLASH_BASE
+       const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+       int flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+       /*
+        * Remap Boot flash + PROMJET region to caching-inhibited
+        * so that flash can be erased properly.
+        */
+
+       /* Flush d-cache and invalidate i-cache of any FLASH data */
+       flush_dcache();
+       invalidate_icache();
+
+       if (flash_esel == -1) {
+               /* very unlikely unless something is messed up */
+               puts("Error: Could not find TLB for FLASH BASE\n");
+               flash_esel = 2; /* give our best effort to continue */
+       } else {
+               /* invalidate existing TLB entry for flash + promjet */
+               disable_tlb(flash_esel);
+       }
+
+       set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+               MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+               0, flash_esel, BOOKE_PAGESZ_256M, 1);
+#endif
+       set_liodns();
+#ifdef CONFIG_SYS_DPAA_QBMAN
+       setup_portals();
+#endif
+       select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+       board_mux_lane_to_slot();
+       return 0;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+       u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+
+       switch (sysclk_conf & 0x0F) {
+       case QIXIS_SYSCLK_64:
+               return 64000000;
+       case QIXIS_SYSCLK_83:
+               return 83333333;
+       case QIXIS_SYSCLK_100:
+               return 100000000;
+       case QIXIS_SYSCLK_125:
+               return 125000000;
+       case QIXIS_SYSCLK_133:
+               return 133333333;
+       case QIXIS_SYSCLK_150:
+               return 150000000;
+       case QIXIS_SYSCLK_160:
+               return 160000000;
+       case QIXIS_SYSCLK_166:
+               return 166666666;
+       }
+       return 66666666;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+       u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
+
+       switch ((ddrclk_conf & 0x30) >> 4) {
+       case QIXIS_DDRCLK_100:
+               return 100000000;
+       case QIXIS_DDRCLK_125:
+               return 125000000;
+       case QIXIS_DDRCLK_133:
+               return 133333333;
+       }
+       return 66666666;
+}
+
+#define NUM_SRDS_PLL   2
+int misc_init_r(void)
+{
+#ifdef CONFIG_PPC_T1024
+       board_mux_setup();
+#endif
+       return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+       phys_addr_t base;
+       phys_size_t size;
+
+       ft_cpu_setup(blob, bd);
+
+       base = getenv_bootm_low();
+       size = getenv_bootm_size();
+
+       fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_PCI
+       pci_of_setup(blob, bd);
+#endif
+
+       fdt_fixup_liodn(blob);
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+       fdt_fixup_dr_usb(blob, bd);
+#endif
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+       fdt_fixup_fman_ethernet(blob);
+       fdt_fixup_board_enet(blob);
+#endif
+
+       return 0;
+}
+
+void qixis_dump_switch(void)
+{
+       int i, nr_of_cfgsw;
+
+       QIXIS_WRITE(cms[0], 0x00);
+       nr_of_cfgsw = QIXIS_READ(cms[1]);
+
+       puts("DIP switch settings dump:\n");
+       for (i = 1; i <= nr_of_cfgsw; i++) {
+               QIXIS_WRITE(cms[0], i);
+               printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
+       }
+}
+
+#ifdef CONFIG_DEEP_SLEEP
+void board_mem_sleep_setup(void)
+{
+       /* does not provide HW signals for power management */
+       QIXIS_WRITE(pwr_ctl[1], (QIXIS_READ(pwr_ctl[1]) & ~0x2));
+       /* Disable MCKE isolation */
+       gpio_set_value(2, 0);
+       udelay(1);
+}
+#endif
diff --git a/board/freescale/t102xqds/t102xqds.h b/board/freescale/t102xqds/t102xqds.h
new file mode 100644 (file)
index 0000000..64ff623
--- /dev/null
@@ -0,0 +1,14 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __T102x_QDS_H__
+#define __T102x_QDS_H__
+
+void fdt_fixup_board_enet(void *blob);
+void pci_of_setup(void *blob, bd_t *bd);
+int select_i2c_ch_pca9547(u8 ch);
+
+#endif
diff --git a/board/freescale/t102xqds/t102xqds_qixis.h b/board/freescale/t102xqds/t102xqds_qixis.h
new file mode 100644 (file)
index 0000000..ad83f03
--- /dev/null
@@ -0,0 +1,61 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __T1024QDS_QIXIS_H__
+#define __T1024QDS_QIXIS_H__
+
+/* Definitions of QIXIS Registers for T1024/T1023 QDS */
+
+/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
+#define BRDCFG4_EMISEL_MASK            0xE0
+#define BRDCFG4_EMISEL_SHIFT           5
+
+/* BRDCFG5[0:1] controls routing and use of I2C3 & I2C4 ports*/
+#define BRDCFG5_IMX_MASK               0xC0
+#define BRDCFG5_IMX_DIU                        0x80
+
+#define BRDCFG9_XFI_TX_DISABLE         0x10
+
+/* BRDCFG13[0:5] TDM configuration and setup */
+#define BRDCFG13_TDM_MASK              0xfc
+#define BRDCFG13_TDM_INTERFACE         0x37
+#define BRDCFG13_HDLC_LOOPBACK         0x29
+#define BRDCFG13_TDM_LOOPBACK          0x31
+
+/* BRDCFG15[3] controls LCD Panel Powerdown */
+#define BRDCFG15_LCDFM                 0x20
+#define BRDCFG15_LCDPD                 0x10
+#define BRDCFG15_LCDPD_MASK            0x10
+#define BRDCFG15_LCDPD_ENABLED         0x00
+
+/* BRDCFG15[6:7] controls DIU MUX selction*/
+#define BRDCFG15_DIUSEL_MASK           0x03
+#define BRDCFG15_DIUSEL_HDMI           0x00
+#define BRDCFG15_DIUSEL_LCD            0x01
+#define BRDCFG15_DIUSEL_UCC            0x10
+#define BRDCFG15_DIUSEL_TDM            0x11
+
+/* SYSCLK */
+#define QIXIS_SYSCLK_66                        0x0
+#define QIXIS_SYSCLK_83                        0x1
+#define QIXIS_SYSCLK_100               0x2
+#define QIXIS_SYSCLK_125               0x3
+#define QIXIS_SYSCLK_133               0x4
+#define QIXIS_SYSCLK_150               0x5
+#define QIXIS_SYSCLK_160               0x6
+#define QIXIS_SYSCLK_166               0x7
+#define QIXIS_SYSCLK_64                        0x8
+
+/* DDRCLK */
+#define QIXIS_DDRCLK_66                        0x0
+#define QIXIS_DDRCLK_100               0x1
+#define QIXIS_DDRCLK_125               0x2
+#define QIXIS_DDRCLK_133               0x3
+
+
+#define QIXIS_SRDS1CLK_122             0x5a
+#define QIXIS_SRDS1CLK_125             0x5e
+#endif
diff --git a/board/freescale/t102xqds/tlb.c b/board/freescale/t102xqds/tlb.c
new file mode 100644 (file)
index 0000000..409e173
--- /dev/null
@@ -0,0 +1,117 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+       /* TLB 0 - for temp stack in cache */
+       SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+                     CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+                     MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                     0, 0, BOOKE_PAGESZ_4K, 0),
+       SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+                     CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+                     MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                     0, 0, BOOKE_PAGESZ_4K, 0),
+       SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+                     CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+                     MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                     0, 0, BOOKE_PAGESZ_4K, 0),
+       SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+                     CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+                     MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                     0, 0, BOOKE_PAGESZ_4K, 0),
+
+       /* TLB 1 */
+       /* *I*** - Covers boot page */
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+       /*
+        * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the
+        * SRAM is at 0xfffc0000, it covered the 0xfffff000.
+        */
+       SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 0, BOOKE_PAGESZ_256K, 1),
+#else
+       SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 0, BOOKE_PAGESZ_4K, 1),
+#endif
+
+       /* *I*G* - CCSRBAR */
+       SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 1, BOOKE_PAGESZ_16M, 1),
+
+       /* *I*G* - Flash, localbus */
+       /* This will be changed to *I*G* after relocation to RAM. */
+       SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+                     MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+                     0, 2, BOOKE_PAGESZ_256M, 1),
+
+#ifndef CONFIG_SPL_BUILD
+       /* *I*G* - PCI */
+       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 3, BOOKE_PAGESZ_1G, 1),
+
+       /* *I*G* - PCI I/O */
+       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 4, BOOKE_PAGESZ_256K, 1),
+
+       /* Bman/Qman */
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+       SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+                     MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                     0, 5, BOOKE_PAGESZ_16M, 1),
+       SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
+                     CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 6, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+       SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+                     MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                     0, 7, BOOKE_PAGESZ_16M, 1),
+       SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
+                     CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 8, BOOKE_PAGESZ_16M, 1),
+#endif
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+       SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 9, BOOKE_PAGESZ_4M, 1),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE
+       SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 10, BOOKE_PAGESZ_64K, 1),
+#endif
+#ifdef QIXIS_BASE
+       SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 11, BOOKE_PAGESZ_4K, 1),
+#endif
+
+#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
+       SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+                     MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                     0, 12, BOOKE_PAGESZ_1G, 1),
+       SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
+                     CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
+                     MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                     0, 13, BOOKE_PAGESZ_1G, 1)
+#endif
+       /* entry 14 and 15 has been used hard coded, they will be disabled
+        * in cpu_init_f, so if needed more, will use entry 16 later.
+        */
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/configs/T1024QDS_D4_SECURE_BOOT_defconfig b/configs/T1024QDS_D4_SECURE_BOOT_defconfig
new file mode 100644 (file)
index 0000000..d86ae05
--- /dev/null
@@ -0,0 +1,4 @@
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SYS_FSL_DDR4,SECURE_BOOT"
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T102XQDS=y
diff --git a/configs/T1024QDS_NAND_defconfig b/configs/T1024QDS_NAND_defconfig
new file mode 100644 (file)
index 0000000..acbbe43
--- /dev/null
@@ -0,0 +1,5 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
++S:CONFIG_PPC=y
++S:CONFIG_MPC85xx=y
++S:CONFIG_TARGET_T102XQDS=y
diff --git a/configs/T1024QDS_SDCARD_defconfig b/configs/T1024QDS_SDCARD_defconfig
new file mode 100644 (file)
index 0000000..82c6e19
--- /dev/null
@@ -0,0 +1,5 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
++S:CONFIG_PPC=y
++S:CONFIG_MPC85xx=y
++S:CONFIG_TARGET_T102XQDS=y
diff --git a/configs/T1024QDS_SECURE_BOOT_defconfig b/configs/T1024QDS_SECURE_BOOT_defconfig
new file mode 100644 (file)
index 0000000..b932619
--- /dev/null
@@ -0,0 +1,4 @@
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SECURE_BOOT"
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T102XQDS=y
diff --git a/configs/T1024QDS_SPIFLASH_defconfig b/configs/T1024QDS_SPIFLASH_defconfig
new file mode 100644 (file)
index 0000000..52aeac7
--- /dev/null
@@ -0,0 +1,5 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
++S:CONFIG_PPC=y
++S:CONFIG_MPC85xx=y
++S:CONFIG_TARGET_T102XQDS=y
diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h
new file mode 100644 (file)
index 0000000..d24e06e
--- /dev/null
@@ -0,0 +1,936 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/*
+ * T1024/T1023 QDS board configuration file
+ */
+
+#ifndef __T1024QDS_H
+#define __T1024QDS_H
+
+/* High Level Configuration Options */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOOKE
+#define CONFIG_E500                    /* BOOKE e500 family */
+#define CONFIG_E500MC                  /* BOOKE e500mc family */
+#define CONFIG_SYS_BOOK3E_HV           /* Category E.HV supported */
+#define CONFIG_MP                      /* support multiple processors */
+#define CONFIG_PHYS_64BIT
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP                1
+#define CONFIG_SYS_NUM_ADDR_MAP        64      /* number of TLB1 entries */
+#endif
+
+#define CONFIG_SYS_FSL_CPC             /* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC             CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_FSL_IFC                 /* Enable IFC Support */
+
+#define CONFIG_FSL_LAW                 /* Use common FSL init code */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_DEEP_SLEEP
+#define CONFIG_SILENT_CONSOLE
+
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_rcw.cfg
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET              "u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_FSL_LAW                 /* Use common FSL init code */
+#define CONFIG_SYS_TEXT_BASE           0x00201000
+#define CONFIG_SPL_TEXT_BASE           0xFFFD8000
+#define CONFIG_SPL_PAD_TO              0x40000
+#define CONFIG_SPL_MAX_SIZE            0x28000
+#define RESET_VECTOR_OFFSET            0x27FFC
+#define BOOT_PAGE_OFFSET               0x27000
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_SKIP_RELOCATE
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#define CONFIG_SYS_NO_FLASH
+#endif
+
+#ifdef CONFIG_NAND
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SYS_NAND_U_BOOT_SIZE    (768 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST     0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_START   0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS    (256 << 10)
+#define CONFIG_SYS_LDSCRIPT    "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#define CONFIG_SPL_NAND_BOOT
+#endif
+
+#ifdef CONFIG_SPIFLASH
+#define CONFIG_RESET_VECTOR_ADDRESS            0x200FFC
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_MINIMAL
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE       (768 << 10)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST                (0x00200000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_START      (0x00200000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS       (256 << 10)
+#define CONFIG_SYS_LDSCRIPT            "arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#endif
+#define CONFIG_SPL_SPI_BOOT
+#endif
+
+#ifdef CONFIG_SDCARD
+#define CONFIG_RESET_VECTOR_ADDRESS            0x200FFC
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_MMC_MINIMAL
+#define CONFIG_SYS_MMC_U_BOOT_SIZE     (768 << 10)
+#define CONFIG_SYS_MMC_U_BOOT_DST      (0x00200000)
+#define CONFIG_SYS_MMC_U_BOOT_START    (0x00200000)
+#define CONFIG_SYS_MMC_U_BOOT_OFFS     (260 << 10)
+#define CONFIG_SYS_LDSCRIPT            "arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#endif
+#define CONFIG_SPL_MMC_BOOT
+#endif
+
+#endif /* CONFIG_RAMBOOT_PBL */
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE   0xeff40000
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS    0xeffffffc
+#endif
+
+#ifndef CONFIG_SYS_NO_FLASH
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#endif
+
+/* PCIe Boot - Master */
+#define CONFIG_SRIO_PCIE_BOOT_MASTER
+/*
+ * for slave u-boot IMAGE instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
+#else
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
+#endif
+/*
+ * for slave UCODE and ENV instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS         0x3ffe00000ull
+#else
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0xffe00000
+#endif
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE     0x40000 /* 256K */
+/* slave core release by master*/
+#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
+#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
+
+/* PCIe Boot - Slave */
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
+               (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
+/* Set 1M boot space for PCIe boot */
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS       \
+               (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#define CONFIG_SYS_NO_FLASH
+#endif
+
+#if defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS             0
+#define CONFIG_ENV_SPI_CS              0
+#define CONFIG_ENV_SPI_MAX_HZ          10000000
+#define CONFIG_ENV_SPI_MODE            0
+#define CONFIG_ENV_SIZE                        0x2000          /* 8KB */
+#define CONFIG_ENV_OFFSET              0x100000        /* 1MB */
+#define CONFIG_ENV_SECT_SIZE           0x10000
+#elif defined(CONFIG_SDCARD)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV         0
+#define CONFIG_ENV_SIZE                        0x2000
+#define CONFIG_ENV_OFFSET              (512 * 0x800)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE                        0x2000
+#define CONFIG_ENV_OFFSET              (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+#define CONFIG_ENV_IS_IN_REMOTE
+#define CONFIG_ENV_ADDR                0xffe20000
+#define CONFIG_ENV_SIZE                0x2000
+#elif defined(CONFIG_ENV_IS_NOWHERE)
+#define CONFIG_ENV_SIZE                0x2000
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR                (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE                0x2000
+#define CONFIG_ENV_SECT_SIZE   0x20000 /* 128K (one sector) */
+#endif
+
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+unsigned long get_board_ddr_clk(void);
+#endif
+
+#define CONFIG_SYS_CLK_FREQ    get_board_sys_clk()
+#define CONFIG_DDR_CLK_FREQ    get_board_ddr_clk()
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BACKSIDE_L2_CACHE
+#define CONFIG_SYS_INIT_L2CSR0         L2CSR0_L2E
+#define CONFIG_BTB                     /* toggle branch predition */
+#define CONFIG_DDR_ECC
+#ifdef CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE          0xdeadbeef
+#endif
+
+#define CONFIG_SYS_MEMTEST_START       0x00200000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END         0x00400000
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_PANIC_HANG      /* do not reset board on panic */
+
+/*
+ *  Config the L3 Cache as L3 SRAM
+ */
+#define CONFIG_SYS_INIT_L3_ADDR                0xFFFC0000
+#define CONFIG_SYS_L3_SIZE             (256 << 10)
+#define CONFIG_SPL_GD_ADDR             (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_ENV_ADDR                        (CONFIG_SPL_GD_ADDR + 4 * 1024)
+#endif
+#define CONFIG_SPL_RELOC_MALLOC_ADDR   (CONFIG_SPL_GD_ADDR + 12 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE   (30 << 10)
+#define CONFIG_SPL_RELOC_STACK         (CONFIG_SPL_GD_ADDR + 64 * 1024)
+#define CONFIG_SPL_RELOC_STACK_SIZE    (22 << 10)
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_DCSRBAR             0xf0000000
+#define CONFIG_SYS_DCSRBAR_PHYS                0xf00000000ull
+#endif
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM      0
+#define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE      0x00000000
+#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_DIMM_SLOTS_PER_CTLR     1
+#define CONFIG_CHIP_SELECTS_PER_CTRL   (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
+#define CONFIG_DDR_SPD
+#ifndef CONFIG_SYS_FSL_DDR4
+#define CONFIG_SYS_FSL_DDR3
+#endif
+
+#define CONFIG_SYS_SPD_BUS_NUM 0
+#define SPD_EEPROM_ADDRESS     0x51
+
+#define CONFIG_SYS_SDRAM_SIZE  4096    /* for fixed parameter use */
+
+/*
+ * IFC Definitions
+ */
+#define CONFIG_SYS_FLASH_BASE  0xe0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_FLASH_BASE_PHYS     (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+#else
+#define CONFIG_SYS_FLASH_BASE_PHYS     CONFIG_SYS_FLASH_BASE
+#endif
+
+#define CONFIG_SYS_NOR0_CSPR_EXT       (0xf)
+#define CONFIG_SYS_NOR0_CSPR   (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
+                               + 0x8000000) | \
+                               CSPR_PORT_SIZE_16 | \
+                               CSPR_MSEL_NOR | \
+                               CSPR_V)
+#define CONFIG_SYS_NOR1_CSPR_EXT       (0xf)
+#define CONFIG_SYS_NOR1_CSPR   (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+                               CSPR_PORT_SIZE_16 | \
+                               CSPR_MSEL_NOR | \
+                               CSPR_V)
+#define CONFIG_SYS_NOR_AMASK   IFC_AMASK(128*1024*1024)
+/* NOR Flash Timing Params */
+#define CONFIG_SYS_NOR_CSOR    CSOR_NAND_TRHZ_80
+#define CONFIG_SYS_NOR_FTIM0   (FTIM0_NOR_TACSE(0x4) | \
+                               FTIM0_NOR_TEADC(0x5) | \
+                               FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1   (FTIM1_NOR_TACO(0x35) | \
+                               FTIM1_NOR_TRAD_NOR(0x1A) |\
+                               FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2   (FTIM2_NOR_TCS(0x4) | \
+                               FTIM2_NOR_TCH(0x4) | \
+                               FTIM2_NOR_TWPH(0x0E) | \
+                               FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3   0x0
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS     45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS     2       /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT      1024    /* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT    60000   /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE_PHYS \
+                                       + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
+#define CONFIG_FSL_QIXIS       /* use common QIXIS code */
+#define QIXIS_BASE             0xffdf0000
+#ifdef CONFIG_PHYS_64BIT
+#define QIXIS_BASE_PHYS                (0xf00000000ull | QIXIS_BASE)
+#else
+#define QIXIS_BASE_PHYS                QIXIS_BASE
+#endif
+#define QIXIS_LBMAP_SWITCH             0x06
+#define QIXIS_LBMAP_MASK               0x0f
+#define QIXIS_LBMAP_SHIFT              0
+#define QIXIS_LBMAP_DFLTBANK           0x00
+#define QIXIS_LBMAP_ALTBANK            0x04
+#define QIXIS_RST_CTL_RESET            0x31
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE   0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START  0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE  0x08
+#define        QIXIS_RST_FORCE_MEM             0x01
+
+#define CONFIG_SYS_CSPR3_EXT   (0xf)
+#define CONFIG_SYS_CSPR3       (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
+                               | CSPR_PORT_SIZE_8 \
+                               | CSPR_MSEL_GPCM \
+                               | CSPR_V)
+#define CONFIG_SYS_AMASK3      IFC_AMASK(4*1024)
+#define CONFIG_SYS_CSOR3       0x0
+/* QIXIS Timing parameters for IFC CS3 */
+#define CONFIG_SYS_CS3_FTIM0           (FTIM0_GPCM_TACSE(0x0e) | \
+                                       FTIM0_GPCM_TEADC(0x0e) | \
+                                       FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CS3_FTIM1           (FTIM1_GPCM_TACO(0xff) | \
+                                       FTIM1_GPCM_TRAD(0x3f))
+#define CONFIG_SYS_CS3_FTIM2           (FTIM2_GPCM_TCS(0x0e) | \
+                                       FTIM2_GPCM_TCH(0x8) | \
+                                       FTIM2_GPCM_TWP(0x1f))
+#define CONFIG_SYS_CS3_FTIM3           0x0
+
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_BASE           0xff800000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_NAND_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_NAND_BASE)
+#else
+#define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
+#endif
+#define CONFIG_SYS_NAND_CSPR_EXT       (0xf)
+#define CONFIG_SYS_NAND_CSPR   (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+                               | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+                               | CSPR_MSEL_NAND        /* MSEL = NAND */ \
+                               | CSPR_V)
+#define CONFIG_SYS_NAND_AMASK  IFC_AMASK(64*1024)
+
+#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+                               | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
+                               | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
+                               | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
+                               | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
+                               | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
+                               | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0          (FTIM0_NAND_TCCST(0x07) | \
+                                       FTIM0_NAND_TWP(0x18)   | \
+                                       FTIM0_NAND_TWCHT(0x07) | \
+                                       FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1          (FTIM1_NAND_TADLE(0x32) | \
+                                       FTIM1_NAND_TWBE(0x39)  | \
+                                       FTIM1_NAND_TRR(0x0e)   | \
+                                       FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2          (FTIM2_NAND_TRAD(0x0f) | \
+                                       FTIM2_NAND_TREH(0x0a) | \
+                                       FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3          0x0
+
+#define CONFIG_SYS_NAND_DDR_LAW                11
+#define CONFIG_SYS_NAND_BASE_LIST      { CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE     (128 * 1024)
+
+#if defined(CONFIG_NAND)
+#define CONFIG_SYS_CSPR0_EXT           CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0               CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0              CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0               CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0           CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1           CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2           CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3           CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1_EXT           CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR1               CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK1              CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1               CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0           CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1           CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2           CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3           CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT           CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR2               CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK2              CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR2               CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS2_FTIM0           CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS2_FTIM1           CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS2_FTIM2           CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS2_FTIM3           CONFIG_SYS_NOR_FTIM3
+#else
+#define CONFIG_SYS_CSPR0_EXT           CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0               CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0              CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0               CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0           CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1           CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2           CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3           CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1_EXT           CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR1               CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK1              CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1               CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0           CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1           CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2           CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3           CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT           CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2               CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2              CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2               CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0           CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1           CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2           CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3           CONFIG_SYS_NAND_FTIM3
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE                CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE                CONFIG_SYS_TEXT_BASE
+#endif
+
+#if defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_HWCONFIG
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR       0xfdd00000      /* Initial L1 address */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH     0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW      0xfe0ec000
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+       ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+         CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#else
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS  0xfe0ec000 /* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
+#endif
+#define CONFIG_SYS_INIT_RAM_SIZE               0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_SIZE - \
+                                       GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN         (768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN          (10 * 1024 * 1024)
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX      1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE    1
+#define CONFIG_SYS_NS16550_CLK         (get_bus_freq(0)/2)
+
+#define CONFIG_SYS_BAUDRATE_TABLE      \
+       {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x11C500)
+#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x11C600)
+#define CONFIG_SYS_NS16550_COM3        (CONFIG_SYS_CCSRBAR+0x11D500)
+#define CONFIG_SYS_NS16550_COM4        (CONFIG_SYS_CCSRBAR+0x11D600)
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV   /* determine from environment */
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/* Video */
+#ifdef CONFIG_PPC_T1024                /* no DIU on T1023 */
+#define CONFIG_FSL_DIU_FB
+#ifdef CONFIG_FSL_DIU_FB
+#define CONFIG_FSL_DIU_CH7301
+#define CONFIG_SYS_DIU_ADDR    (CONFIG_SYS_CCSRBAR + 0x180000)
+#define CONFIG_VIDEO
+#define CONFIG_CMD_BMP
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+/*
+ * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
+ * disable empty flash sector detection, which is I/O-intensive.
+ */
+#undef CONFIG_SYS_FLASH_EMPTY_INFO
+#endif
+#endif
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE     /* enable fit_format_{error,warning}() */
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL             /* Use FSL common I2C driver */
+#define CONFIG_SYS_FSL_I2C_SPEED       50000   /* I2C speed in Hz */
+#define CONFIG_SYS_FSL_I2C_SLAVE       0x7F
+#define CONFIG_SYS_FSL_I2C2_SPEED      50000   /* I2C speed in Hz */
+#define CONFIG_SYS_FSL_I2C2_SLAVE      0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET      0x118000
+#define CONFIG_SYS_FSL_I2C2_OFFSET     0x118100
+
+#define I2C_MUX_PCA_ADDR               0x77
+#define I2C_MUX_PCA_ADDR_PRI           0x77 /* Primary Mux*/
+
+
+/* I2C bus multiplexer */
+#define I2C_MUX_CH_DEFAULT      0x8
+#define I2C_MUX_CH_DIU         0xC
+
+/* LDI/DVI Encoder for display */
+#define CONFIG_SYS_I2C_LDI_ADDR         0x38
+#define CONFIG_SYS_I2C_DVI_ADDR         0x75
+
+/*
+ * RTC configuration
+ */
+#define RTC
+#define CONFIG_RTC_DS3231      1
+#define CONFIG_SYS_I2C_RTC_ADDR        0x68
+
+/*
+ * eSPI - Enhanced SPI
+ */
+#define CONFIG_FSL_ESPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_SPI_FLASH_EON
+#endif
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH_BAR
+#define CONFIG_SF_DEFAULT_SPEED         10000000
+#define CONFIG_SF_DEFAULT_MODE   0
+
+/*
+ * General PCIe
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+#define CONFIG_PCI             /* Enable PCI/PCIE */
+#define CONFIG_PCIE1           /* PCIE controler 1 */
+#define CONFIG_PCIE2           /* PCIE controler 2 */
+#define CONFIG_PCIE3           /* PCIE controler 3 */
+#define CONFIG_FSL_PCI_INIT    /* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT   /* enable 64-bit PCI resources */
+#define CONFIG_PCI_INDIRECT_BRIDGE
+
+#ifdef CONFIG_PCI
+/* controller 1, direct to uli, tgtid 3, Base address 20000 */
+#ifdef CONFIG_PCIE1
+#define        CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
+#ifdef CONFIG_PHYS_64BIT
+#define        CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
+#define        CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
+#else
+#define CONFIG_SYS_PCIE1_MEM_BUS       0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS      0x80000000
+#endif
+#define CONFIG_SYS_PCIE1_MEM_SIZE      0x10000000      /* 256M */
+#define CONFIG_SYS_PCIE1_IO_VIRT       0xf8000000
+#define CONFIG_SYS_PCIE1_IO_BUS                0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_IO_PHYS       0xff8000000ull
+#else
+#define CONFIG_SYS_PCIE1_IO_PHYS       0xf8000000
+#endif
+#define CONFIG_SYS_PCIE1_IO_SIZE       0x00010000      /* 64k */
+#endif
+
+/* controller 2, Slot 2, tgtid 2, Base address 201000 */
+#ifdef CONFIG_PCIE2
+#define CONFIG_SYS_PCIE2_MEM_VIRT      0x90000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_MEM_BUS       0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS      0xc10000000ull
+#else
+#define CONFIG_SYS_PCIE2_MEM_BUS       0x90000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS      0x90000000
+#endif
+#define CONFIG_SYS_PCIE2_MEM_SIZE      0x10000000      /* 256M */
+#define CONFIG_SYS_PCIE2_IO_VIRT       0xf8010000
+#define CONFIG_SYS_PCIE2_IO_BUS                0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_IO_PHYS       0xff8010000ull
+#else
+#define CONFIG_SYS_PCIE2_IO_PHYS       0xf8010000
+#endif
+#define CONFIG_SYS_PCIE2_IO_SIZE       0x00010000      /* 64k */
+#endif
+
+/* controller 3, Slot 1, tgtid 1, Base address 202000 */
+#ifdef CONFIG_PCIE3
+#define CONFIG_SYS_PCIE3_MEM_VIRT      0xa0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE3_MEM_BUS       0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS      0xc20000000ull
+#else
+#define CONFIG_SYS_PCIE3_MEM_BUS       0xa0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS      0xa0000000
+#endif
+#define CONFIG_SYS_PCIE3_MEM_SIZE      0x10000000      /* 256M */
+#define CONFIG_SYS_PCIE3_IO_VIRT       0xf8020000
+#define CONFIG_SYS_PCIE3_IO_BUS                0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE3_IO_PHYS       0xff8020000ull
+#else
+#define CONFIG_SYS_PCIE3_IO_PHYS       0xf8020000
+#endif
+#define CONFIG_SYS_PCIE3_IO_SIZE       0x00010000      /* 64k */
+#endif
+
+#define CONFIG_PCI_PNP                 /* do pci plug-and-play */
+#define CONFIG_E1000
+#define CONFIG_PCI_SCAN_SHOW           /* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#endif /* CONFIG_PCI */
+
+/*
+ *SATA
+ */
+#define CONFIG_FSL_SATA_V2
+#ifdef CONFIG_FSL_SATA_V2
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+#define CONFIG_SYS_SATA_MAX_DEVICE     1
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1               CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS         FLAGS_DMA
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#endif
+
+/*
+ * USB
+ */
+#define CONFIG_HAS_FSL_DR_USB
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_CMD_EXT2
+#endif
+
+/*
+ * SDHC
+ */
+#define CONFIG_MMC
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR      CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* Qman/Bman */
+#ifndef CONFIG_NOBQFMAN
+#define CONFIG_SYS_DPAA_QBMAN          /* Support Q/Bman */
+#define CONFIG_SYS_BMAN_NUM_PORTALS    25
+#define CONFIG_SYS_BMAN_MEM_BASE       0xf4000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_BMAN_MEM_PHYS       0xff4000000ull
+#else
+#define CONFIG_SYS_BMAN_MEM_PHYS       CONFIG_SYS_BMAN_MEM_BASE
+#endif
+#define CONFIG_SYS_BMAN_MEM_SIZE       0x02000000
+#define CONFIG_SYS_QMAN_NUM_PORTALS    25
+#define CONFIG_SYS_QMAN_MEM_BASE       0xf6000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_QMAN_MEM_PHYS       0xff6000000ull
+#else
+#define CONFIG_SYS_QMAN_MEM_PHYS       CONFIG_SYS_QMAN_MEM_BASE
+#endif
+#define CONFIG_SYS_QMAN_MEM_SIZE       0x02000000
+
+#define CONFIG_SYS_DPAA_FMAN
+
+#define CONFIG_QE
+#define CONFIG_U_QE
+/* Default address of microcode for the Linux FMan driver */
+#if defined(CONFIG_SPIFLASH)
+/*
+ * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
+ * env, so we got 0x110000.
+ */
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
+#define CONFIG_SYS_FMAN_FW_ADDR        0x110000
+#define CONFIG_SYS_QE_FW_ADDR  0x130000
+#elif defined(CONFIG_SDCARD)
+/*
+ * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
+ * about 1MB (2048 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
+#define CONFIG_SYS_FMAN_FW_ADDR                (512 * 0x820)
+#define CONFIG_SYS_QE_FW_ADDR          (512 * 0x920)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
+#define CONFIG_SYS_FMAN_FW_ADDR                (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_SYS_QE_FW_ADDR          (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+/*
+ * Slave has no ucode locally, it can fetch this from remote. When implementing
+ * in two corenet boards, slave's ucode could be stored in master's memory
+ * space, the address can be mapped from slave TLB->slave LAW->
+ * slave SRIO or PCIE outbound window->master inbound window->
+ * master LAW->the ucode address in master's memory space.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
+#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
+#else
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_FMAN_FW_ADDR                0xEFF00000
+#define CONFIG_SYS_QE_FW_ADDR          0xEFE00000
+#endif
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH   0x10000
+#define CONFIG_SYS_FDT_PAD             (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+#endif /* CONFIG_NOBQFMAN */
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+#define CONFIG_PHYLIB_10G
+#define CONFIG_PHY_VITESSE
+#define CONFIG_PHY_REALTEK
+#define CONFIG_PHY_TERANETICS
+#define RGMII_PHY1_ADDR                0x1
+#define RGMII_PHY2_ADDR                0x2
+#define SGMII_CARD_AQ_PHY_ADDR_S3 0x3
+#define SGMII_CARD_AQ_PHY_ADDR_S4 0x4
+#define SGMII_CARD_AQ_PHY_ADDR_S5 0x5
+#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
+#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
+#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
+#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
+#endif
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_MII             /* MII PHY management */
+#define CONFIG_ETHPRIME                "FM1@DTSEC4"
+#define CONFIG_PHY_GIGE                /* Include GbE speed/duplex detection */
+#endif
+
+/*
+ * Dynamic MTD Partition support with mtdparts
+ */
+#ifndef CONFIG_SYS_NO_FLASH
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_FLASH_CFI_MTD
+#define MTDIDS_DEFAULT    "nor0=fe8000000.nor,nand0=fff800000.flash," \
+                         "spi0=spife110000.0"
+#define MTDPARTS_DEFAULT  "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
+                         "128k(dtb),96m(fs),-(user);"\
+                         "fff800000.flash:2m(uboot),9m(kernel),"\
+                         "128k(dtb),96m(fs),-(user);spife110000.0:" \
+                         "2m(uboot),9m(kernel),128k(dtb),-(user)"
+#endif
+
+/*
+ * Environment
+ */
+#define CONFIG_LOADS_ECHO              /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE   /* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ERRATA
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SETEXPR
+
+#ifdef CONFIG_PCI
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP                    /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING                 /* Command-line editing */
+#define CONFIG_AUTO_COMPLETE                   /* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR   0x2000000       /* default load address */
+#define CONFIG_SYS_PROMPT      "=> "           /* Monitor Command Prompt */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CBSIZE      1024            /* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE      256             /* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS     16              /* max number of command args */
+#define CONFIG_SYS_BARGSIZE  CONFIG_SYS_CBSIZE  /* Boot Argument Buffer Size */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ   (64 << 20)      /* Initial map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE   230400  /* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ROOTPATH                "/opt/nfsroot"
+#define CONFIG_BOOTFILE                "uImage"
+#define CONFIG_UBOOTPATH       "u-boot.bin" /* U-Boot image on TFTP server */
+#define CONFIG_LOADADDR                1000000 /* default location for tftp, bootm */
+#define CONFIG_BOOTDELAY       10      /* -1 disables auto-boot */
+#define CONFIG_BAUDRATE                115200
+#define __USB_PHY_TYPE         utmi
+
+
+#define        CONFIG_EXTRA_ENV_SETTINGS                               \
+       "hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0"  \
+       "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
+       "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
+       "ramdiskfile=t1024qds/ramdisk.uboot\0"                  \
+       "fdtfile=t1024qds/t1024qds.dtb\0"                       \
+       "netdev=eth0\0"                                         \
+       "video-mode=fslfb:1024x768-32@60,monitor=dvi\0"         \
+       "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
+       "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
+       "tftpflash=tftpboot $loadaddr $uboot && "               \
+       "protect off $ubootaddr +$filesize && "                 \
+       "erase $ubootaddr +$filesize && "                       \
+       "cp.b $loadaddr $ubootaddr $filesize && "               \
+       "protect on $ubootaddr +$filesize && "                  \
+       "cmp.b $loadaddr $ubootaddr $filesize\0"                \
+       "consoledev=ttyS0\0"                                    \
+       "ramdiskaddr=2000000\0"                                 \
+       "fdtaddr=d00000\0"                                      \
+       "bdev=sda3\0"
+
+#define CONFIG_LINUX                                   \
+       "setenv bootargs root=/dev/ram rw "             \
+       "console=$consoledev,$baudrate $othbootargs;"   \
+       "setenv ramdiskaddr 0x02000000;"                \
+       "setenv fdtaddr 0x00c00000;"                    \
+       "setenv loadaddr 0x1000000;"                    \
+       "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND                  \
+       "setenv bootargs root=/dev/nfs rw "     \
+       "nfsroot=$serverip:$rootpath "          \
+       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+       "console=$consoledev,$baudrate $othbootargs;"   \
+       "tftp $loadaddr $bootfile;"             \
+       "tftp $fdtaddr $fdtfile;"               \
+       "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND     CONFIG_LINUX
+
+#ifdef CONFIG_SECURE_BOOT
+#include <asm/fsl_secure_boot.h>
+#endif
+
+#endif /* __T1024QDS_H */