ppc/85xx: Map boot page guarded for MP boot

We already map the page cache-inhibited.  There is no reason we
shouldn't also be marking it guarded to prevent speculative accesses.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/board/freescale/mpc8572ds/tlb.c b/board/freescale/mpc8572ds/tlb.c
index d832f89742fe8cafec4234055e46e8e512ee3c91..6a2a0b57f530f179bdedc005cd9e13cf21444e59 100644 (file)
--- a/board/freescale/mpc8572ds/tlb.c
+++ b/board/freescale/mpc8572ds/tlb.c
@@ -44,7 +44,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
        /* TLB 1 */
        /* *I*** - Covers boot page */
        SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
-                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 0, BOOKE_PAGESZ_4K, 1),
 
        /* *I*G* - CCSRBAR */

diff --git a/board/freescale/p1_p2_rdb/tlb.c b/board/freescale/p1_p2_rdb/tlb.c
index 0009913eaa8be77e385d2260fe227ce823bd7d01..93d0bf7bc7e2b97fa67da7dc47eccc1e6e06cfa7 100644 (file)
--- a/board/freescale/p1_p2_rdb/tlb.c
+++ b/board/freescale/p1_p2_rdb/tlb.c
@@ -44,7 +44,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
        /* TLB 1 */
        /* *I*** - Covers boot page */
        SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
-                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
+                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                        0, 0, BOOKE_PAGESZ_4K, 1),
 
        /* *I*G* - CCSRBAR */

diff --git a/board/freescale/p2020ds/tlb.c b/board/freescale/p2020ds/tlb.c
index b2e562aeb10f2aa97e751be7dc5563a05e523b4c..36ad086d0893a7de1df4ff2af1622e537e671a67 100644 (file)
--- a/board/freescale/p2020ds/tlb.c
+++ b/board/freescale/p2020ds/tlb.c
@@ -47,7 +47,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
        /* TLB 1 */
        /* *I*** - Covers boot page */
        SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
-                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 0, BOOKE_PAGESZ_4K, 1),
 
        /* *I*G* - CCSRBAR */

diff --git a/cpu/mpc85xx/mp.c b/cpu/mpc85xx/mp.c
index 8568f5dbae0406f6d8d65837319f5959a4d2aba5..6530cb176b4564858ee83823ddc6812a8aaaf821 100644 (file)
--- a/cpu/mpc85xx/mp.c
+++ b/cpu/mpc85xx/mp.c
@@ -312,7 +312,7 @@ void setup_mp(void)
                disable_tlb(i);
 
                set_tlb(1, CONFIG_BPTR_VIRT_ADDR, bootpg, /* tlb, epn, rpn */
-                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, /* perms, wimge */
+                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
                        0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */
 
                memcpy((void *)CONFIG_BPTR_VIRT_ADDR, (void *)fixup, 4096);

diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S
index 55eca728697cab223770baa20e2bfdd02f096ced..00c4c547fd91e45cc6e0f036f8421687aa2557ad 100644 (file)
--- a/cpu/mpc85xx/release.S
+++ b/cpu/mpc85xx/release.S
@@ -166,8 +166,8 @@ __secondary_start_page:
        lis     r11,(MAS1_VALID|MAS1_IPROT)@h
        ori     r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
        mtspr   SPRN_MAS1,r11
-       oris    r11,r13,(MAS2_I)@h
-       ori     r11,r13,(MAS2_I)@l
+       oris    r11,r13,(MAS2_I|MAS2_G)@h
+       ori     r11,r13,(MAS2_I|MAS2_G)@l
        mtspr   SPRN_MAS2,r11
        oris    r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@h
        ori     r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@l