board/T4240qds:Fix TLB and LAW size of NAND flash

The internal SRAM of Freescale's IFC NAND machine is of 64K and controller's
Address Mask Registers is initialised with the same.

So Update TLB and LAW size of NAND flash accordingly.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

diff --git a/board/freescale/t4qds/law.c b/board/freescale/t4qds/law.c
index 5debcf612a86f4e618c6b2875a7c3c7f972fcb81..6f2c5c86b4d2dc0d8d83734a33021ff1cdc0a91d 100644 (file)
--- a/board/freescale/t4qds/law.c
+++ b/board/freescale/t4qds/law.c
@@ -40,7 +40,7 @@ struct law_entry law_table[] = {
        SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
 #endif
 #ifdef CONFIG_SYS_NAND_BASE_PHYS
-       SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
+       SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
 #endif
 };
 

diff --git a/board/freescale/t4qds/tlb.c b/board/freescale/t4qds/tlb.c
index 078a6e415cdb993282468d347099ba95b43570bd..80eb511e1d301f409eb36c06a1a8f6da869b6a98 100644 (file)
--- a/board/freescale/t4qds/tlb.c
+++ b/board/freescale/t4qds/tlb.c
@@ -125,7 +125,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
         */
        SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
                        MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-                       0, 16, BOOKE_PAGESZ_1M, 1),
+                       0, 16, BOOKE_PAGESZ_64K, 1),
 #endif
        SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,